soc_maker 0.1.1

data/core_lib/cores/or1200_rel2/01_or1200.yaml

@@ -0,0 +1,208 @@
+SOCM_CORE
+name: OpenRISC 1200
+description: OpenRISC CPU
+id: or1200,rel2
+license: LGPL
+licensefile: 
+author: 
+authormail: 
+vccmd: svn co http://opencores.org/ocsvn/openrisc/openrisc/tags/or1200/rel2/rtl rtl
+toplevel: or1200_top
+interfaces:
+  :clmode: SOCM_IFC
+    name: single
+    dir: 1
+    id: single,1
+    ports:
+      :clmode_i: SOCM_PORT
+        len: 2
+        spc_ref: single
+
+  :pic_ints: SOCM_IFC
+    name: single
+    dir: 1
+    id: single,1
+    ports:
+      :pic_ints_i: SOCM_PORT
+        len: 20
+        spc_ref: single
+
+  :clk: SOCM_IFC
+    name: clk
+    dir: 1
+    id: clk,1
+    ports:
+      :clk_i: SOCM_PORT
+        len: 1
+        spc_ref: clk
+
+  :rst: SOCM_IFC
+    name: rst
+    dir: 1
+    id: rst,1
+    ports:
+      :rst_i: SOCM_PORT
+        len: 1
+        spc_ref: rst
+
+  :wb_instruction: SOCM_IFC
+    name: wishbone_ma
+    dir: 1
+    id: wishbone_ma,b3
+    ports:
+      :iwb_clk_i: SOCM_PORT
+        spc_ref: clk
+        len:  1
+      :iwb_rst_i: SOCM_PORT
+        spc_ref: rst
+        len:  1
+      :iwb_cyc_o: SOCM_PORT
+        spc_ref: cyc
+        len:  1
+      :iwb_stb_o: SOCM_PORT
+        spc_ref: stb
+        len:  1
+      :iwb_adr_o: SOCM_PORT
+        spc_ref: adr
+        len:  32
+      :iwb_sel_o: SOCM_PORT
+        spc_ref: sel
+        len:  4
+      :iwb_we_o: SOCM_PORT
+        spc_ref: we
+        len:  1
+      :iwb_dat_o: SOCM_PORT
+        spc_ref: dat_i
+        len:  32
+      :iwb_dat_i: SOCM_PORT
+        spc_ref: dat_o
+        len:  32
+      :iwb_ack_i: SOCM_PORT
+        spc_ref: ack
+        len:  1
+      :iwb_err_i: SOCM_PORT
+        spc_ref: err
+        len:  1
+      :iwb_rty_i: SOCM_PORT
+        spc_ref: rty
+        len:  1
+
+  :wb_data: SOCM_IFC
+    name: wishbone_ma
+    dir: 1
+    id: wishbone_ma,b3
+    ports:
+      :dwb_clk_i: SOCM_PORT
+        spc_ref: clk
+        len:  1
+      :dwb_rst_i: SOCM_PORT
+        spc_ref: rst
+        len:  1
+      :dwb_cyc_o: SOCM_PORT
+        spc_ref: cyc
+        len:  1
+      :dwb_stb_o: SOCM_PORT
+        spc_ref: stb
+        len:  1
+      :dwb_adr_o: SOCM_PORT
+        spc_ref: adr
+        len:  32
+      :dwb_sel_o: SOCM_PORT
+        spc_ref: sel
+        len:  4
+      :dwb_we_o: SOCM_PORT
+        spc_ref: we
+        len:  1
+      :dwb_dat_o: SOCM_PORT
+        spc_ref: dat_i
+        len:  32
+      :dwb_dat_i: SOCM_PORT
+        spc_ref: dat_o
+        len:  32
+      :dwb_ack_i: SOCM_PORT
+        spc_ref: ack
+        len:  1
+      :dwb_err_i: SOCM_PORT
+        spc_ref: err
+        len:  1
+      :dwb_rty_i: SOCM_PORT
+        spc_ref: rty
+        len:  1
+
+  :ext_debug: SOCM_IFC
+    name: debug
+    dir: 1
+    id: debug,1
+    ports:
+      :dbg_stall_i: SOCM_PORT
+        spc_ref: dbg_stall 
+        len: 1
+      :dbg_ewt_i: SOCM_PORT
+        len: 1
+        spc_ref: dbg_ewt   
+      :dbg_lss_o: SOCM_PORT
+        len: 4
+        spc_ref: dbg_lss   
+      :dbg_is_o: SOCM_PORT
+        len: 2
+        spc_ref: dbg_iso   
+      :dbg_wp_o: SOCM_PORT
+        len: 11
+        spc_ref: dbg_wpo    
+      :dbg_bp_o: SOCM_PORT
+        len: 1
+        spc_ref: dbg_bpo   
+      :dbg_stb_i: SOCM_PORT
+        len: 1
+        spc_ref: dbg_stb   
+      :dbg_we_i: SOCM_PORT
+        len: 1
+        spc_ref: dbg_we    
+      :dbg_adr_i: SOCM_PORT
+        len: 32
+        spc_ref: dbg_adr   
+      :dbg_dat_i: SOCM_PORT
+        len: 32
+        spc_ref: dbg_dat_o
+      :dbg_dat_o: SOCM_PORT
+        len: 32
+        spc_ref: dbg_dat_i 
+      :dbg_ack_o: SOCM_PORT
+        len: 1
+        spc_ref: dbg_ack   
+
+  :pow_man: SOCM_IFC
+    name: or_power_management
+    dir: 1
+    id: or_power_management,1
+    ports:
+      :pm_cpustall_i: SOCM_PORT
+         len: 1
+         spc_ref: pm_cpustall
+      :pm_clksd_o: SOCM_PORT
+         len: 4
+         spc_ref: pm_clksd
+      :pm_dc_gate_o: SOCM_PORT
+         len: 1
+         spc_ref: pm_dc_gate
+      :pm_ic_gate_o: SOCM_PORT
+         len: 1
+         spc_ref: pm_ic_gate
+      :pm_dmmu_gate_o: SOCM_PORT
+         len: 1
+         spc_ref: pm_dmmu_gate
+      :pm_immu_gate_o: SOCM_PORT
+         len: 1
+         spc_ref: pm_immu_gate
+      :pm_tt_gate_o: SOCM_PORT
+         len: 1
+         spc_ref: pm_tt_gate
+      :pm_cpu_gate_o: SOCM_PORT
+         len: 1
+         spc_ref: pm_cpu_gate
+      :pm_wakeup_o: SOCM_PORT
+         len: 1
+         spc_ref: pm_wakeup
+      :pm_lvolt_o: SOCM_PORT
+         len: 1
+         spc_ref: pm_lvolt

data/core_lib/cores/or1200_rel2/02_or1200_files.yaml

@@ -0,0 +1,421 @@
+hdlfiles:
+  :alu: SOCM_HDL_FILE
+    use_syn: true
+    use_sim: true
+    type: verilog
+    path: rtl/verilog/or1200_alu.v            
+
+  :tlb: SOCM_HDL_FILE
+    use_syn: true
+    use_sim: true
+    type: verilog
+    path: rtl/verilog/or1200_dmmu_tlb.v       
+
+  :ram: SOCM_HDL_FILE
+    use_syn: true
+    use_sys_sim: true
+    use_mod_sim: true
+    type: vhdl
+    path: rtl/verilog/or1200_ic_ram.v    
+
+  :operandmuxes: SOCM_HDL_FILE
+    use_syn: true
+    use_sys_sim: true
+    use_mod_sim: true
+    type: vhdl
+    path: rtl/verilog/or1200_operandmuxes.v      
+
+  :spram_1024: SOCM_HDL_FILE
+    use_syn: true
+    use_sys_sim: true
+    use_mod_sim: true
+    type: vhdl
+    path: rtl/verilog/or1200_spram_1024x32.v     
+
+  :spram_64_22: SOCM_HDL_FILE
+    use_syn: true
+    use_sys_sim: true
+    use_mod_sim: true
+    type: vhdl
+    path: rtl/verilog/or1200_spram_64x22.v
+
+  :amultp2: SOCM_HDL_FILE
+    use_syn: true
+    use_sys_sim: true
+    use_mod_sim: true
+    type: vhdl
+    path: rtl/verilog/or1200_amultp2_32x32.v  
+
+  :dmmu_top: SOCM_HDL_FILE
+    use_syn: true
+    use_sys_sim: true
+    use_mod_sim: true
+    type: vhdl
+    path: rtl/verilog/or1200_dmmu_top.v       
+
+  :ic_tag: SOCM_HDL_FILE
+    use_syn: true
+    use_sys_sim: true
+    use_mod_sim: true
+    type: vhdl
+    path: rtl/verilog/or1200_ic_tag.v    
+
+  :pic: SOCM_HDL_FILE
+    use_syn: true
+    use_sys_sim: true
+    use_mod_sim: true
+    type: vhdl
+    path: rtl/verilog/or1200_pic.v               
+
+  :spram_1024_8: SOCM_HDL_FILE
+    use_syn: true
+    use_sys_sim: true
+    use_mod_sim: true
+    type: vhdl
+    path: rtl/verilog/or1200_spram_1024x8.v      
+
+  :spram_64_24: SOCM_HDL_FILE
+    use_syn: true
+    use_sys_sim: true
+    use_mod_sim: true
+    type: vhdl
+    path: rtl/verilog/or1200_spram_64x24.v
+
+  :cfgr: SOCM_HDL_FILE
+    use_syn: true
+    use_sys_sim: true
+    use_mod_sim: true
+    type: vhdl
+    path: rtl/verilog/or1200_cfgr.v           
+
+  :dpram_256_32: SOCM_HDL_FILE
+    use_syn: true
+    use_sys_sim: true
+    use_mod_sim: true
+    type: vhdl
+    path: rtl/verilog/or1200_dpram_256x32.v   
+
+  :ic_top: SOCM_HDL_FILE
+    use_syn: true
+    use_sys_sim: true
+    use_mod_sim: true
+    type: vhdl
+    path: rtl/verilog/or1200_ic_top.v    
+
+  :pm: SOCM_HDL_FILE
+    use_syn: true
+    use_sys_sim: true
+    use_mod_sim: true
+    type: vhdl
+    path: rtl/verilog/or1200_pm.v                
+
+  :spram_128_32: SOCM_HDL_FILE
+    use_syn: true
+    use_sys_sim: true
+    use_mod_sim: true
+    type: vhdl
+    path: rtl/verilog/or1200_spram_128x32.v      
+
+  :sprs: SOCM_HDL_FILE
+    use_syn: true
+    use_sys_sim: true
+    use_mod_sim: true
+    type: vhdl
+    path: rtl/verilog/or1200_sprs.v
+
+  :cpu: SOCM_HDL_FILE
+    use_syn: true
+    use_sys_sim: true
+    use_mod_sim: true
+    type: vhdl
+    path: rtl/verilog/or1200_cpu.v            
+
+  :dpram_32_32: SOCM_HDL_FILE
+    use_syn: true
+    use_sys_sim: true
+    use_mod_sim: true
+    type: vhdl
+    path: rtl/verilog/or1200_dpram_32x32.v    
+
+  :if: SOCM_HDL_FILE
+    use_syn: true
+    use_sys_sim: true
+    use_mod_sim: true
+    type: vhdl
+    path: rtl/verilog/or1200_if.v        
+
+  :qmem_top: SOCM_HDL_FILE
+    use_syn: true
+    use_sys_sim: true
+    use_mod_sim: true
+    type: vhdl
+    path: rtl/verilog/or1200_qmem_top.v          
+
+  :spram_2048_32: SOCM_HDL_FILE
+    use_syn: true
+    use_sys_sim: true
+    use_mod_sim: true
+    type: vhdl
+    path: rtl/verilog/or1200_spram_2048x32_bw.v  
+
+  :top: SOCM_HDL_FILE
+    use_syn: true
+    use_sys_sim: true
+    use_mod_sim: true
+    type: vhdl
+    path: rtl/verilog/or1200_top.v
+
+  :or1200_ctrl: SOCM_HDL_FILE
+    use_syn: true
+    use_sys_sim: true
+    use_mod_sim: true
+    type: vhdl
+    path: rtl/verilog/or1200_ctrl.v           
+
+  :du: SOCM_HDL_FILE
+    use_syn: true
+    use_sys_sim: true
+    use_mod_sim: true
+    type: vhdl
+    path: rtl/verilog/or1200_du.v             
+
+  :immu_tlb: SOCM_HDL_FILE
+    use_syn: true
+    use_sys_sim: true
+    use_mod_sim: true
+    type: vhdl
+    path: rtl/verilog/or1200_immu_tlb.v  
+
+  :reg2mem: SOCM_HDL_FILE
+    use_syn: true
+    use_sys_sim: true
+    use_mod_sim: true
+    type: vhdl
+    path: rtl/verilog/or1200_reg2mem.v           
+
+  :spram_2048_32: SOCM_HDL_FILE
+    use_syn: true
+    use_sys_sim: true
+    use_mod_sim: true
+    type: vhdl
+    path: rtl/verilog/or1200_spram_2048x32.v     
+
+  :tpram_32_32: SOCM_HDL_FILE
+    use_syn: true
+    use_sys_sim: true
+    use_mod_sim: true
+    type: vhdl
+    path: rtl/verilog/or1200_tpram_32x32.v
+
+  :dc_fsm: SOCM_HDL_FILE
+    use_syn: true
+    use_sys_sim: true
+    use_mod_sim: true
+    type: vhdl
+    path: rtl/verilog/or1200_dc_fsm.v         
+
+  :except: SOCM_HDL_FILE
+    use_syn: true
+    use_sys_sim: true
+    use_mod_sim: true
+    type: vhdl
+    path: rtl/verilog/or1200_except.v         
+
+  :immu_top: SOCM_HDL_FILE
+    use_syn: true
+    use_sys_sim: true
+    use_mod_sim: true
+    type: vhdl
+    path: rtl/verilog/or1200_immu_top.v  
+
+  :rfram_generic: SOCM_HDL_FILE
+    use_syn: true
+    use_sys_sim: true
+    use_mod_sim: true
+    type: vhdl
+    path: rtl/verilog/or1200_rfram_generic.v     
+
+  :spram_2048_8: SOCM_HDL_FILE
+    use_syn: true
+    use_sys_sim: true
+    use_mod_sim: true
+    type: vhdl
+    path: rtl/verilog/or1200_spram_2048x8.v      
+
+  :tt: SOCM_HDL_FILE
+    use_syn: true
+    use_sys_sim: true
+    use_mod_sim: true
+    type: vhdl
+    path: rtl/verilog/or1200_tt.v
+
+  :dc_ram: SOCM_HDL_FILE
+    use_syn: true
+    use_sys_sim: true
+    use_mod_sim: true
+    type: vhdl
+    path: rtl/verilog/or1200_dc_ram.v         
+
+  :freeze: SOCM_HDL_FILE
+    use_syn: true
+    use_sys_sim: true
+    use_mod_sim: true
+    type: vhdl
+    path: rtl/verilog/or1200_freeze.v         
+
+  :iwb_biu: SOCM_HDL_FILE
+    use_syn: true
+    use_sys_sim: true
+    use_mod_sim: true
+    type: vhdl
+    path: rtl/verilog/or1200_iwb_biu.v   
+
+  :rf: SOCM_HDL_FILE
+    use_syn: true
+    use_sys_sim: true
+    use_mod_sim: true
+    type: vhdl
+    path: rtl/verilog/or1200_rf.v                
+
+  :spram_256_21: SOCM_HDL_FILE
+    use_syn: true
+    use_sys_sim: true
+    use_mod_sim: true
+    type: vhdl
+    path: rtl/verilog/or1200_spram_256x21.v      
+
+  :wb_biu: SOCM_HDL_FILE
+    use_syn: true
+    use_sys_sim: true
+    use_mod_sim: true
+    type: vhdl
+    path: rtl/verilog/or1200_wb_biu.v
+
+  :dc_tag: SOCM_HDL_FILE
+    use_syn: true
+    use_sys_sim: true
+    use_mod_sim: true
+    type: vhdl
+    path: rtl/verilog/or1200_dc_tag.v         
+
+  :genpc: SOCM_HDL_FILE
+    use_syn: true
+    use_sys_sim: true
+    use_mod_sim: true
+    type: vhdl
+    path: rtl/verilog/or1200_genpc.v          
+
+  :lsu: SOCM_HDL_FILE
+    use_syn: true
+    use_sys_sim: true
+    use_mod_sim: true
+    type: vhdl
+    path: rtl/verilog/or1200_lsu.v       
+
+  :fifo: SOCM_HDL_FILE
+    use_syn: true
+    use_sys_sim: true
+    use_mod_sim: true
+    type: vhdl
+    path: rtl/verilog/or1200_sb_fifo.v           
+
+  :spram_32_24: SOCM_HDL_FILE
+    use_syn: true
+    use_sys_sim: true
+    use_mod_sim: true
+    type: vhdl
+    path: rtl/verilog/or1200_spram_32x24.v       
+
+  :wbmux: SOCM_HDL_FILE
+    use_syn: true
+    use_sys_sim: true
+    use_mod_sim: true
+    type: vhdl
+    path: rtl/verilog/or1200_wbmux.v
+
+  :dc_top: SOCM_HDL_FILE
+    use_syn: true
+    use_sys_sim: true
+    use_mod_sim: true
+    type: vhdl
+    path: rtl/verilog/or1200_dc_top.v         
+
+  :gmultp2_32_32: SOCM_HDL_FILE
+    use_syn: true
+    use_sys_sim: true
+    use_mod_sim: true
+    type: vhdl
+    path: rtl/verilog/or1200_gmultp2_32x32.v  
+
+  :mem2reg: SOCM_HDL_FILE
+    use_syn: true
+    use_sys_sim: true
+    use_mod_sim: true
+    type: vhdl
+    path: rtl/verilog/or1200_mem2reg.v   
+
+  :sb: SOCM_HDL_FILE
+    use_syn: true
+    use_sys_sim: true
+    use_mod_sim: true
+    type: vhdl
+    path: rtl/verilog/or1200_sb.v                
+
+  :spram_512_20: SOCM_HDL_FILE
+    use_syn: true
+    use_sys_sim: true
+    use_mod_sim: true
+    type: vhdl
+    path: rtl/verilog/or1200_spram_512x20.v      
+
+  :xcv_ram32_8d: SOCM_HDL_FILE
+    use_syn: true
+    use_sys_sim: true
+    use_mod_sim: true
+    type: vhdl
+    path: rtl/verilog/or1200_xcv_ram32x8d.v
+
+# Please note: the defines is automatically created
+# see or1200_defines.v.in
+
+# :defines: SOCM_HDL_FILE
+#   use_syn: true
+#   use_sys_sim: true
+#   use_mod_sim: true
+#   type: vhdl
+#   path: rtl/verilog/or1200_defines.v        
+
+  :ic_fsm: SOCM_HDL_FILE
+    use_syn: true
+    use_sys_sim: true
+    use_mod_sim: true
+    type: vhdl
+    path: rtl/verilog/or1200_ic_fsm.v         
+
+  :mult_mac: SOCM_HDL_FILE
+    use_syn: true
+    use_sys_sim: true
+    use_mod_sim: true
+    type: vhdl
+    path: rtl/verilog/or1200_mult_mac.v  
+
+  :spram_2014x32: SOCM_HDL_FILE
+    use_syn: true
+    use_sys_sim: true
+    use_mod_sim: true
+    type: vhdl
+    path: rtl/verilog/or1200_spram_1024x32_bw.v  
+
+  :spram_64_14: SOCM_HDL_FILE
+    use_syn: true
+    use_sys_sim: true
+    use_mod_sim: true
+    type: vhdl
+    path: rtl/verilog/or1200_spram_64x14.v       
+
+  :timescale: SOCM_HDL_FILE
+    use_syn: false
+    use_sys_sim: true
+    use_mod_sim: true
+    type: vhdl
+    path: rtl/verilog/timescale.v