rggen 0.7.2 → 0.8.0

data/sample/sample_1.sv

@@ -1,21 +1,21 @@
 module sample_1 (
-  input clk,
-  input rst_n,
+  input logic clk,
+  input logic rst_n,
   rggen_apb_if.slave apb_if,
-  output [15:0] o_bit_field_0_0,
-  input [15:0] i_bit_field_0_1,
-  output [31:0] o_bit_field_1_0,
-  input i_bit_field_2_0,
-  output o_bit_field_2_1
+  output logic [15:0] o_bit_field_0_0,
+  input logic [15:0] i_bit_field_0_1,
+  output logic [31:0] o_bit_field_1_0,
+  input logic i_bit_field_2_0,
+  output logic o_bit_field_2_1
 );
   rggen_register_if #(7, 32) register_if[3]();
   `define rggen_connect_bit_field_if(RIF, FIF, MSB, LSB) \
-    assign  FIF.read_access         = RIF.read_access; \
-    assign  FIF.write_access        = RIF.write_access; \
-    assign  FIF.write_data          = RIF.write_data[MSB:LSB]; \
-    assign  FIF.write_mask          = RIF.write_mask[MSB:LSB]; \
-    assign  RIF.value[MSB:LSB]      = FIF.value; \
-    assign  RIF.read_data[MSB:LSB]  = FIF.read_data;
+  assign  FIF.read_access         = RIF.read_access; \
+  assign  FIF.write_access        = RIF.write_access; \
+  assign  FIF.write_data          = RIF.write_data[MSB:LSB]; \
+  assign  FIF.write_mask          = RIF.write_mask[MSB:LSB]; \
+  assign  RIF.value[MSB:LSB]      = FIF.value; \
+  assign  RIF.read_data[MSB:LSB]  = FIF.read_data;
   rggen_host_if_apb #(
     .LOCAL_ADDRESS_WIDTH  (7),
     .DATA_WIDTH           (32),

data/sample/sample_setup.rb

@@ -8,13 +8,13 @@ define_list_item :register_block, :host_if, :bar do
   end
 end
 
-enable :global        , [:data_width, :address_width]
+enable :global        , [:data_width, :address_width, :array_port_format, :unfold_sv_interface_port]
 enable :register_block, [:name, :base_address]
 enable :register      , [:offset_address, :name, :array, :type, :uniquness_validator]
 enable :register      , :type, [:indirect, :external]
 enable :bit_field     , [:bit_assignment, :name, :type, :initial_value, :reference]
 enable :bit_field     , :type, [:rw, :ro, :w0c, :w1c, :w0s, :w1s, :rwl, :rwe, :foo, :reserved]
-enable :register_block, [:top_module, :clock_reset, :host_if, :irq_controller]
+enable :register_block, [:top_module, :clock_reset, :host_if]
 enable :register_block, :host_if, [:apb, :bar]
 enable :register      , :rtl_top
 enable :bit_field     , :rtl_top

data/setup/default.rb

@@ -1,10 +1,10 @@
-enable :global        , [:data_width, :address_width]
+enable :global        , [:data_width, :address_width, :array_port_format, :unfold_sv_interface_port]
 enable :register_block, [:name, :byte_size]
 enable :register      , [:offset_address, :name, :array, :type, :uniquness_validator]
 enable :register      , :type, [:indirect, :external]
 enable :bit_field     , [:bit_assignment, :name, :type, :initial_value, :reference]
 enable :bit_field     , :type, [:rw, :ro, :w0c, :w1c, :w0s, :w1s, :rwl, :rwe, :reserved]
-enable :register_block, [:rtl_top, :clock_reset, :host_if, :irq_controller]
+enable :register_block, [:rtl_top, :clock_reset, :host_if]
 enable :register_block, :host_if, [:apb, :axi4lite]
 enable :register      , :rtl_top
 enable :bit_field     , :rtl_top

metadata

@@ -1,14 +1,14 @@
 --- !ruby/object:Gem::Specification
 name: rggen
 version: !ruby/object:Gem::Version
-  version: 0.7.2
+  version: 0.8.0
 platform: ruby
 authors:
 - Taichi Ishitani
 autorequire: 
 bindir: bin
 cert_chain: []
-date: 2019-01-14 00:00:00.000000000 Z
+date: 2019-01-31 00:00:00.000000000 Z
 dependencies:
 - !ruby/object:Gem::Dependency
   name: erubi
@@ -163,7 +163,9 @@ files:
 - lib/rggen/builtins/bit_field/types/w0s_w1s.rb
 - lib/rggen/builtins/bit_field/types/wo.rb
 - lib/rggen/builtins/global/address_width.rb
+- lib/rggen/builtins/global/array_port_format.rb
 - lib/rggen/builtins/global/data_width.rb
+- lib/rggen/builtins/global/unfold_sv_interface_port.rb
 - lib/rggen/builtins/loaders/configuration/json_loader.rb
 - lib/rggen/builtins/loaders/configuration/yaml_loader.rb
 - lib/rggen/builtins/loaders/register_map/csv_loader.rb
@@ -198,11 +200,8 @@ files:
 - lib/rggen/builtins/register_block/host_ifs/apb.rb
 - lib/rggen/builtins/register_block/host_ifs/axi4lite.erb
 - lib/rggen/builtins/register_block/host_ifs/axi4lite.rb
-- lib/rggen/builtins/register_block/irq_controller.erb
-- lib/rggen/builtins/register_block/irq_controller.rb
 - lib/rggen/builtins/register_block/name.rb
 - lib/rggen/builtins/register_block/ral_package.rb
-- lib/rggen/builtins/register_block/rtl_top.erb
 - lib/rggen/builtins/register_block/rtl_top.rb
 - lib/rggen/builtins/register_block/sub_model_creator.rb
 - lib/rggen/commands.rb
@@ -243,16 +242,16 @@ files:
 - lib/rggen/core_components/rtl/setup.rb
 - lib/rggen/core_components/verilog_utility.rb
 - lib/rggen/core_components/verilog_utility/class_definition.rb
-- lib/rggen/core_components/verilog_utility/declaration.rb
 - lib/rggen/core_components/verilog_utility/identifier.rb
-- lib/rggen/core_components/verilog_utility/interface_instantiation.rb
-- lib/rggen/core_components/verilog_utility/interface_port_declaration.rb
+- lib/rggen/core_components/verilog_utility/interface_instance.rb
+- lib/rggen/core_components/verilog_utility/interface_port.rb
 - lib/rggen/core_components/verilog_utility/local_scope.rb
 - lib/rggen/core_components/verilog_utility/module_definition.rb
 - lib/rggen/core_components/verilog_utility/package_definition.rb
 - lib/rggen/core_components/verilog_utility/source_file.rb
 - lib/rggen/core_components/verilog_utility/structure_definition.rb
 - lib/rggen/core_components/verilog_utility/subroutine_definition.rb
+- lib/rggen/core_components/verilog_utility/variable.rb
 - lib/rggen/core_extensions/array.rb
 - lib/rggen/core_extensions/facets.rb
 - lib/rggen/core_extensions/forwardable.rb
@@ -304,7 +303,6 @@ files:
 - rtl/rggen_host_if_apb.sv
 - rtl/rggen_host_if_axi4lite.sv
 - rtl/rggen_indirect_register.sv
-- rtl/rggen_irq_controller.sv
 - rtl/rggen_register_base.sv
 - rtl/rggen_register_if.sv
 - rtl/rggen_rtl_pkg.sv

data/lib/rggen/builtins/register_block/irq_controller.erb

@@ -1,9 +0,0 @@
-rggen_irq_controller #(
-  .TOTAL_INTERRUPTS (<%= total_interrupts %>)
-) u_irq_controller (
-  .clk    (<%= register_block.clock %>),
-  .rst_n  (<%= register_block.reset %>),
-  .i_ier  (<%= ier %>),
-  .i_isr  (<%= isr %>),
-  .o_irq  (<%= irq %>)
-);

data/lib/rggen/builtins/register_block/irq_controller.rb

@@ -1,43 +0,0 @@
-simple_item :register_block, :irq_controller do
-  rtl do
-    available? { register_block.source.bit_fields.any?(&:irq?) }
-
-    build do
-      output :register_block, :irq, width: 1               , name: 'o_irq'
-      logic  :register_block, :ier, width: total_interrupts
-      logic  :register_block, :isr, width: total_interrupts
-    end
-
-    generate_code :register_block do |code|
-      code << assign_ier << nl
-      code << assign_isr << nl
-      code << process_template
-    end
-
-    def assign_ier
-      assign(ier, concat(ier_fields.map(&:value)))
-    end
-
-    def assign_isr
-      assign(isr, concat(isr_fields.map(&:value)))
-    end
-
-    def isr_fields
-      @isr_fields ||= register_block.bit_fields.select(&:irq?)
-    end
-
-    def ier_fields
-      @ier_fields ||= isr_fields.each_with_object([]) do |isr_field, fields|
-        fields << find_ier_field(isr_field.reference)
-      end
-    end
-
-    def find_ier_field(reference)
-      register_block.bit_fields.find_by(name: reference.name)
-    end
-
-    def total_interrupts
-      @total_interrupts ||= isr_fields.sum(0, &:width)
-    end
-  end
-end

data/lib/rggen/builtins/register_block/rtl_top.erb

@@ -1,7 +0,0 @@
-`define rggen_connect_bit_field_if(RIF, FIF, MSB, LSB) \
-  assign  FIF.read_access         = RIF.read_access; \
-  assign  FIF.write_access        = RIF.write_access; \
-  assign  FIF.write_data          = RIF.write_data[MSB:LSB]; \
-  assign  FIF.write_mask          = RIF.write_mask[MSB:LSB]; \
-  assign  RIF.value[MSB:LSB]      = FIF.value; \
-  assign  RIF.read_data[MSB:LSB]  = FIF.read_data;

data/lib/rggen/core_components/verilog_utility/declaration.rb

@@ -1,76 +0,0 @@
-module RgGen
-  module VerilogUtility
-    class Declaration
-      def initialize(declation_type, attributes)
-        @declation_type = declation_type
-        @attributes     = attributes
-      end
-
-      def to_s
-        code_snippets.join(' ')
-      end
-
-      private
-
-      def code_snippets
-        [
-          random_or_direction_or_parameter_type,
-          data_type,
-          width,
-          identifier,
-          default_value_assignment
-        ].select(&:itself)
-      end
-
-      def random_or_direction_or_parameter_type
-        {
-          variable:  @attributes[:random] && :rand,
-          port:      @attributes[:direction],
-          parameter: @attributes[:parameter_type]
-        }[@declation_type]
-      end
-
-      def data_type
-        @attributes[:data_type]
-      end
-
-      def width
-        return unless vector?
-        return "[#{@attributes[:width]}-1:0]" unless numerical_width?
-        "[#{(@attributes[:width] || 1) - 1}:0]"
-      end
-
-      def identifier
-        "#{@attributes[:name]}#{dimensions}"
-      end
-
-      def dimensions
-        return unless @attributes[:dimensions]
-        @attributes[:dimensions].map { |dimension| "[#{dimension}]" }.join
-      end
-
-      def default_value_assignment
-        return unless @attributes[:default]
-        "= #{@attributes[:default]}"
-      end
-
-      def parameter?
-        @declation_type == :parameter
-      end
-
-      def vector?
-        return true  if @attributes[:vector]
-        return false unless @attributes[:width]
-        return true  unless numerical_width?
-        return true  if parameter?
-        @attributes[:width] > 1
-      end
-
-      def numerical_width?
-        return true unless @attributes[:width]
-        return true if Integer === @attributes[:width]
-        false
-      end
-    end
-  end
-end

data/rtl/rggen_irq_controller.sv

@@ -1,21 +0,0 @@
-module rggen_irq_controller #(
-  parameter TOTAL_INTERRUPTS  = 1
-)(
-  input                           clk,
-  input                           rst_n,
-  input   [TOTAL_INTERRUPTS-1:0]  i_ier,
-  input   [TOTAL_INTERRUPTS-1:0]  i_isr,
-  output                          o_irq
-);
-  logic irq;
-
-  assign  o_irq = irq;
-  always_ff @(posedge clk or negedge rst_n) begin
-    if (!rst_n) begin
-      irq <= 1'b0;
-    end
-    else begin
-      irq <= |(i_ier & i_isr);
-    end
-  end
-endmodule