rggen 0.7.2 → 0.8.0

data/lib/rggen/core_components/verilog_utility/local_scope.rb

@@ -9,7 +9,6 @@ module RgGen
       end
 
       def to_code
-        bodies.unshift(signal_declarations) if signals?
         code_block do |c|
           header_code(c)
           body_code(c)
@@ -25,6 +24,13 @@ module RgGen
         loops? && generate_for_header(code)
       end
 
+      def body_code_blocks
+        blocks = []
+        signals? && (blocks << signal_declarations)
+        blocks.concat(super)
+        blocks
+      end
+
       def footer_code(code)
         loops? && generate_for_footer(code)
         code << :end
@@ -61,9 +67,7 @@ module RgGen
 
       def signal_declarations
         lambda do |code|
-          signals.each do |signal|
-            code << signal << semicolon << nl
-          end
+          signals.each { |signal| code << signal << semicolon << nl }
         end
       end
     end

data/lib/rggen/core_components/verilog_utility/module_definition.rb

@@ -5,9 +5,9 @@ module RgGen
       attr_setter :ports
       attr_setter :signals
 
-      def to_code
-        bodies.unshift(signal_declarations) if signals?
-        super
+      def include_file(file)
+        @include_files ||= []
+        @include_files << "`include #{file.to_s.quote}"
       end
 
       private
@@ -15,12 +15,20 @@ module RgGen
       def header_code
         code_block do |code|
           code << :module << space << @name << space
-          parameter_declarations(code)
+          parameters? && parameter_declarations(code)
           port_declarations(code)
           code << semicolon
         end
       end
 
+      def body_code_blocks
+        blocks = []
+        @include_files && (blocks << include_files_code)
+        signals? && (blocks << signal_declarations)
+        blocks.concat(super)
+        blocks
+      end
+
       def footer_code
         :endmodule
       end
@@ -38,7 +46,6 @@ module RgGen
       end
 
       def parameter_declarations(code)
-        return unless parameters?
         wrap(code, '#(', ')') do
           declarations(@parameters, code)
         end
@@ -46,15 +53,19 @@ module RgGen
 
       def port_declarations(code)
         wrap(code, '(', ')') do
-          declarations(@ports, code) if ports?
+          ports? && declarations(@ports, code)
+        end
+      end
+
+      def include_files_code
+        lambda do |code|
+          @include_files.each { |file| code << file << nl }
         end
       end
 
       def signal_declarations
         lambda do |code|
-          signals.each do |signal|
-            code << signal << semicolon << nl
-          end
+          signals.each { |signal| code << signal << semicolon << nl }
         end
       end
 

data/lib/rggen/core_components/verilog_utility/package_definition.rb

@@ -14,17 +14,13 @@ module RgGen
       end
 
       def import_package(name, items = nil)
-        import_packages << ImportedPackage.new(name, items)
+        @import_packages ||= []
+        @import_packages << ImportedPackage.new(name, items)
       end
 
       def include_file(name)
-        include_files << "`include #{name.to_s.quote}"
-      end
-
-      def to_code
-        bodies.unshift(include_fiels_code ) unless @include_files.nil?
-        bodies.unshift(import_packges_code) unless @import_packages.nil?
-        super
+        @include_files ||= []
+        @include_files << "`include #{name.to_s.quote}"
       end
 
       private
@@ -33,31 +29,27 @@ module RgGen
         "package #{@name};"
       end
 
-      def footer_code
-        :endpackage
-      end
-
-      def import_packages
-        @import_packages ||= []
+      def body_code_blocks
+        blocks = []
+        @import_packages && (blocks << import_packges_code)
+        @include_files && (blocks << include_files_code)
+        blocks.concat(super)
+        blocks
       end
 
-      def include_files
-        @include_files ||= []
+      def footer_code
+        :endpackage
       end
 
       def import_packges_code
         lambda do |code|
-          import_packages.each do |package|
-            code << package << nl
-          end
+          @import_packages.each { |package| code << package << nl }
         end
       end
 
-      def include_fiels_code
+      def include_files_code
         lambda do |code|
-          include_files.each do |file|
-            code << file << nl
-          end
+          @include_files.each { |file| code << file << nl }
         end
       end
     end

data/lib/rggen/core_components/verilog_utility/structure_definition.rb

@@ -9,7 +9,8 @@ module RgGen
       end
 
       def body(&block)
-        bodies << block if block_given?
+        @bodies ||= []
+        @bodies << block if block_given?
       end
 
       def to_code
@@ -22,16 +23,16 @@ module RgGen
 
       private
 
-      def bodies
-        @bodies ||= []
-      end
-
       def body_code(code)
-        bodies.each do |body|
+        body_code_blocks.each do |body|
           generate_body_code(code, body)
         end
       end
 
+      def body_code_blocks
+        @bodies || []
+      end
+
       def generate_body_code(code, body)
         indent(code, 2) do
           if body.arity.zero?

data/lib/rggen/core_components/verilog_utility/variable.rb

@@ -0,0 +1,115 @@
+module RgGen
+  module VerilogUtility
+    class Variable
+      def initialize(variable_type, attributes)
+        @variable_type  = variable_type
+        @attributes     = attributes
+      end
+
+      def to_s
+        code_snippets.join(' ')
+      end
+
+      def identifier
+        name          = @attributes[:name]
+        width         = @attributes[:width] || 1
+        dimensions    = @attributes[:dimensions]
+        array_fomrat  = @attributes[:array_format] || :unpacked
+        Identifier.new(name, width, dimensions, array_fomrat)
+      end
+
+      private
+
+      def code_snippets
+        [
+          rand_keyword,
+          port_direction,
+          parameter_keyword,
+          data_type,
+          width,
+          variable_identifier,
+          default_value_assignment
+        ].select(&:itself)
+      end
+
+      def rand_keyword
+        @variable_type == :variable && @attributes[:random] && :rand
+      end
+
+      def port_direction
+        @variable_type == :port && @attributes[:direction]
+      end
+
+      def parameter_keyword
+        @variable_type == :parameter && @attributes[:parameter_type]
+      end
+
+      def data_type
+        @attributes[:data_type]
+      end
+
+      def width
+        vector? || return
+        msb =
+          if numerical_width?
+            vectored_array_size * (@attributes[:width] || 1) - 1
+          elsif vectored_array?
+            "#{vectored_array_size}*#{@attributes[:width]}-1"
+          else
+            "#{@attributes[:width]}-1"
+          end
+        "[#{msb}:0]"
+      end
+
+      def vectored_array_size
+        vectored_array? || (return 1)
+        @attributes[:dimensions].inject(&:*)
+      end
+
+      def variable_identifier
+        "#{@attributes[:name]}#{dimensions}"
+      end
+
+      def dimensions
+        unpacked_array? || return
+        @attributes[:dimensions].map { |dimension| "[#{dimension}]" }.join
+      end
+
+      def default_value_assignment
+        @attributes[:default] || return
+        "= #{@attributes[:default]}"
+      end
+
+      def parameter?
+        @variable_type == :parameter
+      end
+
+      def vector?
+        @attributes[:vector] && (return true)
+        vectored_array? && (return true)
+        @attributes[:width] || (return false)
+        numerical_width? || (return true)
+        parameter? && (return true)
+        @attributes[:width] > 1
+      end
+
+      def numerical_width?
+        @attributes[:width] || (return true)
+        @attributes[:width].is_a?(Integer) && (return true)
+        false
+      end
+
+      def unpacked_array?
+        @attributes[:dimensions] || (return false)
+        @attributes[:array_format] == :vectored && (return false)
+        true
+      end
+
+      def vectored_array?
+        @attributes[:dimensions] || (return false)
+        @attributes[:array_format] == :vectored && (return true)
+        false
+      end
+    end
+  end
+end

data/lib/rggen/version.rb

@@ -1,6 +1,6 @@
 module RgGen
   MAJOR   = 0
-  MINOR   = 7
-  TEENY   = 2
+  MINOR   = 8
+  TEENY   = 0
   VERSION = "#{MAJOR}.#{MINOR}.#{TEENY}".freeze
 end

data/rtl/compile.f

@@ -3,7 +3,6 @@ ${RGGEN_HOME}/rtl/rggen_bus_if.sv
 ${RGGEN_HOME}/rtl/rggen_register_if.sv
 ${RGGEN_HOME}/rtl/rggen_bit_field_if.sv
 ${RGGEN_HOME}/rtl/rggen_bus_splitter.sv
-${RGGEN_HOME}/rtl/rggen_irq_controller.sv
 ${RGGEN_HOME}/rtl/rggen_address_decoder.sv
 ${RGGEN_HOME}/rtl/rggen_register_base.sv
 ${RGGEN_HOME}/rtl/rggen_default_register.sv
@@ -13,9 +12,7 @@ ${RGGEN_HOME}/rtl/rggen_bit_field_ro.sv
 ${RGGEN_HOME}/rtl/rggen_bit_field_rw.sv
 ${RGGEN_HOME}/rtl/rggen_bit_field_rwl_rwe.sv
 ${RGGEN_HOME}/rtl/rggen_bit_field_w01s_w01c.sv
-
 ${RGGEN_HOME}/rtl/rggen_apb_if.sv
 ${RGGEN_HOME}/rtl/rggen_host_if_apb.sv
-
 ${RGGEN_HOME}/rtl/rggen_axi4lite_if.sv
 ${RGGEN_HOME}/rtl/rggen_host_if_axi4lite.sv

data/rtl/rggen_address_decoder.sv

@@ -4,8 +4,8 @@ module rggen_address_decoder #(
   parameter bit [ADDRESS_WIDTH-1:0] END_ADDRESS   = '0,
   parameter int                     DATA_WIDTH    = 32
 )(
-  input   [ADDRESS_WIDTH-1:0] i_address,
-  output                      o_match
+  input   logic [ADDRESS_WIDTH-1:0] i_address,
+  output  logic                     o_match
 );
   localparam  int                         LSB       = $clog2(DATA_WIDTH / 8);
   localparam  bit [ADDRESS_WIDTH-LSB-1:0] SADDRESS  = STAET_ADDRESS[ADDRESS_WIDTH-1:LSB];

data/rtl/rggen_bus_splitter.sv

@@ -2,8 +2,8 @@ module rggen_bus_splitter #(
   parameter int DATA_WIDTH      = 32,
   parameter int TOTAL_REGISTERS = 1
 )(
-  input                     clk,
-  input                     rst_n,
+  input logic               clk,
+  input logic               rst_n,
   rggen_bus_if.slave        bus_if,
   rggen_register_if.master  register_if[TOTAL_REGISTERS]
 );

data/rtl/rggen_external_register.sv

@@ -4,8 +4,8 @@ module rggen_external_register #(
   parameter bit [ADDRESS_WIDTH-1:0] END_ADDRESS   = '0,
   parameter int                     DATA_WIDTH    = 32
 )(
-  input                     clk,
-  input                     rst_n,
+  input logic               clk,
+  input logic               rst_n,
   rggen_register_if.slave   register_if,
   rggen_bus_if.master       bus_if
 );

data/rtl/rggen_host_if_apb.sv

@@ -3,8 +3,8 @@ module rggen_host_if_apb #(
   parameter int DATA_WIDTH          = 32,
   parameter int TOTAL_REGISTERS     = 1
 )(
-  input                     clk,
-  input                     rst_n,
+  input logic               clk,
+  input logic               rst_n,
   rggen_apb_if.slave        apb_if,
   rggen_register_if.master  register_if[TOTAL_REGISTERS]
 );

data/rtl/rggen_indirect_register.sv

@@ -7,9 +7,9 @@ module rggen_indirect_register #(
   parameter int                     DATA_WIDTH    = 32,
   parameter bit [DATA_WIDTH-1:0]    VALID_BITS    = '0
 )(
-  rggen_register_if.slave   register_if,
-  rggen_bit_field_if.master bit_field_if,
-  input [INDEX_WIDTH-1:0]   i_index
+  rggen_register_if.slave       register_if,
+  rggen_bit_field_if.master     bit_field_if,
+  input logic [INDEX_WIDTH-1:0] i_index
 );
   logic index_match;
 

data/sample/sample.json

@@ -1,4 +1,6 @@
 {
   "address_width": 16,
-  "host_if"      : "apb"
+  "host_if": "apb",
+  "array_port_format": "unpacked",
+  "unfold_sv_interface_port": "no"
 }

data/sample/sample.yaml

@@ -1,2 +1,4 @@
 address_width: 16
 host_if: apb
+array_port_format: unpacked
+unfold_sv_interface_port: no

data/sample/sample_0.sv

@@ -1,38 +1,37 @@
 module sample_0 (
-  input clk,
-  input rst_n,
+  input logic clk,
+  input logic rst_n,
   rggen_apb_if.slave apb_if,
-  output o_irq,
-  output [15:0] o_bit_field_0_0,
-  output [15:0] o_bit_field_0_1,
-  output [31:0] o_bit_field_1_0,
-  input i_bit_field_2_0,
-  output o_bit_field_2_1,
-  input [31:0] i_bit_field_3_0,
-  input [15:0] i_bit_field_4_0[4],
-  output [15:0] o_bit_field_4_1[4],
-  input [15:0] i_bit_field_5_0[2][4],
-  output [15:0] o_bit_field_5_1[2][4],
-  input i_bit_field_6_0_set,
-  input i_bit_field_6_1_set,
-  output o_bit_field_7_0,
-  input i_bit_field_7_0_clear,
-  output o_bit_field_7_1,
-  input i_bit_field_7_1_clear,
-  output [15:0] o_bit_field_8_0,
-  output [15:0] o_bit_field_8_1,
+  output logic [15:0] o_bit_field_0_0,
+  output logic [15:0] o_bit_field_0_1,
+  output logic [31:0] o_bit_field_1_0,
+  input logic i_bit_field_2_0,
+  output logic o_bit_field_2_1,
+  input logic [31:0] i_bit_field_3_0,
+  input logic [15:0] i_bit_field_4_0[4],
+  output logic [15:0] o_bit_field_4_1[4],
+  input logic [15:0] i_bit_field_5_0[2][4],
+  output logic [15:0] o_bit_field_5_1[2][4],
+  input logic i_bit_field_6_0_set,
+  output logic o_bit_field_6_0,
+  input logic i_bit_field_6_1_set,
+  output logic o_bit_field_6_1,
+  output logic o_bit_field_7_0,
+  input logic i_bit_field_7_0_clear,
+  output logic o_bit_field_7_1,
+  input logic i_bit_field_7_1_clear,
+  output logic [15:0] o_bit_field_8_0,
+  output logic [15:0] o_bit_field_8_1,
   rggen_bus_if.master register_9_bus_if
 );
   rggen_register_if #(8, 32) register_if[20]();
-  logic [1:0] ier;
-  logic [1:0] isr;
   `define rggen_connect_bit_field_if(RIF, FIF, MSB, LSB) \
-    assign  FIF.read_access         = RIF.read_access; \
-    assign  FIF.write_access        = RIF.write_access; \
-    assign  FIF.write_data          = RIF.write_data[MSB:LSB]; \
-    assign  FIF.write_mask          = RIF.write_mask[MSB:LSB]; \
-    assign  RIF.value[MSB:LSB]      = FIF.value; \
-    assign  RIF.read_data[MSB:LSB]  = FIF.read_data;
+  assign  FIF.read_access         = RIF.read_access; \
+  assign  FIF.write_access        = RIF.write_access; \
+  assign  FIF.write_data          = RIF.write_data[MSB:LSB]; \
+  assign  FIF.write_mask          = RIF.write_mask[MSB:LSB]; \
+  assign  RIF.value[MSB:LSB]      = FIF.value; \
+  assign  RIF.read_data[MSB:LSB]  = FIF.read_data;
   rggen_host_if_apb #(
     .LOCAL_ADDRESS_WIDTH  (8),
     .DATA_WIDTH           (32),
@@ -43,17 +42,6 @@ module sample_0 (
     .apb_if       (apb_if),
     .register_if  (register_if)
   );
-  assign ier = {register_if[2].value[0], register_if[2].value[0]};
-  assign isr = {register_if[16].value[8], register_if[16].value[0]};
-  rggen_irq_controller #(
-    .TOTAL_INTERRUPTS (2)
-  ) u_irq_controller (
-    .clk    (clk),
-    .rst_n  (rst_n),
-    .i_ier  (ier),
-    .i_isr  (isr),
-    .o_irq  (o_irq)
-  );
   generate if (1) begin : g_register_0
     rggen_bit_field_if #(32) bit_field_if();
     rggen_default_register #(
@@ -289,7 +277,7 @@ module sample_0 (
         .rst_n          (rst_n),
         .i_set_or_clear (i_bit_field_6_0_set),
         .bit_field_if   (bit_field_sub_if),
-        .o_value        ()
+        .o_value        (o_bit_field_6_0)
       );
     end
     if (1) begin : g_bit_field_6_1
@@ -305,7 +293,7 @@ module sample_0 (
         .rst_n          (rst_n),
         .i_set_or_clear (i_bit_field_6_1_set),
         .bit_field_if   (bit_field_sub_if),
-        .o_value        ()
+        .o_value        (o_bit_field_6_1)
       );
     end
   end endgenerate