rggen 0.7.2 → 0.8.0

data/lib/rggen/builtins/register_block/rtl_top.rb

@@ -6,9 +6,9 @@ define_simple_item :register_block, :rtl_top do
 
     def source_file_body
       module_definition register_block.name do |m|
-        m.parameters register_block.parameter_declarations(:register_block)
-        m.ports      register_block.port_declarations(:register_block)
-        m.signals    register_block.signal_declarations(:register_block)
+        m.parameters   register_block.parameter_declarations(:register_block)
+        m.ports        register_block.port_declarations(:register_block)
+        m.signals      register_block.signal_declarations(:register_block)
         m.body { |code| module_body(code) }
       end
     end
@@ -17,12 +17,22 @@ define_simple_item :register_block, :rtl_top do
       register_block.generate_code(:register_block, :top_down, code)
     end
 
-    generate_pre_code :register_block do
-      process_template
+    generate_pre_code :register_block do |code|
+      [
+        '`define rggen_connect_bit_field_if(RIF, FIF, MSB, LSB) \\',
+        'assign  FIF.read_access         = RIF.read_access; \\',
+        'assign  FIF.write_access        = RIF.write_access; \\',
+        'assign  FIF.write_data          = RIF.write_data[MSB:LSB]; \\',
+        'assign  FIF.write_mask          = RIF.write_mask[MSB:LSB]; \\',
+        'assign  RIF.value[MSB:LSB]      = FIF.value; \\',
+        'assign  RIF.read_data[MSB:LSB]  = FIF.read_data;'
+      ].each do |line|
+        code  << line << nl
+      end
     end
 
-    generate_post_code :register_block do
-      :'`undef rggen_connect_bit_field_if'
+    generate_post_code :register_block do |code|
+      code  << :'`undef rggen_connect_bit_field_if' << nl
     end
   end
 end

data/lib/rggen/core_components.rb

@@ -6,15 +6,15 @@ require_relative 'core_components/code_utility/source_file'
 require_relative 'core_components/code_utility'
 
 require_relative 'core_components/verilog_utility/identifier'
-require_relative 'core_components/verilog_utility/declaration'
+require_relative 'core_components/verilog_utility/variable'
 require_relative 'core_components/verilog_utility/structure_definition'
 require_relative 'core_components/verilog_utility/local_scope'
 require_relative 'core_components/verilog_utility/module_definition'
 require_relative 'core_components/verilog_utility/package_definition'
 require_relative 'core_components/verilog_utility/class_definition'
 require_relative 'core_components/verilog_utility/subroutine_definition'
-require_relative 'core_components/verilog_utility/interface_instantiation'
-require_relative 'core_components/verilog_utility/interface_port_declaration'
+require_relative 'core_components/verilog_utility/interface_instance'
+require_relative 'core_components/verilog_utility/interface_port'
 require_relative 'core_components/verilog_utility/source_file'
 require_relative 'core_components/verilog_utility'
 

data/lib/rggen/core_components/ral/item.rb

@@ -15,12 +15,12 @@ module RgGen
 
       class << self
         private
-
         def define_declaration_method(method_name)
           define_method(method_name) do |domain, handle_name, attributes = {}|
             attributes[:name] ||= handle_name
-            add_identifier(handle_name, attributes[:name])
-            add_declaration(method_name, domain, attributes)
+            declaration = create_declaration(method_name, attributes)
+            add_declaration(method_name, domain, declaration)
+            add_identifier(handle_name, declaration.identifier)
           end
         end
       end
@@ -29,29 +29,30 @@ module RgGen
       define_declaration_method :parameter
 
       def variable_declarations(domain = nil)
-        return @variable_declarations if domain.nil?
+        domain || (return @variable_declarations)
         @variable_declarations[domain]
       end
 
       def parameter_declarations(domain = nil)
-        return @parameter_declarations if domain.nil?
+        domain || (return @parameter_declarations)
         @parameter_declarations[domain]
       end
 
       private
 
-      def add_identifier(handle_name, name)
-        create_identifier(name).tap do |i|
-          instance_variable_set(handle_name.variablize, i)
-          attr_singleton_reader(handle_name)
-          identifiers << handle_name
-        end
+      def create_declaration(type, attributes)
+        __send__("#{type}_declaration", attributes)
       end
 
-      def add_declaration(type, domain, attributes)
-        instance_variable_get("@#{type}_declarations").tap do |list|
-          list[domain] << __send__("#{type}_declaration", attributes)
-        end
+      def add_identifier(handle_name, identifier)
+        instance_variable_set(handle_name.variablize, identifier)
+        attr_singleton_reader(handle_name)
+        identifiers << handle_name
+      end
+
+      def add_declaration(type, domain, declaration)
+        list  = instance_variable_get("@#{type}_declarations")
+        list[domain]  << declaration
       end
     end
   end

data/lib/rggen/core_components/rtl/component.rb

@@ -19,10 +19,6 @@ module RgGen
       def parameter_declarations(domain)
         [*@items, *@children].flat_map { |o| o.parameter_declarations(domain) }
       end
-
-      def localparam_declarations(domain)
-        [*@items, *@children].flat_map { |o| o.localparam_declarations(domain) }
-      end
     end
   end
 end

data/lib/rggen/core_components/rtl/item.rb

@@ -10,15 +10,13 @@ module RgGen
         @signal_declarations      = Hash.new { |h, d| h[d]  = [] }
         @port_declarations        = Hash.new { |h, d| h[d]  = [] }
         @parameter_declarations   = Hash.new { |h, d| h[d]  = [] }
-        @localparam_declarations  = Hash.new { |h, d| h[d]  = [] }
       end
 
       attr_reader :identifiers
 
-      def_delegator :@signal_declarations    , :[], :signal_declarations
-      def_delegator :@port_declarations      , :[], :port_declarations
-      def_delegator :@parameter_declarations , :[], :parameter_declarations
-      def_delegator :@localparam_declarations, :[], :localparam_declarations
+      def_delegator :@signal_declarations   , :[], :signal_declarations
+      def_delegator :@port_declarations     , :[], :port_declarations
+      def_delegator :@parameter_declarations, :[], :parameter_declarations
 
       class << self
         private
@@ -26,8 +24,9 @@ module RgGen
         def define_declaration_method(method_name)
           define_method(method_name) do |domain, handle_name, attributes = {}|
             attributes[:name] ||= handle_name
-            add_identifier(handle_name, attributes[:name])
-            add_declaration(method_name, domain, attributes)
+            declaration = create_declaration(method_name, attributes)
+            add_declaration(method_name, domain, declaration)
+            add_identifier(handle_name, declaration.identifier)
           end
           private method_name
         end
@@ -45,41 +44,37 @@ module RgGen
 
       private
 
-      def add_declaration(type, domain, attributes)
+      def create_declaration(type, attributes)
         case type
         when :wire, :reg, :logic
-          @signal_declarations[domain] << variable_declaration(type, attributes)
+          variable_declaration(attributes.merge(data_type: type))
         when :interface
-          @signal_declarations[domain] << interface_instantiation(attributes)
+          interface_instance(attributes)
         when :input, :output
-          @port_declarations[domain] << port_declaration(type, attributes)
+          port_declaration(attributes.merge(direction: type))
         when :interface_port
-          @port_declarations[domain] << interface_port_declaration(attributes)
-        when :parameter
-          @parameter_declarations[domain] << parameter_declaration(type, attributes)
-        when :localparam
-          @localparam_declarations[domain] << parameter_declaration(type, attributes)
+          interface_port_declaration(attributes)
+        when :parameter, :localparam
+          parameter_declaration(attributes.merge(parameter_type: type))
         end
       end
 
-      def variable_declaration(data_type, attributes)
-        super(attributes.merge(data_type: data_type))
-      end
-
-      def port_declaration(direction, attributes)
-        super(attributes.merge(direction: direction))
-      end
-
-      def parameter_declaration(parameter_type, attributes)
-        super(attributes.merge(parameter_type: parameter_type))
+      def add_declaration(type, domain, declaration)
+        declarations  =
+          case type
+          when :wire, :reg, :logic, :interface
+            @signal_declarations[domain]
+          when :input, :output, :interface_port
+            @port_declarations[domain]
+          when :parameter, :localparam
+            @parameter_declarations[domain]
+          end
+        declarations  << declaration
       end
 
-      def add_identifier(handle_name, name)
-        identifier  = create_identifier(name)
-        instance_exec do
-          instance_variable_set(handle_name.variablize, identifier)
-          attr_singleton_reader(handle_name)
-        end
+      def add_identifier(handle_name, identifier)
+        instance_variable_set(handle_name.variablize, identifier)
+        attr_singleton_reader(handle_name)
         identifiers << handle_name
       end
     end

data/lib/rggen/core_components/verilog_utility.rb

@@ -13,23 +13,23 @@ module RgGen
     end
 
     def variable_declaration(attributes)
-      Declaration.new(:variable, attributes)
+      Variable.new(:variable, attributes)
     end
 
-    def interface_instantiation(attributes)
-      InterfaceInstantiation.new(attributes)
+    def interface_instance(attributes)
+      InterfaceInstance.new(attributes)
     end
 
     def port_declaration(attributes)
-      Declaration.new(:port, attributes)
+      Variable.new(:port, attributes)
     end
 
     def interface_port_declaration(attributes)
-      InterfacePortDeclaration.new(attributes)
+      InterfacePort.new(attributes)
     end
 
     def parameter_declaration(attributes)
-      Declaration.new(:parameter, attributes)
+      Variable.new(:parameter, attributes)
     end
 
     def module_definition(name, &body)

data/lib/rggen/core_components/verilog_utility/class_definition.rb

@@ -5,22 +5,24 @@ module RgGen
       attr_setter :parameters
       attr_setter :variables
 
-      def to_code
-        bodies.unshift(variables_declarations) if variables?
-        super
-      end
-
       private
 
       def header_code
         code_block do |code|
-          code << :class << space   << @name
-          paraemter_declarations(code) if parameters?
-          code << space  <<:extends << space << @base unless @base.nil?
+          code << :class << space << @name
+          parameters? && paraemter_declarations(code)
+          @base && (code << space <<:extends << space << @base)
           code << semicolon
         end
       end
 
+      def body_code_blocks
+        blocks = []
+        variables? && (blocks << variables_declarations)
+        blocks.concat(super)
+        blocks
+      end
+
       def footer_code
         :endclass
       end
@@ -46,9 +48,7 @@ module RgGen
 
       def variables_declarations
         lambda do |code|
-          variables.each do |variable|
-            code << variable << semicolon << nl
-          end
+          variables.each { |variable| code << variable << semicolon << nl }
         end
       end
     end

data/lib/rggen/core_components/verilog_utility/identifier.rb

@@ -3,25 +3,30 @@ module RgGen
     class Identifier
       include InputBase::RegxpPatterns
 
-      def initialize(name)
-        @name = name
+      def initialize(name, width = nil, array_dimensions = nil, array_format = nil)
+        @name             = name
+        @width            = width
+        @array_dimensions = array_dimensions
+        @array_format     = array_format || :unpacked
       end
 
       def to_s
         @name.to_s
       end
 
-      def [](indexes_or_msb, lsb = indexes_or_msb)
-        if indexes_or_msb.nil?
+      def [](array_index_or_msb, lsb = array_index_or_msb)
+        if array_index_or_msb.nil?
           self
-        elsif indexes_or_msb.is_a?(Array)
-          indexes_or_msb.inject(self) do |identifer, index|
-            identifer[index]
-          end
-        elsif indexes_or_msb == lsb
-          Identifier.new("#{@name}[#{indexes_or_msb}]")
         else
-          Identifier.new("#{@name}[#{indexes_or_msb}:#{lsb}]")
+          new_name  =
+            if array_index_or_msb.is_a?(Array)
+              "#{@name}#{array_selection(array_index_or_msb)}"
+            elsif array_index_or_msb == lsb
+              "#{@name}[#{array_index_or_msb}]"
+            else
+              "#{@name}[#{array_index_or_msb}:#{lsb}]"
+            end
+          Identifier.new(new_name, nil, nil, nil)
         end
       end
 
@@ -30,17 +35,44 @@ module RgGen
       ].freeze
 
       def method_missing(name, *args)
-        return super if args.size > 0
-        return super if TYPE_CONVERSIONS.include?(name)
-        return super unless name =~ variable_name
-        Identifier.new("#{@name}.#{name}")
+        args.size.zero? || (return super)
+        TYPE_CONVERSIONS.include?(name) && (return super)
+        (name =~ variable_name) || (return super)
+        Identifier.new("#{@name}.#{name}", nil, nil, nil)
       end
 
       def respond_to_missing?(symbol, include_private)
-        return super if TYPE_CONVERSIONS.include?(symbol)
-        return super unless symbol =~ variable_name
+        TYPE_CONVERSIONS.include?(symbol) && (return super)
+        symbol =~ variable_name || (return super)
         true
       end
+
+      private
+
+      def array_selection(array_index)
+        if @array_format == :unpacked
+          array_index.map { |i| "[#{i}]" }.join
+        else
+          "[#{@width}*(#{vector_index(array_index)})+:#{@width}]"
+        end
+      end
+
+      def vector_index(array_index)
+        index = []
+        array_index.zip(index_factors).reverse_each do |i, f|
+          index << ((index.size.zero? && i.to_s) || "#{f}*#{i}")
+        end
+        index.reverse.join('+')
+      end
+
+      def index_factors
+        factors = []
+        @array_dimensions.reverse.inject(1) do |elements, dimension|
+          factors.unshift(elements)
+          elements * dimension
+        end
+        factors
+      end
     end
   end
 end

data/lib/rggen/core_components/verilog_utility/{interface_instantiation.rb → interface_instance.rb}

@@ -1,12 +1,16 @@
 module RgGen
   module VerilogUtility
-    class InterfaceInstantiation
+    class InterfaceInstance
       def initialize(attributes)
         @attributes = attributes
       end
 
       def to_s
-        "#{interface_type} #{identifier}()"
+        "#{interface_type} #{instance_identifier}()"
+      end
+
+      def identifier
+        Identifier.new(@attributes[:name], nil, nil, nil)
       end
 
       private
@@ -20,7 +24,7 @@ module RgGen
         "#(#{@attributes[:parameters].join(', ')})"
       end
 
-      def identifier
+      def instance_identifier
         "#{@attributes[:name]}#{dimensions}"
       end
 

data/lib/rggen/core_components/verilog_utility/{interface_port_declaration.rb → interface_port.rb}

@@ -1,12 +1,16 @@
 module RgGen
   module VerilogUtility
-    class InterfacePortDeclaration
+    class InterfacePort
       def initialize(attributes)
         @attributes = attributes
       end
 
       def to_s
-        "#{interface_type} #{identifier}"
+        "#{interface_type} #{port_identifier}"
+      end
+
+      def identifier
+        Identifier.new(@attributes[:name], nil, nil, nil)
       end
 
       private
@@ -16,7 +20,7 @@ module RgGen
         "#{@attributes[:type]}.#{@attributes[:modport]}"
       end
 
-      def identifier
+      def port_identifier
         "#{@attributes[:name]}#{dimensions}"
       end