rggen 0.7.2 → 0.8.0

checksums.yaml

@@ -1,7 +1,7 @@
 ---
 SHA256:
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-  data.tar.gz: 722aa640d20ca719816965d83b16f5b67fafc26597c8f7b2083986e1ba24ee6e
+  metadata.gz: 1ae419a5f6e280921fc5527d3e697856fdda719cb7b381a59f34cbb23cb6bcab
+  data.tar.gz: ca6ea865dd6abef639b4f171bba9899132a56ddaa3eeacffa43d003ded1e801a
 SHA512:
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+  data.tar.gz: 99b98435e35e3c9b06ba268a623768ad70588dbecd16ccc9a6dd738933302cd72f36b57abbb89e547719ba3e875b0cd09c017d650bb95e38a31df0d639edb885

data/lib/rggen/builtins.rb

@@ -6,6 +6,8 @@ require_relative 'builtins/loaders/register_map/xlsx_ods_loader'
 
 require_relative 'builtins/global/address_width'
 require_relative 'builtins/global/data_width'
+require_relative 'builtins/global/array_port_format'
+require_relative 'builtins/global/unfold_sv_interface_port'
 
 require_relative 'builtins/bit_field/bit_assignment'
 require_relative 'builtins/bit_field/field_model'
@@ -47,7 +49,6 @@ require_relative 'builtins/register_block/default_map_creator'
 require_relative 'builtins/register_block/host_if'
 require_relative 'builtins/register_block/host_ifs/apb'
 require_relative 'builtins/register_block/host_ifs/axi4lite'
-require_relative 'builtins/register_block/irq_controller'
 require_relative 'builtins/register_block/name'
 require_relative 'builtins/register_block/ral_package'
 require_relative 'builtins/register_block/rtl_top'

data/lib/rggen/builtins/bit_field/type.rb

@@ -70,10 +70,6 @@ list_item :bit_field, :type do
         def same_width
           :same_width
         end
-
-        def irq?(&body)
-          define_method(:irq?, &body)
-        end
       end
 
       field :type
@@ -82,7 +78,6 @@ list_item :bit_field, :type do
       field :read_only? , forward_to_helper: true
       field :write_only?, forward_to_helper: true
       field :reserved?  , forward_to_helper: true
-      field :irq?       , default:           false
 
       class_delegator :full_width
       class_delegator :need_initial_value?
@@ -174,6 +169,9 @@ list_item :bit_field, :type do
       delegate [
         :dimensions, :index, :local_index, :loop_variables
       ] => :register
+      delegate [
+        :array_port_format
+      ] => :configuration
 
       available? { !bit_field.reserved? }
 

data/lib/rggen/builtins/bit_field/types/ro.rb

@@ -6,9 +6,11 @@ list_item :bit_field, :type, :ro do
   rtl do
     build do
       input :register_block, :value_in,
-            name:       "i_#{bit_field.name}",
-            width:      width,
-            dimensions: dimensions
+            name:         "i_#{bit_field.name}",
+            data_type:    :logic,
+            width:        width,
+            dimensions:   dimensions,
+            array_format: array_port_format
     end
 
     generate_code_from_template :bit_field

data/lib/rggen/builtins/bit_field/types/rw.rb

@@ -7,9 +7,11 @@ list_item :bit_field, :type, :rw do
   rtl do
     build do
       output :register_block, :value_out,
-             name: "o_#{bit_field.name}",
-             width: width,
-             dimensions: dimensions
+             name:          "o_#{bit_field.name}",
+             data_type:     :logic,
+             width:         width,
+             dimensions:    dimensions,
+             array_format:  array_port_format
     end
 
     generate_code_from_template :bit_field

data/lib/rggen/builtins/bit_field/types/rwl_rwe.rb

@@ -8,9 +8,11 @@ list_item :bit_field, :type, [:rwl, :rwe] do
   rtl do
     build do
       output :register_block, :value_out,
-             name:      "o_#{bit_field.name}",
-             width:      width,
-             dimensions: dimensions
+             name:          "o_#{bit_field.name}",
+             data_type:     :logic,
+             width:         width,
+             dimensions:    dimensions,
+             array_format:  array_port_format
     end
 
     generate_code_from_template :bit_field

data/lib/rggen/builtins/bit_field/types/w0c_w1c.erb

@@ -8,5 +8,5 @@ rggen_bit_field_w01s_w01c #(
   .rst_n          (<%= register_block.reset %>),
   .i_set_or_clear (<%= set[loop_variables] %>),
   .bit_field_if   (<%= bit_field_sub_if %>),
-  .o_value        ()
+  .o_value        (<%= value_out[loop_variables] %>)
 );

data/lib/rggen/builtins/bit_field/types/w0c_w1c.rb

@@ -2,16 +2,22 @@ list_item :bit_field, :type, [:w0c, :w1c] do
   register_map do
     read_write
     need_initial_value
-    use_reference width: same_width
-    irq? { bit_field.has_reference? }
   end
 
   rtl do
     build do
       input :register_block, :set,
-            name: "i_#{name}_set",
-            width: width,
-            dimensions: dimensions
+            name:         "i_#{name}_set",
+            data_type:    :logic,
+            width:        width,
+            dimensions:   dimensions,
+            array_format: array_port_format
+      output :register_block, :value_out,
+             name:          "o_#{name}",
+             data_type:     :logic,
+             width:         width,
+             dimensions:    dimensions,
+             array_format:  array_port_format
     end
 
     generate_code_from_template :bit_field

data/lib/rggen/builtins/bit_field/types/w0s_w1s.rb

@@ -7,13 +7,17 @@ list_item :bit_field, :type, [:w0s, :w1s] do
   rtl do
     build do
       output :register_block, :value_out,
-             name:      "o_#{name}",
-             width:      width,
-             dimensions: dimensions
+             name:          "o_#{name}",
+             data_type:     :logic,
+             width:         width,
+             dimensions:    dimensions,
+             array_format:  array_port_format
        input :register_block, :clear,
-             name:       "i_#{name}_clear",
-             width:      width,
-             dimensions: dimensions
+             name:          "i_#{name}_clear",
+             data_type:     :logic,
+             width:         width,
+             dimensions:    dimensions,
+             array_format:  array_port_format
     end
 
     generate_code_from_template :bit_field

data/lib/rggen/builtins/global/array_port_format.rb

@@ -0,0 +1,15 @@
+simple_item :global, :array_port_format do
+  configuration do
+    field :array_port_format, default: :unpacked
+
+    input_pattern /(unpacked|vectored)/i
+
+    build do |value|
+      pattern_matched? || (
+        error 'invalid array port format; ' \
+              "should be 'unpacked' or 'vectored': #{value.inspect}"
+      )
+      @array_port_format  = captures.first.downcase.to_sym
+    end
+  end
+end

data/lib/rggen/builtins/global/unfold_sv_interface_port.rb

@@ -0,0 +1,22 @@
+simple_item :global, :unfold_sv_interface_port do
+  configuration do
+    field :unfold_sv_interface_port?, default: false
+
+    build do |value|
+      @unfold_sv_interface_port =
+        case value
+        when true, false
+          value
+        when /\Atrue|on|yes\z/i
+          true
+        when /\Afalse|nil|off|no\z/i
+          false
+        else
+          message =
+            'non boolean value; should be true/false/nil/on/off/yes/no: ' \
+            "#{value.inspect}"
+          error message
+        end
+    end
+  end
+end

data/lib/rggen/builtins/register/type.rb

@@ -202,15 +202,21 @@ list_item :register, :type do
         actual_bit_fields.size
       end
 
+      def address_range
+        @address_range ||=
+          if register.array?
+            register.start_address..(register.start_address + byte_width - 1)
+          else
+            register.start_address..register.end_address
+          end
+      end
+
       def start_address
         address_code(register.start_address)
       end
 
       def end_address
-        return address_code(register.end_address) unless register.array?
-        address_code(
-          register.start_address + byte_width - 1
-        )
+        address_code(address_range.last)
       end
 
       def address_code(address)

data/lib/rggen/builtins/register/types/external.rb

@@ -6,14 +6,65 @@ list_item :register, :type, :external do
   end
 
   rtl do
+    delegate [:unfold_sv_interface_port?] => :configuration
+    delegate [:name] => :register
+
     build do
-      interface_port :register_block, :bus_if,
-                     name:    "#{register.name}_bus_if",
-                     type:    :rggen_bus_if,
-                     modport: :master
+      if unfold_sv_interface_port?
+        output :register_block, :request,
+          name: "o_#{name}_request", data_type: :logic, width: 1
+        output :register_block, :address,
+          name: "o_#{name}_address", data_type: :logic, width: address_width
+        output :register_block, :direction,
+          name: "o_#{name}_direction", data_type: :logic, width: 1
+        output :register_block, :write_data,
+          name: "o_#{name}_write_data", data_type: :logic, width: data_width
+        output :register_block, :strobe,
+          name: "o_#{name}_strobe", data_type: :logic, width: data_width / 8
+        input :register_block, :done,
+          name: "i_#{name}_done", data_type: :logic, width: 1
+        input :register_block, :write_done,
+          name: "i_#{name}_write_done", data_type: :logic, width: 1
+        input :register_block, :read_done,
+          name: "i_#{name}_read_done", data_type: :logic, width: 1
+        input :register_block, :read_data,
+          name: "i_#{name}_read_data", data_type: :logic, width: data_width
+        input :register_block, :status,
+          name: "i_#{name}_status", data_type: :logic, width: 2
+        interface :register, :bus_if,
+          type: :rggen_bus_if, parameters: [address_width, data_width]
+
+      else
+          interface_port :register_block, :bus_if,
+            name: "#{name}_bus_if", type: :rggen_bus_if, modport: :master
+      end
     end
 
-    generate_code_from_template :register
+    def address_width
+      Math.clog2(address_range.end - address_range.begin + 1)
+    end
+
+    generate_code :register do |code|
+      unfold_sv_interface_port? && bus_if_assignment(code)
+      code << process_template
+    end
+
+    def bus_if_assignment(code)
+      code << assign(request   , "#{bus_if}.request"     ) << nl
+      code << assign(address   , "#{bus_if}.address"     ) << nl
+      code << assign(direction , "#{bus_if}.direction"   ) << nl
+      code << assign(write_data, "#{bus_if}.write_data"  ) << nl
+      code << assign(strobe    , "#{bus_if}.write_strobe") << nl
+      code << assign("#{bus_if}.done"      , done         ) << nl
+      code << assign("#{bus_if}.write_done", write_done   ) << nl
+      code << assign("#{bus_if}.read_done" , read_done    ) << nl
+      code << assign("#{bus_if}.read_data" , read_data    ) << nl
+      code << assign("#{bus_if}.status"    , casted_status) << nl
+    end
+
+    def casted_status
+      "rggen_rtl_pkg::rggen_status'(#{status})"
+    end
   end
 
   c_header do

data/lib/rggen/builtins/register_block/clock_reset.rb

@@ -1,8 +1,8 @@
 simple_item :register_block, :clock_reset do
   rtl do
     build do
-      input :register_block, :clock, name: 'clk'  , width: 1
-      input :register_block, :reset, name: 'rst_n', width: 1
+      input :register_block, :clock, name: 'clk'  , data_type: :logic, width: 1
+      input :register_block, :reset, name: 'rst_n', data_type: :logic, width: 1
     end
   end
 end

data/lib/rggen/builtins/register_block/host_if.rb

@@ -41,7 +41,7 @@ list_item :register_block, :host_if do
 
     item_base do
       delegate [:local_address_width, :clock, :reset] => :register_block
-      delegate [:data_width] => :configuration
+      delegate [:data_width, :unfold_sv_interface_port?] => :configuration
 
       build do
         interface :register_block, :register_if,

data/lib/rggen/builtins/register_block/host_ifs/apb.rb

@@ -14,11 +14,51 @@ list_item :register_block, :host_if, :apb do
 
   rtl do
     build do
-      interface_port :register_block, :apb_if,
-                     type: :rggen_apb_if,
-                     modport: :slave
+      if unfold_sv_interface_port?
+        input :register_block, :psel,
+          name: 'i_psel', data_type: :logic, width: 1
+        input :register_block, :penable,
+          name: 'i_penable', data_type: :logic, width: 1
+        input :register_block, :paddr,
+          name: 'i_paddr', data_type: :logic, width: local_address_width
+        input :register_block, :pprot,
+          name: 'i_pprot', data_type: :logic, width: 3
+        input :register_block, :pwrite,
+          name: 'i_pwrite', data_type: :logic, width: 1
+        input :register_block, :pwdata,
+          name: 'i_pwdata', data_type: :logic, width: data_width
+        input :register_block, :pstrb,
+          name: 'i_pstrb', data_type: :logic, width: data_width / 8
+        output :register_block, :pready,
+          name: 'o_pready', data_type: :logic, width: 1
+        output :register_block, :prdata,
+          name: 'o_prdata', data_type: :logic, width: data_width
+        output :register_block, :pslverr,
+          name: 'o_pslverr', data_type: :logic, width: 1
+        interface :register_block, :apb_if,
+          type: :rggen_apb_if, parameters: [local_address_width, data_width]
+      else
+        interface_port :register_block, :apb_if,
+          type: :rggen_apb_if, modport:  :slave
+      end
+    end
+
+    generate_code :register_block do |code|
+      unfold_sv_interface_port? && apb_if_assignment(code)
+      code << process_template
     end
 
-    generate_code_from_template :register_block
+    def apb_if_assignment(code)
+      code << assign("#{apb_if}.psel"   , psel   ) << nl
+      code << assign("#{apb_if}.penable", penable) << nl
+      code << assign("#{apb_if}.paddr"  , paddr  ) << nl
+      code << assign("#{apb_if}.pprot"  , pprot  ) << nl
+      code << assign("#{apb_if}.pwrite" , pwrite ) << nl
+      code << assign("#{apb_if}.pwdata" , pwdata ) << nl
+      code << assign("#{apb_if}.pstrb"  , pstrb  ) << nl
+      code << assign(pready , "#{apb_if}.pready" ) << nl
+      code << assign(prdata , "#{apb_if}.prdata" ) << nl
+      code << assign(pslverr, "#{apb_if}.pslverr") << nl
+    end
   end
 end

data/lib/rggen/builtins/register_block/host_ifs/axi4lite.rb

@@ -11,14 +11,83 @@ list_item :register_block, :host_if, :axi4lite do
   rtl do
     build do
       parameter :register_block, :access_priority,
-                name:      'ACCESS_PRIORITY',
-                data_type: :'rggen_rtl_pkg::rggen_direction',
-                default:   :'rggen_rtl_pkg::RGGEN_WRITE'
-      interface_port :register_block, :axi4lite_if,
-                     type:    :rggen_axi4lite_if,
-                     modport: :slave
+        name:      'ACCESS_PRIORITY',
+        data_type: :'rggen_rtl_pkg::rggen_direction',
+        default:   :'rggen_rtl_pkg::RGGEN_WRITE'
+      if unfold_sv_interface_port?
+        input :register_block, :awvalid,
+          name: 'i_awvalid', data_type: :logic, width: 1
+        output :register_block, :awready,
+          name: 'o_awready', data_type: :logic, width: 1
+        input :register_block, :awaddr,
+          name: 'i_awaddr', data_type: :logic, width: local_address_width
+        input :register_block, :awprot,
+          name: 'i_awprot', data_type: :logic, width: 3
+        input :register_block, :wvalid,
+          name: 'i_wvalid', data_type: :logic, width: 1
+        output :register_block, :wready,
+          name: 'o_wready', data_type: :logic, width: 1
+        input :register_block, :wdata,
+          name: 'i_wdata', data_type: :logic, width: data_width
+        input :register_block, :wstrb,
+          name: 'i_wstrb', data_type: :logic, width: data_width / 8
+        output :register_block, :bvalid,
+          name: 'o_bvalid', data_type: :logic, width: 1
+        input :register_block, :bready,
+          name: 'i_bready', data_type: :logic, width: 1
+        output :register_block, :bresp,
+          name: 'o_bresp', data_type: :logic, width: 2
+        input :register_block, :arvalid,
+          name: 'i_arvalid', data_type: :logic, width: 1
+        output :register_block, :arready,
+          name: 'o_arready', data_type: :logic, width: 1
+        input :register_block, :araddr,
+          name: 'i_araddr', data_type: :logic, width: local_address_width
+        input :register_block, :arprot,
+          name: 'i_arprot', data_type: :logic, width: 3
+        output :register_block, :rvalid,
+          name: 'o_rvalid', data_type: :logic, width: 1
+        input :register_block, :rready,
+          name: 'i_rready', data_type: :logic, width: 1
+        output :register_block, :rdata,
+          name: 'o_rdata', data_type: :logic, width: data_width
+        output :register_block, :rresp,
+          name: 'o_rresp', data_type: :logic, width: 2
+        interface :register_block, :axi4lite_if,
+          type: :rggen_axi4lite_if,
+          parameters: [local_address_width, data_width]
+      else
+        interface_port :register_block, :axi4lite_if,
+          type:    :rggen_axi4lite_if,
+          modport: :slave
+      end
+    end
+
+    generate_code :register_block do |code|
+      unfold_sv_interface_port? && axi4lite_if_assignment(code)
+      code << process_template
     end
 
-    generate_code_from_template :register_block
+    def axi4lite_if_assignment(code)
+      code << assign("#{axi4lite_if}.awvalid", awvalid) << nl
+      code << assign(awready, "#{axi4lite_if}.awready") << nl
+      code << assign("#{axi4lite_if}.awaddr" , awaddr ) << nl
+      code << assign("#{axi4lite_if}.awprot" , awprot ) << nl
+      code << assign("#{axi4lite_if}.wvalid" , wvalid ) << nl
+      code << assign(wready , "#{axi4lite_if}.wready" ) << nl
+      code << assign("#{axi4lite_if}.wdata"  , wdata  ) << nl
+      code << assign("#{axi4lite_if}.wstrb"  , wstrb  ) << nl
+      code << assign(bvalid , "#{axi4lite_if}.bvalid" ) << nl
+      code << assign("#{axi4lite_if}.bready" , bready ) << nl
+      code << assign(bresp  , "#{axi4lite_if}.bresp"  ) << nl
+      code << assign("#{axi4lite_if}.arvalid", arvalid) << nl
+      code << assign(arready, "#{axi4lite_if}.arready") << nl
+      code << assign("#{axi4lite_if}.araddr" , araddr ) << nl
+      code << assign("#{axi4lite_if}.arprot" , arprot ) << nl
+      code << assign(rvalid , "#{axi4lite_if}.rvalid" ) << nl
+      code << assign("#{axi4lite_if}.rready" , rready ) << nl
+      code << assign(rdata  , "#{axi4lite_if}.rdata"  ) << nl
+      code << assign(rresp  , "#{axi4lite_if}.rresp"  ) << nl
+    end
   end
 end