rggen-systemverilog 0.24.0 → 0.26.0

data/lib/rggen/systemverilog/rtl/register_block/protocol/wishbone.rb

@@ -0,0 +1,26 @@
+# frozen_string_literal: true
+
+RgGen.define_list_item_feature(:register_block, :protocol, :wishbone) do
+  configuration do
+    verify(:component) do
+      error_condition { configuration.bus_width > 64 }
+      message do
+        'bus width over 64 bit is not supported: ' \
+        "#{configuration.bus_width}"
+      end
+    end
+  end
+
+  sv_rtl do
+    build do
+      parameter :use_stall, {
+        name: 'USE_STALL', data_type: :bit, default: 1
+      }
+      interface_port :wishbone_if, {
+        name: 'wishbone_if', interface_type: 'rggen_wishbone_if', modport: 'slave'
+      }
+    end
+
+    main_code :register_block, from_template: true
+  end
+end

data/lib/rggen/systemverilog/rtl/register_block/sv_rtl_top.rb

@@ -5,12 +5,8 @@ RgGen.define_simple_feature(:register_block, :sv_rtl_top) do
     export :total_registers
 
     build do
-      input :clock, {
-        name: 'i_clk', data_type: :logic, width: 1
-      }
-      input :reset, {
-        name: 'i_rst_n', data_type: :logic, width: 1
-      }
+      input :clock, { name: 'i_clk', width: 1 }
+      input :reset, { name: 'i_rst_n', width: 1 }
       interface :register_if, {
         name: 'register_if', interface_type: 'rggen_register_if',
         parameter_values: [address_width, bus_width, value_width],

data/lib/rggen/systemverilog/rtl/register_index.rb

@@ -50,13 +50,10 @@ module RgGen
         end
 
         def index(offset_or_offsets = nil)
-          operands = index_operands(offset_or_offsets)
-          partial_indices = partial_sums(operands)
-          if partial_indices.empty? || partial_indices.all?(&method(:integer?))
-            partial_indices.sum
-          else
-            partial_indices.join('+')
-          end
+          offset_or_offsets
+            .yield_self(&method(:index_operands))
+            .yield_self(&method(:partial_sums))
+            .yield_self(&method(:reduce_indices))
         end
 
         def inside_loop?
@@ -87,12 +84,17 @@ module RgGen
           ]
         end
 
+        def reduce_indices(indices)
+          if indices.empty? || indices.all?(&method(:integer?))
+            indices.sum
+          else
+            indices.join('+')
+          end
+        end
+
         def local_register_index(offset)
           (component.array? || nil) &&
-            begin
-              operands = [component.count(false), offset || local_index]
-              product(operands, true)
-            end
+            product([component.count(false), offset || local_index], true)
         end
 
         def product(operands, need_bracket)

data/lib/rggen/systemverilog/rtl/register_type.rb

@@ -25,9 +25,10 @@ module RgGen
         end
 
         def offset_address
-          offsets = [*register_files, register].flat_map(&method(:collect_offsets))
-          offsets = partial_sums(offsets)
-          format_offsets(offsets)
+          [*register_files, register]
+            .flat_map(&method(:collect_offsets))
+            .yield_self(&method(:partial_sums))
+            .yield_self(&method(:format_offsets))
         end
 
         def collect_offsets(component)

data/lib/rggen/systemverilog/rtl/setup.rb

@@ -3,11 +3,9 @@
 require 'rggen/systemverilog/rtl'
 
 RgGen.register_plugin RgGen::SystemVerilog::RTL do |builder|
-  builder.enable :global, [
-    :array_port_format, :fold_sv_interface_port
-  ]
+  builder.enable :global, [:array_port_format]
   builder.enable :register_block, [:sv_rtl_top, :protocol]
-  builder.enable :register_block, :protocol, [:apb, :axi4lite]
+  builder.enable :register_block, :protocol, [:apb, :axi4lite, :wishbone]
   builder.enable :register_file, [:sv_rtl_top]
   builder.enable :register, [:sv_rtl_top]
   builder.enable :bit_field, [:sv_rtl_top]

data/lib/rggen/systemverilog/rtl.rb

@@ -25,21 +25,20 @@ module RgGen
           'rtl/bit_field/sv_rtl_top',
           'rtl/bit_field/type',
           'rtl/bit_field/type/rc_w0c_w1c_wc_woc',
-          'rtl/bit_field/type/reserved',
-          'rtl/bit_field/type/ro',
+          'rtl/bit_field/type/ro_rotrg',
           'rtl/bit_field/type/rof',
+          'rtl/bit_field/type/rowo_rowotrg',
           'rtl/bit_field/type/rs_w0s_w1s_ws_wos',
-          'rtl/bit_field/type/rw_w1_wo_wo1',
+          'rtl/bit_field/type/rw_rwtrg_w1',
           'rtl/bit_field/type/rwc',
-          'rtl/bit_field/type/rwe',
-          'rtl/bit_field/type/rwl',
+          'rtl/bit_field/type/rwe_rwl',
           'rtl/bit_field/type/rws',
           'rtl/bit_field/type/w0crs_w0src_w1crs_w1src_wcrs_wsrc',
           'rtl/bit_field/type/w0t_w1t',
           'rtl/bit_field/type/w0trg_w1trg',
+          'rtl/bit_field/type/wo_wo1_wotrg',
           'rtl/bit_field/type/wrc_wrs',
           'rtl/global/array_port_format',
-          'rtl/global/fold_sv_interface_port',
           'rtl/register/sv_rtl_top',
           'rtl/register/type',
           'rtl/register/type/external',
@@ -47,6 +46,7 @@ module RgGen
           'rtl/register_block/protocol',
           'rtl/register_block/protocol/apb',
           'rtl/register_block/protocol/axi4lite',
+          'rtl/register_block/protocol/wishbone',
           'rtl/register_block/sv_rtl_top',
           'rtl/register_file/sv_rtl_top'
         ]

data/lib/rggen/systemverilog/version.rb

@@ -2,6 +2,6 @@
 
 module RgGen
   module SystemVerilog
-    VERSION = '0.24.0'
+    VERSION = '0.26.0'
   end
 end

metadata

@@ -1,29 +1,15 @@
 --- !ruby/object:Gem::Specification
 name: rggen-systemverilog
 version: !ruby/object:Gem::Version
-  version: 0.24.0
+  version: 0.26.0
 platform: ruby
 authors:
 - Taichi Ishitani
 autorequire: 
 bindir: bin
 cert_chain: []
-date: 2021-01-20 00:00:00.000000000 Z
+date: 2022-03-25 00:00:00.000000000 Z
 dependencies:
-- !ruby/object:Gem::Dependency
-  name: facets
-  requirement: !ruby/object:Gem::Requirement
-    requirements:
-    - - ">="
-      - !ruby/object:Gem::Version
-        version: '3.0'
-  type: :runtime
-  prerelease: false
-  version_requirements: !ruby/object:Gem::Requirement
-    requirements:
-    - - ">="
-      - !ruby/object:Gem::Version
-        version: '3.0'
 - !ruby/object:Gem::Dependency
   name: bundler
   requirement: !ruby/object:Gem::Requirement
@@ -69,7 +55,9 @@ files:
 - lib/rggen/systemverilog/common/utility/structure_definition.rb
 - lib/rggen/systemverilog/ral.rb
 - lib/rggen/systemverilog/ral/bit_field/type.rb
-- lib/rggen/systemverilog/ral/bit_field/type/reserved_rof.rb
+- lib/rggen/systemverilog/ral/bit_field/type/rof.rb
+- lib/rggen/systemverilog/ral/bit_field/type/rotrg_rwtrg_wotrg.rb
+- lib/rggen/systemverilog/ral/bit_field/type/rowo_rowotrg.rb
 - lib/rggen/systemverilog/ral/bit_field/type/rwc_rws.rb
 - lib/rggen/systemverilog/ral/bit_field/type/rwe_rwl.rb
 - lib/rggen/systemverilog/ral/bit_field/type/w0trg_w1trg.rb
@@ -91,22 +79,20 @@ files:
 - lib/rggen/systemverilog/rtl/bit_field/type.rb
 - lib/rggen/systemverilog/rtl/bit_field/type/rc_w0c_w1c_wc_woc.erb
 - lib/rggen/systemverilog/rtl/bit_field/type/rc_w0c_w1c_wc_woc.rb
-- lib/rggen/systemverilog/rtl/bit_field/type/reserved.erb
-- lib/rggen/systemverilog/rtl/bit_field/type/reserved.rb
-- lib/rggen/systemverilog/rtl/bit_field/type/ro.erb
-- lib/rggen/systemverilog/rtl/bit_field/type/ro.rb
+- lib/rggen/systemverilog/rtl/bit_field/type/ro_rotrg.erb
+- lib/rggen/systemverilog/rtl/bit_field/type/ro_rotrg.rb
 - lib/rggen/systemverilog/rtl/bit_field/type/rof.erb
 - lib/rggen/systemverilog/rtl/bit_field/type/rof.rb
+- lib/rggen/systemverilog/rtl/bit_field/type/rowo_rowotrg.erb
+- lib/rggen/systemverilog/rtl/bit_field/type/rowo_rowotrg.rb
 - lib/rggen/systemverilog/rtl/bit_field/type/rs_w0s_w1s_ws_wos.erb
 - lib/rggen/systemverilog/rtl/bit_field/type/rs_w0s_w1s_ws_wos.rb
-- lib/rggen/systemverilog/rtl/bit_field/type/rw_w1_wo_wo1.erb
-- lib/rggen/systemverilog/rtl/bit_field/type/rw_w1_wo_wo1.rb
+- lib/rggen/systemverilog/rtl/bit_field/type/rw_rwtrg_w1.erb
+- lib/rggen/systemverilog/rtl/bit_field/type/rw_rwtrg_w1.rb
 - lib/rggen/systemverilog/rtl/bit_field/type/rwc.erb
 - lib/rggen/systemverilog/rtl/bit_field/type/rwc.rb
-- lib/rggen/systemverilog/rtl/bit_field/type/rwe.erb
-- lib/rggen/systemverilog/rtl/bit_field/type/rwe.rb
-- lib/rggen/systemverilog/rtl/bit_field/type/rwl.erb
-- lib/rggen/systemverilog/rtl/bit_field/type/rwl.rb
+- lib/rggen/systemverilog/rtl/bit_field/type/rwe_rwl.erb
+- lib/rggen/systemverilog/rtl/bit_field/type/rwe_rwl.rb
 - lib/rggen/systemverilog/rtl/bit_field/type/rws.erb
 - lib/rggen/systemverilog/rtl/bit_field/type/rws.rb
 - lib/rggen/systemverilog/rtl/bit_field/type/w0crs_w0src_w1crs_w1src_wcrs_wsrc.erb
@@ -115,12 +101,13 @@ files:
 - lib/rggen/systemverilog/rtl/bit_field/type/w0t_w1t.rb
 - lib/rggen/systemverilog/rtl/bit_field/type/w0trg_w1trg.erb
 - lib/rggen/systemverilog/rtl/bit_field/type/w0trg_w1trg.rb
+- lib/rggen/systemverilog/rtl/bit_field/type/wo_wo1_wotrg.erb
+- lib/rggen/systemverilog/rtl/bit_field/type/wo_wo1_wotrg.rb
 - lib/rggen/systemverilog/rtl/bit_field/type/wrc_wrs.erb
 - lib/rggen/systemverilog/rtl/bit_field/type/wrc_wrs.rb
 - lib/rggen/systemverilog/rtl/bit_field_index.rb
 - lib/rggen/systemverilog/rtl/feature.rb
 - lib/rggen/systemverilog/rtl/global/array_port_format.rb
-- lib/rggen/systemverilog/rtl/global/fold_sv_interface_port.rb
 - lib/rggen/systemverilog/rtl/indirect_index.rb
 - lib/rggen/systemverilog/rtl/partial_sum.rb
 - lib/rggen/systemverilog/rtl/register/sv_rtl_top.rb
@@ -135,6 +122,8 @@ files:
 - lib/rggen/systemverilog/rtl/register_block/protocol/apb.rb
 - lib/rggen/systemverilog/rtl/register_block/protocol/axi4lite.erb
 - lib/rggen/systemverilog/rtl/register_block/protocol/axi4lite.rb
+- lib/rggen/systemverilog/rtl/register_block/protocol/wishbone.erb
+- lib/rggen/systemverilog/rtl/register_block/protocol/wishbone.rb
 - lib/rggen/systemverilog/rtl/register_block/sv_rtl_macros.erb
 - lib/rggen/systemverilog/rtl/register_block/sv_rtl_top.rb
 - lib/rggen/systemverilog/rtl/register_file/sv_rtl_top.rb
@@ -148,6 +137,7 @@ licenses:
 metadata:
   bug_tracker_uri: https://github.com/rggen/rggen-systemverilog/issues
   mailing_list_uri: https://groups.google.com/d/forum/rggen
+  rubygems_mfa_required: 'true'
   source_code_uri: https://github.com/rggen/rggen-systemverilog
   wiki_uri: https://github.com/rggen/rggen/wiki
 post_install_message: 
@@ -158,15 +148,15 @@ required_ruby_version: !ruby/object:Gem::Requirement
   requirements:
   - - ">="
     - !ruby/object:Gem::Version
-      version: '2.4'
+      version: '2.6'
 required_rubygems_version: !ruby/object:Gem::Requirement
   requirements:
   - - ">="
     - !ruby/object:Gem::Version
       version: '0'
 requirements: []
-rubygems_version: 3.2.3
+rubygems_version: 3.3.3
 signing_key: 
 specification_version: 4
-summary: rggen-systemverilog-0.24.0
+summary: rggen-systemverilog-0.26.0
 test_files: []

data/lib/rggen/systemverilog/ral/bit_field/type/reserved_rof.rb

@@ -1,5 +0,0 @@
-# frozen_string_literal: true
-
-RgGen.define_list_item_feature(:bit_field, :type, [:reserved, :rof]) do
-  sv_ral { access 'RO' }
-end

data/lib/rggen/systemverilog/rtl/bit_field/type/reserved.erb

@@ -1,18 +0,0 @@
-rggen_bit_field #(
-  .WIDTH          (<%= width %>),
-  .SW_READ_ACTION (RGGEN_READ_NONE),
-  .STORAGE        (0)
-) u_bit_field (
-  .i_clk              ('0),
-  .i_rst_n            ('0),
-  .bit_field_if       (<%= bit_field_if %>),
-  .i_sw_write_enable  ('0),
-  .i_hw_write_enable  ('0),
-  .i_hw_write_data    ('0),
-  .i_hw_set           ('0),
-  .i_hw_clear         ('0),
-  .i_value            ('0),
-  .i_mask             ('0),
-  .o_value            (),
-  .o_value_unmasked   ()
-);

data/lib/rggen/systemverilog/rtl/bit_field/type/reserved.rb

@@ -1,7 +0,0 @@
-# frozen_string_literal: true
-
-RgGen.define_list_item_feature(:bit_field, :type, :reserved) do
-  sv_rtl do
-    main_code :bit_field, from_template: true
-  end
-end

data/lib/rggen/systemverilog/rtl/bit_field/type/ro.rb

@@ -1,22 +0,0 @@
-# frozen_string_literal: true
-
-RgGen.define_list_item_feature(:bit_field, :type, :ro) do
-  sv_rtl do
-    build do
-      unless bit_field.reference?
-        input :value_in, {
-          name: "i_#{full_name}", data_type: :logic, width: width,
-          array_size: array_size, array_format: array_port_format
-        }
-      end
-    end
-
-    main_code :bit_field, from_template: true
-
-    private
-
-    def reference_or_value_in
-      bit_field.reference? && reference_bit_field || value_in[loop_variables]
-    end
-  end
-end

data/lib/rggen/systemverilog/rtl/bit_field/type/rw_w1_wo_wo1.rb

@@ -1,24 +0,0 @@
-# frozen_string_literal: true
-
-RgGen.define_list_item_feature(:bit_field, :type, [:rw, :w1, :wo, :wo1]) do
-  sv_rtl do
-    build do
-      output :value_out, {
-        name: "o_#{full_name}", data_type: :logic, width: width,
-        array_size: array_size, array_format: array_port_format
-      }
-    end
-
-    main_code :bit_field, from_template: true
-
-    private
-
-    def read_action
-      bit_field.readable? && 'RGGEN_READ_DEFAULT' || 'RGGEN_READ_NONE'
-    end
-
-    def write_once
-      [:w1, :wo1].include?(bit_field.type) && 1 || 0
-    end
-  end
-end

data/lib/rggen/systemverilog/rtl/bit_field/type/rwe.rb

@@ -1,26 +0,0 @@
-# frozen_string_literal: true
-
-RgGen.define_list_item_feature(:bit_field, :type, :rwe) do
-  sv_rtl do
-    build do
-      unless bit_field.reference?
-        input :enable, {
-          name: "i_#{full_name}_enable", data_type: :logic, width: 1,
-          array_size: array_size, array_format: array_port_format
-        }
-      end
-      output :value_out, {
-        name: "o_#{full_name}", data_type: :logic, width: width,
-        array_size: array_size, array_format: array_port_format
-      }
-    end
-
-    main_code :bit_field, from_template: true
-
-    private
-
-    def enable_signal
-      reference_bit_field || enable[loop_variables]
-    end
-  end
-end

data/lib/rggen/systemverilog/rtl/bit_field/type/rwl.rb

@@ -1,26 +0,0 @@
-# frozen_string_literal: true
-
-RgGen.define_list_item_feature(:bit_field, :type, :rwl) do
-  sv_rtl do
-    build do
-      unless bit_field.reference?
-        input :lock, {
-          name: "i_#{full_name}_lock", data_type: :logic, width: 1,
-          array_size: array_size, array_format: array_port_format
-        }
-      end
-      output :value_out, {
-        name: "o_#{full_name}", data_type: :logic, width: width,
-        array_size: array_size, array_format: array_port_format
-      }
-    end
-
-    main_code :bit_field, from_template: true
-
-    private
-
-    def lock_signal
-      reference_bit_field || lock[loop_variables]
-    end
-  end
-end

data/lib/rggen/systemverilog/rtl/global/fold_sv_interface_port.rb

@@ -1,28 +0,0 @@
-# frozen_string_literal: true
-
-RgGen.define_simple_feature(:global, :fold_sv_interface_port) do
-  configuration do
-    property :fold_sv_interface_port?, default: true
-
-    input_pattern [
-      /true|on|yes/i, /false|off|no/i
-    ], match_automatically: false
-
-    ignore_empty_value false
-
-    build do |value|
-      @fold_sv_interface_port =
-        if [true, false].include?(value)
-          value
-        elsif match_pattern(value)
-          [true, false][match_index]
-        else
-          error "cannot convert #{value.inspect} into boolean"
-        end
-    end
-
-    printable :fold_sv_interface_port do
-      fold_sv_interface_port?
-    end
-  end
-end