rggen-systemverilog 0.24.0 → 0.26.0

checksums.yaml

@@ -1,7 +1,7 @@
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+  data.tar.gz: 4ea6fb47189ec224f30701198d9a51de4ab68cbc2a601b048ad23b1edcda1308214218fd456550c2e8d085c3575ab2aeec7e58c43d6337dba81111c0e8f0b07f

data/LICENSE

@@ -1,6 +1,6 @@
 The MIT License (MIT)
 
-Copyright (c) 2019-2021 Taichi Ishitani
+Copyright (c) 2019-2022 Taichi Ishitani
 
 Permission is hereby granted, free of charge, to any person obtaining a copy
 of this software and associated documentation files (the "Software"), to deal

data/README.md

@@ -34,7 +34,7 @@ Feedbacks, bug reports, questions and etc. are wellcome! You can post them by us
 
 ## Copyright & License
 
-Copyright © 2019-2021 Taichi Ishitani. RgGen::SystemVerilog is licensed under the [MIT License](https://opensource.org/licenses/MIT), see [LICENSE](LICENSE) for futher details.
+Copyright © 2019-2022 Taichi Ishitani. RgGen::SystemVerilog is licensed under the [MIT License](https://opensource.org/licenses/MIT), see [LICENSE](LICENSE) for futher details.
 
 ## Code of Conduct
 

data/lib/rggen/systemverilog/common/factories.rb

@@ -3,7 +3,7 @@
 module RgGen
   module SystemVerilog
     module Common
-      class ComponentFactory < Core::OutputBase::ComponentFactory
+      class ComponentFactory < Core::OutputBase::SourceFileComponentFactory
       end
 
       class FeatureFactory < Core::OutputBase::FeatureFactory

data/lib/rggen/systemverilog/common/feature.rb

@@ -73,7 +73,7 @@ module RgGen
 
         def add_identifier(entity, name)
           instance_variable_set("@#{name}", entity.identifier)
-          attr_singleton_reader(name)
+          singleton_exec { attr_reader name }
           export(name)
         end
 

data/lib/rggen/systemverilog/common/utility/class_definition.rb

@@ -13,10 +13,14 @@ module RgGen
           private
 
           def header_code(code)
-            code << [:class, space, name]
+            class_header_begin(code)
             parameter_declarations(code)
             class_inheritance(code)
-            code << semicolon
+            class_header_end(code)
+          end
+
+          def class_header_begin(code)
+            code << ['class', space, name]
           end
 
           def parameter_declarations(code)
@@ -28,7 +32,11 @@ module RgGen
 
           def class_inheritance(code)
             return unless base
-            code << [space, :extends, space, base]
+            code << [space, 'extends', space, base]
+          end
+
+          def class_header_end(code)
+            code << semicolon
           end
 
           def pre_body_code(code)
@@ -36,7 +44,7 @@ module RgGen
           end
 
           def footer_code
-            :endclass
+            'endclass'
           end
         end
       end

data/lib/rggen/systemverilog/common/utility/data_object.rb

@@ -25,8 +25,7 @@ module RgGen
 
           def declaration
             declaration_snippets
-              .select(&:itself)
-              .reject(&:empty?)
+              .select { |snippet| snippet && !snippet.empty? }
               .join(' ')
           end
 

data/lib/rggen/systemverilog/common/utility/function_definition.rb

@@ -19,11 +19,15 @@ module RgGen
           private
 
           def header_code(code)
-            code << :function
+            function_header_begin(code)
             return_type_declaration(code)
-            code << [space, name]
+            function_name(code)
             argument_declarations(code)
-            code << semicolon
+            function_header_end(code)
+          end
+
+          def function_header_begin(code)
+            code << 'function'
           end
 
           def return_type_declaration(code)
@@ -31,14 +35,22 @@ module RgGen
             code << [space, return_type.declaration]
           end
 
+          def function_name(code)
+            code << space << name
+          end
+
           def argument_declarations(code)
             wrap(code, '(', ')') do
               add_declarations_to_header(code, Array(arguments))
             end
           end
 
+          def function_header_end(code)
+            code << semicolon
+          end
+
           def footer_code
-            :endfunction
+            'endfunction'
           end
         end
       end

data/lib/rggen/systemverilog/common/utility/identifier.rb

@@ -47,7 +47,7 @@ module RgGen
 
           def __create_new_identifier__(array_index_or_lsb, lsb_or_width, width)
             select = __create_select__(array_index_or_lsb, lsb_or_width, width)
-            Identifier.new("#{@name}#{select}") do |identifier|
+            self.class.new("#{@name}#{select}") do |identifier|
               identifier.__sub_identifiers__(@sub_identifiers)
             end
           end
@@ -74,24 +74,29 @@ module RgGen
           end
 
           def __serialized_lsb__(array_index, lsb)
-            serialized_index = __serialized_index__(array_index)
-            array_lsb = __reduce_array__([@width, serialized_index], :*, 1)
+            index =
+              array_index
+                .yield_self(&method(:__serialized_index__))
+                .yield_self(&method(:__enclose_index_in_parenthesis))
+            array_lsb = __reduce_array__([@width, index], :*, 1)
             __reduce_array__([array_lsb, lsb], :+, 0)
           end
 
           def __serialized_index__(array_index)
-            index_values =
-              array_index
-                .reverse
-                .zip(__index_factors__)
-                .map { |i, f| __calc_index_value__(i, f) }
-            index = __reduce_array__(index_values.reverse, :+, 0)
-            integer?(index) ? index : "(#{index})"
+            array_index
+              .reverse
+              .zip(__index_factors__)
+              .map { |i, f| __calc_index_value__(i, f) }
+              .yield_self { |values| __reduce_array__(values.reverse, :+, 0) }
+          end
+
+          def __enclose_index_in_parenthesis(index)
+            integer?(index) && index || "(#{index})"
           end
 
           def __index_factors__
             Array.new(@array_size.size) do |i|
-              i.zero? ? nil : __reduce_array__(@array_size[-i..-1], :*, 1)
+              i.zero? ? nil : __reduce_array__(@array_size[-i..], :*, 1)
             end
           end
 

data/lib/rggen/systemverilog/common/utility/local_scope.rb

@@ -17,13 +17,13 @@ module RgGen
           private
 
           def header_code(code)
-            code << [:generate, space] if @top_scope
+            code << ['generate', space] if @top_scope
             code << "if (1) begin : #{name}" << nl
           end
 
           def footer_code(code)
-            code << :end
-            code << [space, :endgenerate] if @top_scope
+            code << 'end'
+            code << [space, 'endgenerate'] if @top_scope
           end
 
           def pre_body_code(code)
@@ -58,10 +58,12 @@ module RgGen
           end
 
           def post_body_code(code)
-            (loop_size&.size || 0).times do
-              code.indent -= 2
-              code << :end << nl
-            end
+            loop_size&.size&.times { generate_for_end(code) }
+          end
+
+          def generate_for_end(code)
+            code.indent -= 2
+            code << 'end' << nl
           end
         end
       end

data/lib/rggen/systemverilog/common/utility/module_definition.rb

@@ -23,11 +23,15 @@ module RgGen
           private
 
           def header_code(code)
-            code << [:module, space, name]
+            module_header_begin(code)
             package_import_declaration(code)
             parameter_declarations(code)
             port_declarations(code)
-            code << semicolon
+            module_header_end(code)
+          end
+
+          def module_header_begin(code)
+            code << 'module' << space << name
           end
 
           def package_import_declaration(code)
@@ -41,7 +45,7 @@ module RgGen
           def pacakge_import_items
             Array(@package_imports).map.with_index do |package, i|
               if i.zero?
-                [:import, "#{package}::*"].join(space)
+                ['import', "#{package}::*"].join(space)
               else
                 [space(6), "#{package}::*"].join(space)
               end
@@ -62,12 +66,16 @@ module RgGen
             end
           end
 
+          def module_header_end(code)
+            code << semicolon
+          end
+
           def pre_body_code(code)
             add_declarations_to_body(code, Array(variables))
           end
 
           def footer_code
-            :endmodule
+            'endmodule'
           end
         end
       end

data/lib/rggen/systemverilog/common/utility/package_definition.rb

@@ -30,7 +30,7 @@ module RgGen
           private
 
           def header_code(code)
-            code << [:package, space, name, semicolon]
+            code << ['package', space, name, semicolon]
           end
 
           def pre_body_code(code)
@@ -41,18 +41,18 @@ module RgGen
           def package_import_declaration(code)
             declarations =
               Array(@package_imports)
-                .map { |package| [:import, space, package, '::*'] }
+                .map { |package| ['import', space, package, '::*'] }
             add_declarations_to_body(code, declarations)
           end
 
           def file_include_directives(code)
             Array(@include_files).each do |file|
-              code << [:'`include', space, string(file), nl]
+              code << ['`include', space, string(file), nl]
             end
           end
 
           def footer_code
-            :endpackage
+            'endpackage'
           end
         end
       end

data/lib/rggen/systemverilog/common/utility.rb

@@ -13,7 +13,7 @@ module RgGen
         private
 
         def create_identifier(name)
-          Identifier.new(name)
+          name && Identifier.new(name)
         end
 
         def assign(lhs, rhs)

data/lib/rggen/systemverilog/common.rb

@@ -1,7 +1,5 @@
 # frozen_string_literal: true
 
-require 'facets/kernel/attr_singleton'
-
 require_relative 'version'
 
 require_relative 'common/utility/identifier'

data/lib/rggen/systemverilog/ral/bit_field/type/rof.rb

@@ -0,0 +1,5 @@
+# frozen_string_literal: true
+
+RgGen.define_list_item_feature(:bit_field, :type, :rof) do
+  sv_ral { access 'RO' }
+end

data/lib/rggen/systemverilog/ral/bit_field/type/rotrg_rwtrg_wotrg.rb

@@ -0,0 +1,9 @@
+# frozen_string_literal: true
+
+RgGen.define_list_item_feature(:bit_field, :type, [:rotrg, :rwtrg, :wotrg]) do
+  sv_ral do
+    access do
+      { rotrg: :ro, rwtrg: :rw, wotrg: :wo }[bit_field.type]
+    end
+  end
+end

data/lib/rggen/systemverilog/ral/bit_field/type/rowo_rowotrg.rb

@@ -0,0 +1,8 @@
+# frozen_string_literal: true
+
+RgGen.define_list_item_feature(:bit_field, :type, [:rowo, :rowotrg]) do
+  sv_ral do
+    access 'rowo'
+    model_name { 'rggen_ral_rowo_field' }
+  end
+end

data/lib/rggen/systemverilog/ral/bit_field/type.rb

@@ -4,11 +4,20 @@ RgGen.define_list_feature(:bit_field, :type) do
   sv_ral do
     base_feature do
       define_helpers do
-        attr_setter :access
+        def access(access_type = nil, &block)
+          attribute_accessor('@access', access_type, &block)
+        end
 
         def model_name(name = nil, &block)
-          @model_name = name || block || @model_name
-          @model_name
+          attribute_accessor('@model_name', name, &block)
+        end
+
+        private
+
+        def attribute_accessor(variable_name, value, &block)
+          (new_value = value || block) &&
+            instance_variable_set(variable_name, new_value)
+          instance_variable_get(variable_name)
         end
       end
 
@@ -24,17 +33,16 @@ RgGen.define_list_feature(:bit_field, :type) do
       end
 
       def access
-        (helper.access || bit_field.type).to_s.upcase
+        eval_attribute(:access, bit_field.type).to_s.upcase
       end
 
       def model_name
-        name = helper.model_name
-        name.is_a?(Proc) && instance_eval(&name) || name || :rggen_ral_field
+        eval_attribute(:model_name, 'rggen_ral_field')
       end
 
       def constructors
         (bit_field.sequence_size&.times || [nil]).map do |index|
-          macro_call(:rggen_ral_create_field, arguments(index))
+          macro_call('rggen_ral_create_field', arguments(index))
         end
       end
 
@@ -73,6 +81,11 @@ RgGen.define_list_feature(:bit_field, :type) do
           ''
         end
       end
+
+      def eval_attribute(attribute, default_value)
+        value = helper.__send__(attribute)
+        value.is_a?(Proc) && instance_eval(&value) || value || default_value
+      end
     end
 
     default_feature do

data/lib/rggen/systemverilog/ral/register_common.rb

@@ -9,7 +9,7 @@ module RgGen
         def array_indices
           if component.array?
             index_table = component.array_size.map { |size| (0...size).to_a }
-            index_table[0].product(*index_table[1..-1])
+            index_table[0].product(*index_table[1..])
           else
             [nil]
           end

data/lib/rggen/systemverilog/ral.rb

@@ -19,7 +19,9 @@ module RgGen
 
         plugin.files [
           'ral/bit_field/type',
-          'ral/bit_field/type/reserved_rof',
+          'ral/bit_field/type/rof',
+          'ral/bit_field/type/rotrg_rwtrg_wotrg',
+          'ral/bit_field/type/rowo_rowotrg',
           'ral/bit_field/type/rwc_rws',
           'ral/bit_field/type/rwe_rwl',
           'ral/bit_field/type/w0trg_w1trg',

data/lib/rggen/systemverilog/rtl/bit_field/sv_rtl_top.rb

@@ -116,7 +116,7 @@ RgGen.define_simple_feature(:bit_field, :sv_rtl_top) do
 
     def bit_field_if_connection
       macro_call(
-        :rggen_connect_bit_field_if,
+        'rggen_connect_bit_field_if',
         [
           register.bit_field_if,
           bit_field.bit_field_sub_if,

data/lib/rggen/systemverilog/rtl/bit_field/type/rc_w0c_w1c_wc_woc.erb

@@ -7,6 +7,8 @@ rggen_bit_field #(
   .i_clk              (<%= clock %>),
   .i_rst_n            (<%= reset %>),
   .bit_field_if       (<%= bit_field_if %>),
+  .o_write_trigger    (),
+  .o_read_trigger     (),
   .i_sw_write_enable  (<%= write_enable %>),
   .i_hw_write_enable  ('0),
   .i_hw_write_data    ('0),

data/lib/rggen/systemverilog/rtl/bit_field/type/rc_w0c_w1c_wc_woc.rb

@@ -4,16 +4,16 @@ RgGen.define_list_item_feature(:bit_field, :type, [:rc, :w0c, :w1c, :wc, :woc])
   sv_rtl do
     build do
       input :set, {
-        name: "i_#{full_name}_set", data_type: :logic, width: width,
+        name: "i_#{full_name}_set", width: width,
         array_size: array_size, array_format: array_port_format
       }
       output :value_out, {
-        name: "o_#{full_name}", data_type: :logic, width: width,
+        name: "o_#{full_name}", width: width,
         array_size: array_size, array_format: array_port_format
       }
       if bit_field.reference?
         output :value_unmasked, {
-          name: "o_#{full_name}_unmasked", data_type: :logic, width: width,
+          name: "o_#{full_name}_unmasked", width: width,
           array_size: array_size, array_format: array_port_format
         }
       end

data/lib/rggen/systemverilog/rtl/bit_field/type/{ro.erb → ro_rotrg.erb}

@@ -1,10 +1,14 @@
 rggen_bit_field #(
-  .WIDTH    (<%= width %>),
-  .STORAGE  (0)
+  .WIDTH              (<%= width %>),
+  .STORAGE            (0),
+  .EXTERNAL_READ_DATA (1),
+  .TRIGGER            (<%= trigger %>)
 ) u_bit_field (
-  .i_clk              ('0),
-  .i_rst_n            ('0),
+  .i_clk              (<%= clock %>),
+  .i_rst_n            (<%= reset %>),
   .bit_field_if       (<%= bit_field_if %>),
+  .o_write_trigger    (),
+  .o_read_trigger     (<%= read_trigger_signal %>),
   .i_sw_write_enable  ('0),
   .i_hw_write_enable  ('0),
   .i_hw_write_data    ('0),

data/lib/rggen/systemverilog/rtl/bit_field/type/ro_rotrg.rb

@@ -0,0 +1,40 @@
+# frozen_string_literal: true
+
+RgGen.define_list_item_feature(:bit_field, :type, [:ro, :rotrg]) do
+  sv_rtl do
+    build do
+      unless bit_field.reference?
+        input :value_in, {
+          name: "i_#{full_name}", width: width,
+          array_size: array_size, array_format: array_port_format
+        }
+      end
+      if rotrg?
+        output :read_trigger, {
+          name: "o_#{full_name}_read_trigger", width: 1,
+          array_size: array_size, array_format: array_port_format
+        }
+      end
+    end
+
+    main_code :bit_field, from_template: true
+
+    private
+
+    def rotrg?
+      bit_field.type == :rotrg
+    end
+
+    def trigger
+      rotrg? && 1 || 0
+    end
+
+    def read_trigger_signal
+      rotrg? && read_trigger[loop_variables] || nil
+    end
+
+    def reference_or_value_in
+      reference_bit_field || value_in[loop_variables]
+    end
+  end
+end

data/lib/rggen/systemverilog/rtl/bit_field/type/rof.erb

@@ -1,10 +1,13 @@
 rggen_bit_field #(
-  .WIDTH    (<%= width %>),
-  .STORAGE  (0)
+  .WIDTH              (<%= width %>),
+  .STORAGE            (0),
+  .EXTERNAL_READ_DATA (1)
 ) u_bit_field (
   .i_clk              ('0),
   .i_rst_n            ('0),
   .bit_field_if       (<%= bit_field_if %>),
+  .o_write_trigger    (),
+  .o_read_trigger     (),
   .i_sw_write_enable  ('0),
   .i_hw_write_enable  ('0),
   .i_hw_write_data    ('0),

data/lib/rggen/systemverilog/rtl/bit_field/type/rowo_rowotrg.erb

@@ -0,0 +1,21 @@
+rggen_bit_field #(
+  .WIDTH              (<%= width %>),
+  .INITIAL_VALUE      (<%= initial_value %>),
+  .EXTERNAL_READ_DATA (1),
+  .TRIGGER            (<%= trigger %>)
+) u_bit_field (
+  .i_clk              (<%= clock %>),
+  .i_rst_n            (<%= reset %>),
+  .bit_field_if       (<%= bit_field_if %>),
+  .o_write_trigger    (<%= write_trigger_signal %>),
+  .o_read_trigger     (<%= read_trigger_signal %>),
+  .i_sw_write_enable  ('1),
+  .i_hw_write_enable  ('0),
+  .i_hw_write_data    ('0),
+  .i_hw_set           ('0),
+  .i_hw_clear         ('0),
+  .i_value            (<%= reference_or_value_in %>),
+  .i_mask             ('1),
+  .o_value            (<%= value_out[loop_variables] %>),
+  .o_value_unmasked   ()
+);

data/lib/rggen/systemverilog/rtl/bit_field/type/rowo_rowotrg.rb

@@ -0,0 +1,52 @@
+# frozen_string_literal: true
+
+RgGen.define_list_item_feature(:bit_field, :type, [:rowo, :rowotrg]) do
+  sv_rtl do
+    build do
+      output :value_out, {
+        name: "o_#{full_name}", width: width,
+        array_size: array_size, array_format: array_port_format
+      }
+      unless bit_field.reference?
+        input :value_in, {
+          name: "i_#{full_name}", width: width,
+          array_size: array_size, array_format: array_port_format
+        }
+      end
+      if rowotrg?
+        output :write_trigger, {
+          name: "o_#{full_name}_write_trigger", width: 1,
+          array_size: array_size, array_format: array_port_format
+        }
+        output :read_trigger, {
+          name: "o_#{full_name}_read_trigger", width: 1,
+          array_size: array_size, array_format: array_port_format
+        }
+      end
+    end
+
+    main_code :bit_field, from_template: true
+
+    private
+
+    def rowotrg?
+      bit_field.type == :rowotrg
+    end
+
+    def trigger
+      rowotrg? && 1 || 0
+    end
+
+    def write_trigger_signal
+      rowotrg? && write_trigger[loop_variables] || nil
+    end
+
+    def read_trigger_signal
+      rowotrg? && read_trigger[loop_variables] || nil
+    end
+
+    def reference_or_value_in
+      reference_bit_field || value_in[loop_variables]
+    end
+  end
+end

data/lib/rggen/systemverilog/rtl/bit_field/type/rs_w0s_w1s_ws_wos.erb

@@ -7,6 +7,8 @@ rggen_bit_field #(
   .i_clk              (<%= clock %>),
   .i_rst_n            (<%= reset %>),
   .bit_field_if       (<%= bit_field_if %>),
+  .o_write_trigger    (),
+  .o_read_trigger     (),
   .i_sw_write_enable  (<%= write_enable %>),
   .i_hw_write_enable  ('0),
   .i_hw_write_data    ('0),

data/lib/rggen/systemverilog/rtl/bit_field/type/rs_w0s_w1s_ws_wos.rb

@@ -4,11 +4,11 @@ RgGen.define_list_item_feature(:bit_field, :type, [:rs, :w0s, :w1s, :ws, :wos])
   sv_rtl do
     build do
       input :clear, {
-        name: "i_#{full_name}_clear", data_type: :logic, width: width,
+        name: "i_#{full_name}_clear", width: width,
         array_size: array_size, array_format: array_port_format
       }
       output :value_out, {
-        name: "o_#{full_name}", data_type: :logic, width: width,
+        name: "o_#{full_name}", width: width,
         array_size: array_size, array_format: array_port_format
       }
     end