rggen-systemverilog 0.24.0 → 0.26.0
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- checksums.yaml +4 -4
- data/LICENSE +1 -1
- data/README.md +1 -1
- data/lib/rggen/systemverilog/common/factories.rb +1 -1
- data/lib/rggen/systemverilog/common/feature.rb +1 -1
- data/lib/rggen/systemverilog/common/utility/class_definition.rb +12 -4
- data/lib/rggen/systemverilog/common/utility/data_object.rb +1 -2
- data/lib/rggen/systemverilog/common/utility/function_definition.rb +16 -4
- data/lib/rggen/systemverilog/common/utility/identifier.rb +16 -11
- data/lib/rggen/systemverilog/common/utility/local_scope.rb +9 -7
- data/lib/rggen/systemverilog/common/utility/module_definition.rb +12 -4
- data/lib/rggen/systemverilog/common/utility/package_definition.rb +4 -4
- data/lib/rggen/systemverilog/common/utility.rb +1 -1
- data/lib/rggen/systemverilog/common.rb +0 -2
- data/lib/rggen/systemverilog/ral/bit_field/type/rof.rb +5 -0
- data/lib/rggen/systemverilog/ral/bit_field/type/rotrg_rwtrg_wotrg.rb +9 -0
- data/lib/rggen/systemverilog/ral/bit_field/type/rowo_rowotrg.rb +8 -0
- data/lib/rggen/systemverilog/ral/bit_field/type.rb +20 -7
- data/lib/rggen/systemverilog/ral/register_common.rb +1 -1
- data/lib/rggen/systemverilog/ral.rb +3 -1
- data/lib/rggen/systemverilog/rtl/bit_field/sv_rtl_top.rb +1 -1
- data/lib/rggen/systemverilog/rtl/bit_field/type/rc_w0c_w1c_wc_woc.erb +2 -0
- data/lib/rggen/systemverilog/rtl/bit_field/type/rc_w0c_w1c_wc_woc.rb +3 -3
- data/lib/rggen/systemverilog/rtl/bit_field/type/{ro.erb → ro_rotrg.erb} +8 -4
- data/lib/rggen/systemverilog/rtl/bit_field/type/ro_rotrg.rb +40 -0
- data/lib/rggen/systemverilog/rtl/bit_field/type/rof.erb +5 -2
- data/lib/rggen/systemverilog/rtl/bit_field/type/rowo_rowotrg.erb +21 -0
- data/lib/rggen/systemverilog/rtl/bit_field/type/rowo_rowotrg.rb +52 -0
- data/lib/rggen/systemverilog/rtl/bit_field/type/rs_w0s_w1s_ws_wos.erb +2 -0
- data/lib/rggen/systemverilog/rtl/bit_field/type/rs_w0s_w1s_ws_wos.rb +2 -2
- data/lib/rggen/systemverilog/rtl/bit_field/type/{rw_w1_wo_wo1.erb → rw_rwtrg_w1.erb} +4 -2
- data/lib/rggen/systemverilog/rtl/bit_field/type/rw_rwtrg_w1.rb +46 -0
- data/lib/rggen/systemverilog/rtl/bit_field/type/rwc.erb +2 -0
- data/lib/rggen/systemverilog/rtl/bit_field/type/rwc.rb +2 -2
- data/lib/rggen/systemverilog/rtl/bit_field/type/{rwl.erb → rwe_rwl.erb} +4 -2
- data/lib/rggen/systemverilog/rtl/bit_field/type/rwe_rwl.rb +34 -0
- data/lib/rggen/systemverilog/rtl/bit_field/type/rws.erb +2 -0
- data/lib/rggen/systemverilog/rtl/bit_field/type/rws.rb +3 -3
- data/lib/rggen/systemverilog/rtl/bit_field/type/w0crs_w0src_w1crs_w1src_wcrs_wsrc.erb +2 -0
- data/lib/rggen/systemverilog/rtl/bit_field/type/w0crs_w0src_w1crs_w1src_wcrs_wsrc.rb +1 -1
- data/lib/rggen/systemverilog/rtl/bit_field/type/w0t_w1t.erb +2 -0
- data/lib/rggen/systemverilog/rtl/bit_field/type/w0t_w1t.rb +1 -1
- data/lib/rggen/systemverilog/rtl/bit_field/type/w0trg_w1trg.rb +1 -1
- data/lib/rggen/systemverilog/rtl/bit_field/type/{rwe.erb → wo_wo1_wotrg.erb} +8 -4
- data/lib/rggen/systemverilog/rtl/bit_field/type/wo_wo1_wotrg.rb +38 -0
- data/lib/rggen/systemverilog/rtl/bit_field/type/wrc_wrs.erb +2 -0
- data/lib/rggen/systemverilog/rtl/bit_field/type/wrc_wrs.rb +1 -1
- data/lib/rggen/systemverilog/rtl/bit_field_index.rb +1 -2
- data/lib/rggen/systemverilog/rtl/feature.rb +8 -6
- data/lib/rggen/systemverilog/rtl/partial_sum.rb +5 -6
- data/lib/rggen/systemverilog/rtl/register/type/external.rb +5 -62
- data/lib/rggen/systemverilog/rtl/register_block/protocol/apb.rb +3 -60
- data/lib/rggen/systemverilog/rtl/register_block/protocol/axi4lite.rb +4 -118
- data/lib/rggen/systemverilog/rtl/register_block/protocol/wishbone.erb +17 -0
- data/lib/rggen/systemverilog/rtl/register_block/protocol/wishbone.rb +26 -0
- data/lib/rggen/systemverilog/rtl/register_block/sv_rtl_top.rb +2 -6
- data/lib/rggen/systemverilog/rtl/register_index.rb +13 -11
- data/lib/rggen/systemverilog/rtl/register_type.rb +4 -3
- data/lib/rggen/systemverilog/rtl/setup.rb +2 -4
- data/lib/rggen/systemverilog/rtl.rb +6 -6
- data/lib/rggen/systemverilog/version.rb +1 -1
- metadata +21 -31
- data/lib/rggen/systemverilog/ral/bit_field/type/reserved_rof.rb +0 -5
- data/lib/rggen/systemverilog/rtl/bit_field/type/reserved.erb +0 -18
- data/lib/rggen/systemverilog/rtl/bit_field/type/reserved.rb +0 -7
- data/lib/rggen/systemverilog/rtl/bit_field/type/ro.rb +0 -22
- data/lib/rggen/systemverilog/rtl/bit_field/type/rw_w1_wo_wo1.rb +0 -24
- data/lib/rggen/systemverilog/rtl/bit_field/type/rwe.rb +0 -26
- data/lib/rggen/systemverilog/rtl/bit_field/type/rwl.rb +0 -26
- data/lib/rggen/systemverilog/rtl/global/fold_sv_interface_port.rb +0 -28
checksums.yaml
CHANGED
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---
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SHA256:
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metadata.gz:
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data.tar.gz:
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metadata.gz: 6093eea4b475c6dddb948d2b0bb5053705cc64f38a5603c925d0ab04029e0978
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data.tar.gz: e2c07ce7eb68f15c9e4d2dbd0f83d7a74dbcb92ba292ba1fae8830c4ca147cb0
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SHA512:
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metadata.gz:
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data.tar.gz:
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metadata.gz: 2d460b5eecdc50fbae20514b7f814fd98774b6dcb05ab72df2936301a9218870609eb1236b13f9a305d1882f001360eb84537b083c5323d2fde475fe170ffaed
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data.tar.gz: 4ea6fb47189ec224f30701198d9a51de4ab68cbc2a601b048ad23b1edcda1308214218fd456550c2e8d085c3575ab2aeec7e58c43d6337dba81111c0e8f0b07f
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data/LICENSE
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The MIT License (MIT)
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Copyright (c) 2019-
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Copyright (c) 2019-2022 Taichi Ishitani
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Permission is hereby granted, free of charge, to any person obtaining a copy
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of this software and associated documentation files (the "Software"), to deal
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data/README.md
CHANGED
@@ -34,7 +34,7 @@ Feedbacks, bug reports, questions and etc. are wellcome! You can post them by us
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## Copyright & License
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Copyright © 2019-
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Copyright © 2019-2022 Taichi Ishitani. RgGen::SystemVerilog is licensed under the [MIT License](https://opensource.org/licenses/MIT), see [LICENSE](LICENSE) for futher details.
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## Code of Conduct
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@@ -13,10 +13,14 @@ module RgGen
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private
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def header_code(code)
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code
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class_header_begin(code)
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parameter_declarations(code)
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class_inheritance(code)
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-
code
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class_header_end(code)
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end
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def class_header_begin(code)
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code << ['class', space, name]
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end
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def parameter_declarations(code)
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def class_inheritance(code)
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return unless base
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code << [space,
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code << [space, 'extends', space, base]
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end
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def class_header_end(code)
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code << semicolon
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end
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def pre_body_code(code)
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end
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def footer_code
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-
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'endclass'
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end
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end
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end
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private
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def header_code(code)
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-
code
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function_header_begin(code)
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return_type_declaration(code)
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-
code
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function_name(code)
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argument_declarations(code)
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-
code
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function_header_end(code)
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end
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def function_header_begin(code)
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code << 'function'
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end
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def return_type_declaration(code)
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code << [space, return_type.declaration]
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end
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def function_name(code)
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code << space << name
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end
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def argument_declarations(code)
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wrap(code, '(', ')') do
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add_declarations_to_header(code, Array(arguments))
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end
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end
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def function_header_end(code)
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code << semicolon
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end
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def footer_code
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-
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'endfunction'
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end
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end
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end
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def __create_new_identifier__(array_index_or_lsb, lsb_or_width, width)
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select = __create_select__(array_index_or_lsb, lsb_or_width, width)
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-
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self.class.new("#{@name}#{select}") do |identifier|
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identifier.__sub_identifiers__(@sub_identifiers)
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end
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end
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end
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def __serialized_lsb__(array_index, lsb)
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index =
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array_index
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.yield_self(&method(:__serialized_index__))
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.yield_self(&method(:__enclose_index_in_parenthesis))
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array_lsb = __reduce_array__([@width, index], :*, 1)
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__reduce_array__([array_lsb, lsb], :+, 0)
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end
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def __serialized_index__(array_index)
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array_index
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.reverse
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.zip(__index_factors__)
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.map { |i, f| __calc_index_value__(i, f) }
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.yield_self { |values| __reduce_array__(values.reverse, :+, 0) }
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end
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def __enclose_index_in_parenthesis(index)
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integer?(index) && index || "(#{index})"
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end
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def __index_factors__
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Array.new(@array_size.size) do |i|
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i.zero? ? nil : __reduce_array__(@array_size[-i
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i.zero? ? nil : __reduce_array__(@array_size[-i..], :*, 1)
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end
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end
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private
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def header_code(code)
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code << [
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code << ['generate', space] if @top_scope
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code << "if (1) begin : #{name}" << nl
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end
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def footer_code(code)
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code <<
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code << [space,
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code << 'end'
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code << [space, 'endgenerate'] if @top_scope
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end
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def pre_body_code(code)
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end
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def post_body_code(code)
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loop_size&.size&.times { generate_for_end(code) }
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end
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def generate_for_end(code)
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code.indent -= 2
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code << 'end' << nl
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end
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end
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end
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private
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def header_code(code)
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code
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module_header_begin(code)
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package_import_declaration(code)
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parameter_declarations(code)
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port_declarations(code)
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code
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module_header_end(code)
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end
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def module_header_begin(code)
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code << 'module' << space << name
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end
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def package_import_declaration(code)
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def pacakge_import_items
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Array(@package_imports).map.with_index do |package, i|
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if i.zero?
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[
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['import', "#{package}::*"].join(space)
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else
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[space(6), "#{package}::*"].join(space)
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end
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@@ -62,12 +66,16 @@ module RgGen
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end
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end
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def module_header_end(code)
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code << semicolon
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end
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def pre_body_code(code)
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add_declarations_to_body(code, Array(variables))
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end
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def footer_code
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-
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'endmodule'
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end
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end
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end
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private
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def header_code(code)
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code << [
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code << ['package', space, name, semicolon]
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end
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def pre_body_code(code)
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def package_import_declaration(code)
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declarations =
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Array(@package_imports)
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.map { |package| [
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.map { |package| ['import', space, package, '::*'] }
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add_declarations_to_body(code, declarations)
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end
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def file_include_directives(code)
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Array(@include_files).each do |file|
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-
code << [
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code << ['`include', space, string(file), nl]
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end
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end
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def footer_code
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-
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+
'endpackage'
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end
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end
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end
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@@ -4,11 +4,20 @@ RgGen.define_list_feature(:bit_field, :type) do
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sv_ral do
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base_feature do
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define_helpers do
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-
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def access(access_type = nil, &block)
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attribute_accessor('@access', access_type, &block)
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end
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def model_name(name = nil, &block)
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@model_name
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-
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attribute_accessor('@model_name', name, &block)
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end
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private
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def attribute_accessor(variable_name, value, &block)
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(new_value = value || block) &&
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instance_variable_set(variable_name, new_value)
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instance_variable_get(variable_name)
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end
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end
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@@ -24,17 +33,16 @@ RgGen.define_list_feature(:bit_field, :type) do
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end
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25
34
|
|
26
35
|
def access
|
27
|
-
(
|
36
|
+
eval_attribute(:access, bit_field.type).to_s.upcase
|
28
37
|
end
|
29
38
|
|
30
39
|
def model_name
|
31
|
-
|
32
|
-
name.is_a?(Proc) && instance_eval(&name) || name || :rggen_ral_field
|
40
|
+
eval_attribute(:model_name, 'rggen_ral_field')
|
33
41
|
end
|
34
42
|
|
35
43
|
def constructors
|
36
44
|
(bit_field.sequence_size&.times || [nil]).map do |index|
|
37
|
-
macro_call(
|
45
|
+
macro_call('rggen_ral_create_field', arguments(index))
|
38
46
|
end
|
39
47
|
end
|
40
48
|
|
@@ -73,6 +81,11 @@ RgGen.define_list_feature(:bit_field, :type) do
|
|
73
81
|
''
|
74
82
|
end
|
75
83
|
end
|
84
|
+
|
85
|
+
def eval_attribute(attribute, default_value)
|
86
|
+
value = helper.__send__(attribute)
|
87
|
+
value.is_a?(Proc) && instance_eval(&value) || value || default_value
|
88
|
+
end
|
76
89
|
end
|
77
90
|
|
78
91
|
default_feature do
|
@@ -19,7 +19,9 @@ module RgGen
|
|
19
19
|
|
20
20
|
plugin.files [
|
21
21
|
'ral/bit_field/type',
|
22
|
-
'ral/bit_field/type/
|
22
|
+
'ral/bit_field/type/rof',
|
23
|
+
'ral/bit_field/type/rotrg_rwtrg_wotrg',
|
24
|
+
'ral/bit_field/type/rowo_rowotrg',
|
23
25
|
'ral/bit_field/type/rwc_rws',
|
24
26
|
'ral/bit_field/type/rwe_rwl',
|
25
27
|
'ral/bit_field/type/w0trg_w1trg',
|
@@ -4,16 +4,16 @@ RgGen.define_list_item_feature(:bit_field, :type, [:rc, :w0c, :w1c, :wc, :woc])
|
|
4
4
|
sv_rtl do
|
5
5
|
build do
|
6
6
|
input :set, {
|
7
|
-
name: "i_#{full_name}_set",
|
7
|
+
name: "i_#{full_name}_set", width: width,
|
8
8
|
array_size: array_size, array_format: array_port_format
|
9
9
|
}
|
10
10
|
output :value_out, {
|
11
|
-
name: "o_#{full_name}",
|
11
|
+
name: "o_#{full_name}", width: width,
|
12
12
|
array_size: array_size, array_format: array_port_format
|
13
13
|
}
|
14
14
|
if bit_field.reference?
|
15
15
|
output :value_unmasked, {
|
16
|
-
name: "o_#{full_name}_unmasked",
|
16
|
+
name: "o_#{full_name}_unmasked", width: width,
|
17
17
|
array_size: array_size, array_format: array_port_format
|
18
18
|
}
|
19
19
|
end
|
@@ -1,10 +1,14 @@
|
|
1
1
|
rggen_bit_field #(
|
2
|
-
.WIDTH
|
3
|
-
.STORAGE
|
2
|
+
.WIDTH (<%= width %>),
|
3
|
+
.STORAGE (0),
|
4
|
+
.EXTERNAL_READ_DATA (1),
|
5
|
+
.TRIGGER (<%= trigger %>)
|
4
6
|
) u_bit_field (
|
5
|
-
.i_clk (
|
6
|
-
.i_rst_n (
|
7
|
+
.i_clk (<%= clock %>),
|
8
|
+
.i_rst_n (<%= reset %>),
|
7
9
|
.bit_field_if (<%= bit_field_if %>),
|
10
|
+
.o_write_trigger (),
|
11
|
+
.o_read_trigger (<%= read_trigger_signal %>),
|
8
12
|
.i_sw_write_enable ('0),
|
9
13
|
.i_hw_write_enable ('0),
|
10
14
|
.i_hw_write_data ('0),
|
@@ -0,0 +1,40 @@
|
|
1
|
+
# frozen_string_literal: true
|
2
|
+
|
3
|
+
RgGen.define_list_item_feature(:bit_field, :type, [:ro, :rotrg]) do
|
4
|
+
sv_rtl do
|
5
|
+
build do
|
6
|
+
unless bit_field.reference?
|
7
|
+
input :value_in, {
|
8
|
+
name: "i_#{full_name}", width: width,
|
9
|
+
array_size: array_size, array_format: array_port_format
|
10
|
+
}
|
11
|
+
end
|
12
|
+
if rotrg?
|
13
|
+
output :read_trigger, {
|
14
|
+
name: "o_#{full_name}_read_trigger", width: 1,
|
15
|
+
array_size: array_size, array_format: array_port_format
|
16
|
+
}
|
17
|
+
end
|
18
|
+
end
|
19
|
+
|
20
|
+
main_code :bit_field, from_template: true
|
21
|
+
|
22
|
+
private
|
23
|
+
|
24
|
+
def rotrg?
|
25
|
+
bit_field.type == :rotrg
|
26
|
+
end
|
27
|
+
|
28
|
+
def trigger
|
29
|
+
rotrg? && 1 || 0
|
30
|
+
end
|
31
|
+
|
32
|
+
def read_trigger_signal
|
33
|
+
rotrg? && read_trigger[loop_variables] || nil
|
34
|
+
end
|
35
|
+
|
36
|
+
def reference_or_value_in
|
37
|
+
reference_bit_field || value_in[loop_variables]
|
38
|
+
end
|
39
|
+
end
|
40
|
+
end
|
@@ -1,10 +1,13 @@
|
|
1
1
|
rggen_bit_field #(
|
2
|
-
.WIDTH
|
3
|
-
.STORAGE
|
2
|
+
.WIDTH (<%= width %>),
|
3
|
+
.STORAGE (0),
|
4
|
+
.EXTERNAL_READ_DATA (1)
|
4
5
|
) u_bit_field (
|
5
6
|
.i_clk ('0),
|
6
7
|
.i_rst_n ('0),
|
7
8
|
.bit_field_if (<%= bit_field_if %>),
|
9
|
+
.o_write_trigger (),
|
10
|
+
.o_read_trigger (),
|
8
11
|
.i_sw_write_enable ('0),
|
9
12
|
.i_hw_write_enable ('0),
|
10
13
|
.i_hw_write_data ('0),
|
@@ -0,0 +1,21 @@
|
|
1
|
+
rggen_bit_field #(
|
2
|
+
.WIDTH (<%= width %>),
|
3
|
+
.INITIAL_VALUE (<%= initial_value %>),
|
4
|
+
.EXTERNAL_READ_DATA (1),
|
5
|
+
.TRIGGER (<%= trigger %>)
|
6
|
+
) u_bit_field (
|
7
|
+
.i_clk (<%= clock %>),
|
8
|
+
.i_rst_n (<%= reset %>),
|
9
|
+
.bit_field_if (<%= bit_field_if %>),
|
10
|
+
.o_write_trigger (<%= write_trigger_signal %>),
|
11
|
+
.o_read_trigger (<%= read_trigger_signal %>),
|
12
|
+
.i_sw_write_enable ('1),
|
13
|
+
.i_hw_write_enable ('0),
|
14
|
+
.i_hw_write_data ('0),
|
15
|
+
.i_hw_set ('0),
|
16
|
+
.i_hw_clear ('0),
|
17
|
+
.i_value (<%= reference_or_value_in %>),
|
18
|
+
.i_mask ('1),
|
19
|
+
.o_value (<%= value_out[loop_variables] %>),
|
20
|
+
.o_value_unmasked ()
|
21
|
+
);
|
@@ -0,0 +1,52 @@
|
|
1
|
+
# frozen_string_literal: true
|
2
|
+
|
3
|
+
RgGen.define_list_item_feature(:bit_field, :type, [:rowo, :rowotrg]) do
|
4
|
+
sv_rtl do
|
5
|
+
build do
|
6
|
+
output :value_out, {
|
7
|
+
name: "o_#{full_name}", width: width,
|
8
|
+
array_size: array_size, array_format: array_port_format
|
9
|
+
}
|
10
|
+
unless bit_field.reference?
|
11
|
+
input :value_in, {
|
12
|
+
name: "i_#{full_name}", width: width,
|
13
|
+
array_size: array_size, array_format: array_port_format
|
14
|
+
}
|
15
|
+
end
|
16
|
+
if rowotrg?
|
17
|
+
output :write_trigger, {
|
18
|
+
name: "o_#{full_name}_write_trigger", width: 1,
|
19
|
+
array_size: array_size, array_format: array_port_format
|
20
|
+
}
|
21
|
+
output :read_trigger, {
|
22
|
+
name: "o_#{full_name}_read_trigger", width: 1,
|
23
|
+
array_size: array_size, array_format: array_port_format
|
24
|
+
}
|
25
|
+
end
|
26
|
+
end
|
27
|
+
|
28
|
+
main_code :bit_field, from_template: true
|
29
|
+
|
30
|
+
private
|
31
|
+
|
32
|
+
def rowotrg?
|
33
|
+
bit_field.type == :rowotrg
|
34
|
+
end
|
35
|
+
|
36
|
+
def trigger
|
37
|
+
rowotrg? && 1 || 0
|
38
|
+
end
|
39
|
+
|
40
|
+
def write_trigger_signal
|
41
|
+
rowotrg? && write_trigger[loop_variables] || nil
|
42
|
+
end
|
43
|
+
|
44
|
+
def read_trigger_signal
|
45
|
+
rowotrg? && read_trigger[loop_variables] || nil
|
46
|
+
end
|
47
|
+
|
48
|
+
def reference_or_value_in
|
49
|
+
reference_bit_field || value_in[loop_variables]
|
50
|
+
end
|
51
|
+
end
|
52
|
+
end
|
@@ -4,11 +4,11 @@ RgGen.define_list_item_feature(:bit_field, :type, [:rs, :w0s, :w1s, :ws, :wos])
|
|
4
4
|
sv_rtl do
|
5
5
|
build do
|
6
6
|
input :clear, {
|
7
|
-
name: "i_#{full_name}_clear",
|
7
|
+
name: "i_#{full_name}_clear", width: width,
|
8
8
|
array_size: array_size, array_format: array_port_format
|
9
9
|
}
|
10
10
|
output :value_out, {
|
11
|
-
name: "o_#{full_name}",
|
11
|
+
name: "o_#{full_name}", width: width,
|
12
12
|
array_size: array_size, array_format: array_port_format
|
13
13
|
}
|
14
14
|
end
|