rggen-systemverilog 0.24.0 → 0.26.0

data/lib/rggen/systemverilog/rtl/bit_field/type/{rw_w1_wo_wo1.erb → rw_rwtrg_w1.erb}

@@ -1,12 +1,14 @@
 rggen_bit_field #(
   .WIDTH          (<%= width %>),
   .INITIAL_VALUE  (<%= initial_value %>),
-  .SW_READ_ACTION (<%= read_action %>),
-  .SW_WRITE_ONCE  (<%= write_once %>)
+  .SW_WRITE_ONCE  (<%= write_once %>),
+  .TRIGGER        (<%= trigger %>)
 ) u_bit_field (
   .i_clk              (<%= clock %>),
   .i_rst_n            (<%= reset %>),
   .bit_field_if       (<%= bit_field_if %>),
+  .o_write_trigger    (<%= write_trigger_signal %>),
+  .o_read_trigger     (<%= read_trigger_signal %>),
   .i_sw_write_enable  ('1),
   .i_hw_write_enable  ('0),
   .i_hw_write_data    ('0),

data/lib/rggen/systemverilog/rtl/bit_field/type/rw_rwtrg_w1.rb

@@ -0,0 +1,46 @@
+# frozen_string_literal: true
+
+RgGen.define_list_item_feature(:bit_field, :type, [:rw, :rwtrg, :w1]) do
+  sv_rtl do
+    build do
+      output :value_out, {
+        name: "o_#{full_name}", width: width,
+        array_size: array_size, array_format: array_port_format
+      }
+      if rwtrg?
+        output :write_trigger, {
+          name: "o_#{full_name}_write_trigger", width: 1,
+          array_size: array_size, array_format: array_port_format
+        }
+        output :read_trigger, {
+          name: "o_#{full_name}_read_trigger", width: 1,
+          array_size: array_size, array_format: array_port_format
+        }
+      end
+    end
+
+    main_code :bit_field, from_template: true
+
+    private
+
+    def rwtrg?
+      bit_field.type == :rwtrg
+    end
+
+    def trigger
+      rwtrg? && 1 || 0
+    end
+
+    def write_trigger_signal
+      rwtrg? && write_trigger[loop_variables] || nil
+    end
+
+    def read_trigger_signal
+      rwtrg? && read_trigger[loop_variables] || nil
+    end
+
+    def write_once
+      bit_field.type == :w1 && 1 || 0
+    end
+  end
+end

data/lib/rggen/systemverilog/rtl/bit_field/type/rwc.erb

@@ -6,6 +6,8 @@ rggen_bit_field #(
   .i_clk              (<%= clock %>),
   .i_rst_n            (<%= reset %>),
   .bit_field_if       (<%= bit_field_if %>),
+  .o_write_trigger    (),
+  .o_read_trigger     (),
   .i_sw_write_enable  ('1),
   .i_hw_write_enable  ('0),
   .i_hw_write_data    ('0),

data/lib/rggen/systemverilog/rtl/bit_field/type/rwc.rb

@@ -5,12 +5,12 @@ RgGen.define_list_item_feature(:bit_field, :type, :rwc) do
     build do
       unless bit_field.reference?
         input :clear, {
-          name: "i_#{full_name}_clear", data_type: :logic, width: 1,
+          name: "i_#{full_name}_clear", width: 1,
           array_size: array_size, array_format: array_port_format
         }
       end
       output :value_out, {
-        name: "o_#{full_name}", data_type: :logic, width: width,
+        name: "o_#{full_name}", width: width,
         array_size: array_size, array_format: array_port_format
       }
     end

data/lib/rggen/systemverilog/rtl/bit_field/type/{rwl.erb → rwe_rwl.erb}

@@ -1,12 +1,14 @@
 rggen_bit_field #(
   .WIDTH                    (<%= width %>),
   .INITIAL_VALUE            (<%= initial_value %>),
-  .SW_WRITE_ENABLE_POLARITY (RGGEN_ACTIVE_LOW)
+  .SW_WRITE_ENABLE_POLARITY (<%= polarity %>)
 ) u_bit_field (
   .i_clk              (<%= clock %>),
   .i_rst_n            (<%= reset %>),
   .bit_field_if       (<%= bit_field_if %>),
-  .i_sw_write_enable  (<%= lock_signal %>),
+  .o_write_trigger    (),
+  .o_read_trigger     (),
+  .i_sw_write_enable  (<%= control_signal %>),
   .i_hw_write_enable  ('0),
   .i_hw_write_data    ('0),
   .i_hw_set           ('0),

data/lib/rggen/systemverilog/rtl/bit_field/type/rwe_rwl.rb

@@ -0,0 +1,34 @@
+# frozen_string_literal: true
+
+RgGen.define_list_item_feature(:bit_field, :type, [:rwe, :rwl]) do
+  sv_rtl do
+    build do
+      unless bit_field.reference?
+        input :control, {
+          name: "i_#{full_name}_#{enable_or_lock}", width: 1,
+          array_size: array_size, array_format: array_port_format
+        }
+      end
+      output :value_out, {
+        name: "o_#{full_name}", width: width,
+        array_size: array_size, array_format: array_port_format
+      }
+    end
+
+    main_code :bit_field, from_template: true
+
+    private
+
+    def enable_or_lock
+      { rwe: :enable, rwl: :lock }[bit_field.type]
+    end
+
+    def control_signal
+      reference_bit_field || control[loop_variables]
+    end
+
+    def polarity
+      { rwe: 'RGGEN_ACTIVE_HIGH', rwl: 'RGGEN_ACTIVE_LOW' }[bit_field.type]
+    end
+  end
+end

data/lib/rggen/systemverilog/rtl/bit_field/type/rws.erb

@@ -5,6 +5,8 @@ rggen_bit_field #(
   .i_clk              (<%= clock %>),
   .i_rst_n            (<%= reset %>),
   .bit_field_if       (<%= bit_field_if %>),
+  .o_write_trigger    (),
+  .o_read_trigger     (),
   .i_sw_write_enable  ('1),
   .i_hw_write_enable  (<%= set_signal %>),
   .i_hw_write_data    (<%= value_in[loop_variables] %>),

data/lib/rggen/systemverilog/rtl/bit_field/type/rws.rb

@@ -5,16 +5,16 @@ RgGen.define_list_item_feature(:bit_field, :type, :rws) do
     build do
       unless bit_field.reference?
         input :set, {
-          name: "i_#{full_name}_set", data_type: :logic, width: 1,
+          name: "i_#{full_name}_set", width: 1,
           array_size: array_size, array_format: array_port_format
         }
       end
       input :value_in, {
-        name: "i_#{full_name}", data_type: :logic, width: width,
+        name: "i_#{full_name}", width: width,
         array_size: array_size, array_format: array_port_format
       }
       output :value_out, {
-        name: "o_#{full_name}", data_type: :logic, width: width,
+        name: "o_#{full_name}", width: width,
         array_size: array_size, array_format: array_port_format
       }
     end

data/lib/rggen/systemverilog/rtl/bit_field/type/w0crs_w0src_w1crs_w1src_wcrs_wsrc.erb

@@ -7,6 +7,8 @@ rggen_bit_field #(
   .i_clk              (<%= clock %>),
   .i_rst_n            (<%= reset %>),
   .bit_field_if       (<%= bit_field_if %>),
+  .o_write_trigger    (),
+  .o_read_trigger     (),
   .i_sw_write_enable  ('1),
   .i_hw_write_enable  ('0),
   .i_hw_write_data    ('0),

data/lib/rggen/systemverilog/rtl/bit_field/type/w0crs_w0src_w1crs_w1src_wcrs_wsrc.rb

@@ -6,7 +6,7 @@ RgGen.define_list_item_feature(
   sv_rtl do
     build do
       output :value_out, {
-        name: "o_#{full_name}", data_type: :logic, width: width,
+        name: "o_#{full_name}", width: width,
         array_size: array_size, array_format: array_port_format
       }
     end

data/lib/rggen/systemverilog/rtl/bit_field/type/w0t_w1t.erb

@@ -6,6 +6,8 @@ rggen_bit_field #(
   .i_clk              (<%= clock %>),
   .i_rst_n            (<%= reset %>),
   .bit_field_if       (<%= bit_field_if %>),
+  .o_write_trigger    (),
+  .o_read_trigger     (),
   .i_sw_write_enable  ('1),
   .i_hw_write_enable  ('0),
   .i_hw_write_data    ('0),

data/lib/rggen/systemverilog/rtl/bit_field/type/w0t_w1t.rb

@@ -4,7 +4,7 @@ RgGen.define_list_item_feature(:bit_field, :type, [:w0t, :w1t]) do
   sv_rtl do
     build do
       output :value_out, {
-        name: "o_#{full_name}", data_type: :logic, width: width,
+        name: "o_#{full_name}", width: width,
         array_size: array_size, array_format: array_port_format
       }
     end

data/lib/rggen/systemverilog/rtl/bit_field/type/w0trg_w1trg.rb

@@ -4,7 +4,7 @@ RgGen.define_list_item_feature(:bit_field, :type, [:w0trg, :w1trg]) do
   sv_rtl do
     build do
       output :trigger, {
-        name: "o_#{full_name}_trigger", data_type: :logic, width: width,
+        name: "o_#{full_name}_trigger", width: width,
         array_size: array_size, array_format: array_port_format
       }
     end

data/lib/rggen/systemverilog/rtl/bit_field/type/{rwe.erb → wo_wo1_wotrg.erb}

@@ -1,12 +1,16 @@
 rggen_bit_field #(
-  .WIDTH                    (<%= width %>),
-  .INITIAL_VALUE            (<%= initial_value %>),
-  .SW_WRITE_ENABLE_POLARITY (RGGEN_ACTIVE_HIGH)
+  .WIDTH          (<%= width %>),
+  .INITIAL_VALUE  (<%= initial_value %>),
+  .SW_READ_ACTION (RGGEN_READ_NONE),
+  .SW_WRITE_ONCE  (<%= write_once %>),
+  .TRIGGER        (<%= trigger %>)
 ) u_bit_field (
   .i_clk              (<%= clock %>),
   .i_rst_n            (<%= reset %>),
   .bit_field_if       (<%= bit_field_if %>),
-  .i_sw_write_enable  (<%= enable_signal %>),
+  .o_write_trigger    (<%= write_trigger_signal %>),
+  .o_read_trigger     (),
+  .i_sw_write_enable  ('1),
   .i_hw_write_enable  ('0),
   .i_hw_write_data    ('0),
   .i_hw_set           ('0),

data/lib/rggen/systemverilog/rtl/bit_field/type/wo_wo1_wotrg.rb

@@ -0,0 +1,38 @@
+# frozen_string_literal: true
+
+RgGen.define_list_item_feature(:bit_field, :type, [:wo, :wo1, :wotrg]) do
+  sv_rtl do
+    build do
+      output :value_out, {
+        name: "o_#{full_name}", width: width,
+        array_size: array_size, array_format: array_port_format
+      }
+      if wotrg?
+        output :write_trigger, {
+          name: "o_#{full_name}_write_trigger", width: 1,
+          array_size: array_size, array_format: array_port_format
+        }
+      end
+    end
+
+    main_code :bit_field, from_template: true
+
+    private
+
+    def wotrg?
+      bit_field.type == :wotrg
+    end
+
+    def trigger
+      wotrg? && 1 || 0
+    end
+
+    def write_trigger_signal
+      wotrg? && write_trigger[loop_variables] || nil
+    end
+
+    def write_once
+      bit_field.type == :wo1 && 1 || 0
+    end
+  end
+end

data/lib/rggen/systemverilog/rtl/bit_field/type/wrc_wrs.erb

@@ -6,6 +6,8 @@ rggen_bit_field #(
   .i_clk              (<%= clock %>),
   .i_rst_n            (<%= reset %>),
   .bit_field_if       (<%= bit_field_if %>),
+  .o_write_trigger    (),
+  .o_read_trigger     (),
   .i_sw_write_enable  ('1),
   .i_hw_write_enable  ('0),
   .i_hw_write_data    ('0),

data/lib/rggen/systemverilog/rtl/bit_field/type/wrc_wrs.rb

@@ -4,7 +4,7 @@ RgGen.define_list_item_feature(:bit_field, :type, [:wrc, :wrs]) do
   sv_rtl do
     build do
       output :value_out, {
-        name: "o_#{full_name}", data_type: :logic, width: width,
+        name: "o_#{full_name}", width: width,
         array_size: array_size, array_format: array_port_format
       }
     end

data/lib/rggen/systemverilog/rtl/bit_field_index.rb

@@ -15,8 +15,7 @@ module RgGen
         end
 
         def local_index
-          index_name = local_index_name
-          index_name && create_identifier(index_name)
+          create_identifier(local_index_name)
         end
 
         def local_indices

data/lib/rggen/systemverilog/rtl/feature.rb

@@ -16,10 +16,12 @@ module RgGen
           InterfaceInstance.new(attributes, &block)
         end
 
-        def create_argument(direction, attributes, &block)
-          DataObject.new(
-            :argument, attributes.merge(direction: direction), &block
-          )
+        def create_port(direction, attributes, &block)
+          attributes =
+            { data_type: 'logic' }
+              .merge(attributes)
+              .merge(direction: direction)
+          DataObject.new(:argument, attributes, &block)
         end
 
         def create_if_port(_, attributes, &block)
@@ -34,8 +36,8 @@ module RgGen
 
         define_entity :logic, :create_variable, :variable, -> { component }
         define_entity :interface, :create_if_instance, :variable, -> { component }
-        define_entity :input, :create_argument, :port, -> { register_block }
-        define_entity :output, :create_argument, :port, -> { register_block }
+        define_entity :input, :create_port, :port, -> { register_block }
+        define_entity :output, :create_port, :port, -> { register_block }
         define_entity :interface_port, :create_if_port, :port, -> { register_block }
         define_entity :parameter, :create_parameter, :parameter, -> { register_block }
         define_entity :localparam, :create_parameter, :parameter, -> { component }

data/lib/rggen/systemverilog/rtl/partial_sum.rb

@@ -7,12 +7,11 @@ module RgGen
         private
 
         def partial_sums(operands)
-          sums =
-            operands
-              .chunk(&method(:integer?))
-              .flat_map(&method(:calc_partial_sum))
-              .reject { |value| integer?(value) && value.zero? }
-          sums.empty? && [0] || sums
+          operands
+            .chunk(&method(:integer?))
+            .flat_map(&method(:calc_partial_sum))
+            .reject { |value| integer?(value) && value.zero? }
+            .tap { |sums| sums.empty? && (sums << 0) }
         end
 
         def calc_partial_sum(kind_ans_values)

data/lib/rggen/systemverilog/rtl/register/type/external.rb

@@ -3,71 +3,14 @@
 RgGen.define_list_item_feature(:register, :type, :external) do
   sv_rtl do
     build do
-      if configuration.fold_sv_interface_port?
-        interface_port :bus_if, {
-          name: "#{register.name}_bus_if",
-          interface_type: 'rggen_bus_if',
-          modport: 'master'
-        }
-      else
-        output :valid, {
-          name: "o_#{register.name}_valid",
-          data_type: :logic, width: 1
-        }
-        output :access, {
-          name: "o_#{register.name}_access",
-          data_type: :logic, width: '$bits(rggen_access)'
-        }
-        output :address, {
-          name: "o_#{register.name}_address",
-          data_type: :logic, width: address_width
-        }
-        output :write_data, {
-          name: "o_#{register.name}_data",
-          data_type: :logic, width: bus_width
-        }
-        output :strobe, {
-          name: "o_#{register.name}_strobe",
-          data_type: :logic, width: byte_width
-        }
-        input :ready, {
-          name: "i_#{register.name}_ready",
-          data_type: :logic, width: 1
-        }
-        input :status, {
-          name: "i_#{register.name}_status",
-          data_type: :logic, width: 2
-        }
-        input :read_data, {
-          name: "i_#{register.name}_data",
-          data_type: :logic, width: bus_width
-        }
-        interface :bus_if, {
-          name: 'bus_if', interface_type: 'rggen_bus_if',
-          parameter_values: [address_width, bus_width],
-          variables: [
-            'valid', 'access', 'address', 'write_data', 'strobe',
-            'ready', 'status', 'read_data'
-          ]
-        }
-      end
+      interface_port :bus_if, {
+        name: "#{register.name}_bus_if",
+        interface_type: 'rggen_bus_if',
+        modport: 'master'
+      }
     end
 
     main_code :register, from_template: true
-    main_code :register do |code|
-      unless configuration.fold_sv_interface_port?
-        [
-          [valid, bus_if.valid],
-          [access, bus_if.access],
-          [address, bus_if.address],
-          [write_data, bus_if.write_data],
-          [strobe, bus_if.strobe],
-          [bus_if.ready, ready],
-          [bus_if.status, "rggen_status'(#{status})"],
-          [bus_if.read_data, read_data]
-        ].map { |lhs, rhs| code << assign(lhs, rhs) << nl }
-      end
-    end
 
     private
 

data/lib/rggen/systemverilog/rtl/register_block/protocol/apb.rb

@@ -21,68 +21,11 @@ RgGen.define_list_item_feature(:register_block, :protocol, :apb) do
 
   sv_rtl do
     build do
-      if configuration.fold_sv_interface_port?
-        interface_port :apb_if, {
-          name: 'apb_if', interface_type: 'rggen_apb_if', modport: 'slave'
-        }
-      else
-        input :psel, {
-          name: 'i_psel', data_type: :logic, width: 1
-        }
-        input :penable, {
-          name: 'i_penable', data_type: :logic, width: 1
-        }
-        input :paddr, {
-          name: 'i_paddr', data_type: :logic, width: address_width
-        }
-        input :pprot, {
-          name: 'i_pprot', data_type: :logic, width: 3
-        }
-        input :pwrite, {
-          name: 'i_pwrite', data_type: :logic, width: 1
-        }
-        input :pstrb, {
-          name: 'i_pstrb', data_type: :logic, width: byte_width
-        }
-        input :pwdata, {
-          name: 'i_pwdata', data_type: :logic, width: bus_width
-        }
-        output :pready, {
-          name: 'o_pready', data_type: :logic, width: 1
-        }
-        output :prdata, {
-          name: 'o_prdata', data_type: :logic, width: bus_width
-        }
-        output :pslverr, {
-          name: 'o_pslverr', data_type: :logic, width: 1
-        }
-        interface :apb_if, {
-          name: 'apb_if', interface_type: 'rggen_apb_if',
-          parameter_values: [address_width, bus_width],
-          variables: [
-            'psel', 'penable', 'paddr', 'pprot', 'pwrite', 'pstrb', 'pwdata',
-            'pready', 'prdata', 'pslverr'
-          ]
-        }
-      end
+      interface_port :apb_if, {
+        name: 'apb_if', interface_type: 'rggen_apb_if', modport: 'slave'
+      }
     end
 
     main_code :register_block, from_template: true
-    main_code :register_block do |code|
-      unless configuration.fold_sv_interface_port?
-        [
-          [apb_if.psel, psel],
-          [apb_if.penable, penable],
-          [apb_if.paddr, paddr],
-          [apb_if.pprot, pprot],
-          [apb_if.pwrite, pwrite],
-          [apb_if.pstrb, pstrb],
-          [apb_if.pwdata, pwdata],
-          [pready, apb_if.pready],
-          [prdata, apb_if.prdata],
-          [pslverr, apb_if.pslverr]
-        ].each { |lhs, rhs| code << assign(lhs, rhs) << nl }
-      end
-    end
   end
 end

data/lib/rggen/systemverilog/rtl/register_block/protocol/axi4lite.rb

@@ -19,132 +19,18 @@ RgGen.define_list_item_feature(:register_block, :protocol, :axi4lite) do
       parameter :write_first, {
         name: 'WRITE_FIRST', data_type: :bit, default: 1
       }
-      if configuration.fold_sv_interface_port?
-        interface_port :axi4lite_if, {
-          name: 'axi4lite_if',
-          interface_type: 'rggen_axi4lite_if', modport: 'slave'
-        }
-      else
-        input :awvalid, {
-          name: 'i_awvalid', data_type: :logic, width: 1
-        }
-        output :awready, {
-          name: 'o_awready', data_type: :logic, width: 1
-        }
-        input :awid, {
-          name: 'i_awid', data_type: :logic, width: id_port_width
-        }
-        input :awaddr, {
-          name: 'i_awaddr', data_type: :logic, width: address_width
-        }
-        input :awprot, {
-          name: 'i_awprot', data_type: :logic, width: 3
-        }
-        input :wvalid, {
-          name: 'i_wvalid', data_type: :logic, width: 1
-        }
-        output :wready, {
-          name: 'o_wready', data_type: :logic, width: 1
-        }
-        input :wdata, {
-          name: 'i_wdata', data_type: :logic, width: bus_width
-        }
-        input :wstrb, {
-          name: 'i_wstrb', data_type: :logic, width: byte_width
-        }
-        output :bvalid, {
-          name: 'o_bvalid', data_type: :logic, width: 1
-        }
-        output :bid, {
-          name: 'o_bid', data_type: :logic, width: id_port_width
-        }
-        input :bready, {
-          name: 'i_bready', data_type: :logic, width: 1
-        }
-        output :bresp, {
-          name: 'o_bresp', data_type: :logic, width: 2
-        }
-        input :arvalid, {
-          name: 'i_arvalid', data_type: :logic, width: 1
-        }
-        output :arready, {
-          name: 'o_arready', data_type: :logic, width: 1
-        }
-        input :arid, {
-          name: 'i_arid', data_type: :logic, width: id_port_width
-        }
-        input :araddr, {
-          name: 'i_araddr', data_type: :logic, width: address_width
-        }
-        input :arprot, {
-          name: 'i_arprot', data_type: :logic, width: 3
-        }
-        output :rvalid, {
-          name: 'o_rvalid', data_type: :logic, width: 1
-        }
-        input :rready, {
-          name: 'i_rready', data_type: :logic, width: 1
-        }
-        output :rid, {
-          name: 'o_rid', data_type: :logic, width: id_port_width
-        }
-        output :rdata, {
-          name: 'o_rdata', data_type: :logic, width: bus_width
-        }
-        output :rresp, {
-          name: 'o_rresp', data_type: :logic, width: 2
-        }
-        interface :axi4lite_if, {
-          name: 'axi4lite_if', interface_type: 'rggen_axi4lite_if',
-          parameter_values: [id_width, address_width, bus_width],
-          variables: [
-            'awvalid', 'awready', 'awid', 'awaddr', 'awprot',
-            'wvalid', 'wready', 'wdata', 'wstrb',
-            'bvalid', 'bready', 'bid', 'bresp',
-            'arvalid', 'arready', 'arid', 'araddr', 'arprot',
-            'rvalid', 'rready', 'rid', 'rdata', 'rresp'
-          ]
-        }
-      end
+      interface_port :axi4lite_if, {
+        name: 'axi4lite_if',
+        interface_type: 'rggen_axi4lite_if', modport: 'slave'
+      }
     end
 
     main_code :register_block, from_template: true
-    main_code :register_block do |code|
-      configuration.fold_sv_interface_port? || assign_axi4lite_signals(code)
-    end
 
     private
 
     def id_port_width
       "((#{id_width}>0)?#{id_width}:1)"
     end
-
-    def assign_axi4lite_signals(code)
-      [
-        [axi4lite_if.awvalid, awvalid],
-        [awready, axi4lite_if.awready],
-        [axi4lite_if.awid, awid],
-        [axi4lite_if.awaddr, awaddr],
-        [axi4lite_if.awprot, awprot],
-        [axi4lite_if.wvalid, wvalid],
-        [wready, axi4lite_if.wready],
-        [axi4lite_if.wdata, wdata],
-        [axi4lite_if.wstrb, wstrb],
-        [bvalid, axi4lite_if.bvalid],
-        [axi4lite_if.bready, bready],
-        [bid, axi4lite_if.bid],
-        [bresp, axi4lite_if.bresp],
-        [axi4lite_if.arvalid, arvalid],
-        [arready, axi4lite_if.arready],
-        [axi4lite_if.arid, arid],
-        [axi4lite_if.araddr, araddr],
-        [axi4lite_if.arprot, arprot],
-        [rvalid, axi4lite_if.rvalid],
-        [axi4lite_if.rready, rready],
-        [rid, axi4lite_if.rid],
-        [rdata, axi4lite_if.rdata],
-        [rresp, axi4lite_if.rresp]
-      ].each { |lhs, rhs| code << assign(lhs, rhs) << nl }
-    end
   end
 end

data/lib/rggen/systemverilog/rtl/register_block/protocol/wishbone.erb

@@ -0,0 +1,17 @@
+rggen_wishbone_adapter #(
+  .ADDRESS_WIDTH        (<%= address_width %>),
+  .LOCAL_ADDRESS_WIDTH  (<%= local_address_width %>),
+  .BUS_WIDTH            (<%= bus_width %>),
+  .REGISTERS            (<%= total_registers %>),
+  .PRE_DECODE           (<%= pre_decode %>),
+  .BASE_ADDRESS         (<%= base_address %>),
+  .BYTE_SIZE            (<%= byte_size %>),
+  .ERROR_STATUS         (<%= error_status %>),
+  .DEFAULT_READ_DATA    (<%= default_read_data %>),
+  .USE_STALL            (<%= use_stall %>)
+) u_adapter (
+  .i_clk        (<%= clock %>),
+  .i_rst_n      (<%= reset %>),
+  .wishbone_if  (<%= wishbone_if %>),
+  .register_if  (<%= register_if %>)
+);