rggen-systemverilog 0.21.0 → 0.24.0

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Files changed (50) hide show
  1. checksums.yaml +4 -4
  2. data/LICENSE +1 -1
  3. data/README.md +2 -2
  4. data/lib/rggen/systemverilog/common.rb +0 -22
  5. data/lib/rggen/systemverilog/common/feature.rb +2 -2
  6. data/lib/rggen/systemverilog/common/utility.rb +4 -0
  7. data/lib/rggen/systemverilog/common/utility/identifier.rb +19 -15
  8. data/lib/rggen/systemverilog/ral.rb +20 -26
  9. data/lib/rggen/systemverilog/ral/bit_field/type.rb +1 -1
  10. data/lib/rggen/systemverilog/ral/setup.rb +1 -1
  11. data/lib/rggen/systemverilog/rtl.rb +39 -41
  12. data/lib/rggen/systemverilog/rtl/bit_field/sv_rtl_top.rb +10 -46
  13. data/lib/rggen/systemverilog/rtl/bit_field/type.rb +1 -2
  14. data/lib/rggen/systemverilog/rtl/bit_field/type/rc_w0c_w1c_wc_woc.erb +19 -0
  15. data/lib/rggen/systemverilog/rtl/bit_field/type/{rc_w0c_w1c.rb → rc_w0c_w1c_wc_woc.rb} +22 -11
  16. data/lib/rggen/systemverilog/rtl/bit_field/type/reserved.erb +17 -2
  17. data/lib/rggen/systemverilog/rtl/bit_field/type/ro.erb +15 -4
  18. data/lib/rggen/systemverilog/rtl/bit_field/type/rof.erb +15 -4
  19. data/lib/rggen/systemverilog/rtl/bit_field/type/rs_w0s_w1s_ws_wos.erb +19 -0
  20. data/lib/rggen/systemverilog/rtl/bit_field/type/{rs_w0s_w1s.rb → rs_w0s_w1s_ws_wos.rb} +21 -9
  21. data/lib/rggen/systemverilog/rtl/bit_field/type/rw_w1_wo_wo1.erb +15 -7
  22. data/lib/rggen/systemverilog/rtl/bit_field/type/rw_w1_wo_wo1.rb +2 -2
  23. data/lib/rggen/systemverilog/rtl/bit_field/type/rwc.erb +15 -7
  24. data/lib/rggen/systemverilog/rtl/bit_field/type/rwe.erb +16 -8
  25. data/lib/rggen/systemverilog/rtl/bit_field/type/rwl.erb +16 -8
  26. data/lib/rggen/systemverilog/rtl/bit_field/type/rws.erb +13 -7
  27. data/lib/rggen/systemverilog/rtl/bit_field/type/w0crs_w0src_w1crs_w1src_wcrs_wsrc.erb +19 -0
  28. data/lib/rggen/systemverilog/rtl/bit_field/type/w0crs_w0src_w1crs_w1src_wcrs_wsrc.rb +37 -0
  29. data/lib/rggen/systemverilog/rtl/bit_field/type/w0t_w1t.erb +18 -0
  30. data/lib/rggen/systemverilog/rtl/bit_field/type/{w0src_w1src.rb → w0t_w1t.rb} +6 -4
  31. data/lib/rggen/systemverilog/rtl/bit_field/type/wrc_wrs.erb +18 -0
  32. data/lib/rggen/systemverilog/rtl/bit_field/type/{w0crs_w1crs.rb → wrc_wrs.rb} +6 -4
  33. data/lib/rggen/systemverilog/rtl/bit_field_index.rb +53 -0
  34. data/lib/rggen/systemverilog/rtl/indirect_index.rb +35 -0
  35. data/lib/rggen/systemverilog/rtl/register/type.rb +1 -56
  36. data/lib/rggen/systemverilog/rtl/register/type/external.rb +0 -4
  37. data/lib/rggen/systemverilog/rtl/register/type/indirect.rb +2 -26
  38. data/lib/rggen/systemverilog/rtl/register_block/protocol.rb +14 -8
  39. data/lib/rggen/systemverilog/rtl/register_block/protocol/axi4lite.erb +1 -0
  40. data/lib/rggen/systemverilog/rtl/register_block/protocol/axi4lite.rb +55 -28
  41. data/lib/rggen/systemverilog/rtl/register_block/sv_rtl_top.rb +1 -1
  42. data/lib/rggen/systemverilog/rtl/register_index.rb +4 -4
  43. data/lib/rggen/systemverilog/rtl/register_type.rb +68 -0
  44. data/lib/rggen/systemverilog/rtl/setup.rb +1 -1
  45. data/lib/rggen/systemverilog/version.rb +1 -1
  46. metadata +17 -26
  47. data/lib/rggen/systemverilog/rtl/bit_field/type/rc_w0c_w1c.erb +0 -15
  48. data/lib/rggen/systemverilog/rtl/bit_field/type/rs_w0s_w1s.erb +0 -13
  49. data/lib/rggen/systemverilog/rtl/bit_field/type/w0crs_w1crs.erb +0 -10
  50. data/lib/rggen/systemverilog/rtl/bit_field/type/w0src_w1src.erb +0 -10
@@ -0,0 +1,68 @@
1
+ # frozen_string_literal: true
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+
3
+ module RgGen
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+ module SystemVerilog
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+ module RTL
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+ module RegisterType
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+ include PartialSum
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+
9
+ private
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+
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+ def readable
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+ register.readable? && 1 || 0
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+ end
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+
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+ def writable
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+ register.writable? && 1 || 0
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+ end
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+
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+ def bus_width
20
+ configuration.bus_width
21
+ end
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+
23
+ def address_width
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+ register_block.local_address_width
25
+ end
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+
27
+ def offset_address
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+ offsets = [*register_files, register].flat_map(&method(:collect_offsets))
29
+ offsets = partial_sums(offsets)
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+ format_offsets(offsets)
31
+ end
32
+
33
+ def collect_offsets(component)
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+ if component.register_file? && component.array?
35
+ [component.offset_address, byte_offset(component)]
36
+ else
37
+ component.offset_address
38
+ end
39
+ end
40
+
41
+ def byte_offset(component)
42
+ "#{component.byte_size(false)}*(#{component.local_index})"
43
+ end
44
+
45
+ def format_offsets(offsets)
46
+ offsets.map(&method(:format_offset)).join('+')
47
+ end
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+
49
+ def format_offset(offset)
50
+ offset.is_a?(Integer) ? hex(offset, address_width) : offset
51
+ end
52
+
53
+ def width
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+ register.width
55
+ end
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+
57
+ def valid_bits
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+ bits = register.bit_fields.map(&:bit_map).inject(:|)
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+ hex(bits, register.width)
60
+ end
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+
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+ def register_index
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+ register.local_index || 0
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+ end
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+ end
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+ end
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+ end
68
+ end
@@ -2,7 +2,7 @@
2
2
 
3
3
  require 'rggen/systemverilog/rtl'
4
4
 
5
- RgGen.setup :'rggen-sv-rtl', RgGen::SystemVerilog::RTL do |builder|
5
+ RgGen.register_plugin RgGen::SystemVerilog::RTL do |builder|
6
6
  builder.enable :global, [
7
7
  :array_port_format, :fold_sv_interface_port
8
8
  ]
@@ -2,6 +2,6 @@
2
2
 
3
3
  module RgGen
4
4
  module SystemVerilog
5
- VERSION = '0.21.0'
5
+ VERSION = '0.24.0'
6
6
  end
7
7
  end
metadata CHANGED
@@ -1,29 +1,15 @@
1
1
  --- !ruby/object:Gem::Specification
2
2
  name: rggen-systemverilog
3
3
  version: !ruby/object:Gem::Version
4
- version: 0.21.0
4
+ version: 0.24.0
5
5
  platform: ruby
6
6
  authors:
7
7
  - Taichi Ishitani
8
8
  autorequire:
9
9
  bindir: bin
10
10
  cert_chain: []
11
- date: 2020-07-22 00:00:00.000000000 Z
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+ date: 2021-01-20 00:00:00.000000000 Z
12
12
  dependencies:
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- - !ruby/object:Gem::Dependency
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- name: docile
15
- requirement: !ruby/object:Gem::Requirement
16
- requirements:
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- - - ">="
18
- - !ruby/object:Gem::Version
19
- version: 1.1.5
20
- type: :runtime
21
- prerelease: false
22
- version_requirements: !ruby/object:Gem::Requirement
23
- requirements:
24
- - - ">="
25
- - !ruby/object:Gem::Version
26
- version: 1.1.5
27
13
  - !ruby/object:Gem::Dependency
28
14
  name: facets
29
15
  requirement: !ruby/object:Gem::Requirement
@@ -103,16 +89,16 @@ files:
103
89
  - lib/rggen/systemverilog/rtl.rb
104
90
  - lib/rggen/systemverilog/rtl/bit_field/sv_rtl_top.rb
105
91
  - lib/rggen/systemverilog/rtl/bit_field/type.rb
106
- - lib/rggen/systemverilog/rtl/bit_field/type/rc_w0c_w1c.erb
107
- - lib/rggen/systemverilog/rtl/bit_field/type/rc_w0c_w1c.rb
92
+ - lib/rggen/systemverilog/rtl/bit_field/type/rc_w0c_w1c_wc_woc.erb
93
+ - lib/rggen/systemverilog/rtl/bit_field/type/rc_w0c_w1c_wc_woc.rb
108
94
  - lib/rggen/systemverilog/rtl/bit_field/type/reserved.erb
109
95
  - lib/rggen/systemverilog/rtl/bit_field/type/reserved.rb
110
96
  - lib/rggen/systemverilog/rtl/bit_field/type/ro.erb
111
97
  - lib/rggen/systemverilog/rtl/bit_field/type/ro.rb
112
98
  - lib/rggen/systemverilog/rtl/bit_field/type/rof.erb
113
99
  - lib/rggen/systemverilog/rtl/bit_field/type/rof.rb
114
- - lib/rggen/systemverilog/rtl/bit_field/type/rs_w0s_w1s.erb
115
- - lib/rggen/systemverilog/rtl/bit_field/type/rs_w0s_w1s.rb
100
+ - lib/rggen/systemverilog/rtl/bit_field/type/rs_w0s_w1s_ws_wos.erb
101
+ - lib/rggen/systemverilog/rtl/bit_field/type/rs_w0s_w1s_ws_wos.rb
116
102
  - lib/rggen/systemverilog/rtl/bit_field/type/rw_w1_wo_wo1.erb
117
103
  - lib/rggen/systemverilog/rtl/bit_field/type/rw_w1_wo_wo1.rb
118
104
  - lib/rggen/systemverilog/rtl/bit_field/type/rwc.erb
@@ -123,15 +109,19 @@ files:
123
109
  - lib/rggen/systemverilog/rtl/bit_field/type/rwl.rb
124
110
  - lib/rggen/systemverilog/rtl/bit_field/type/rws.erb
125
111
  - lib/rggen/systemverilog/rtl/bit_field/type/rws.rb
126
- - lib/rggen/systemverilog/rtl/bit_field/type/w0crs_w1crs.erb
127
- - lib/rggen/systemverilog/rtl/bit_field/type/w0crs_w1crs.rb
128
- - lib/rggen/systemverilog/rtl/bit_field/type/w0src_w1src.erb
129
- - lib/rggen/systemverilog/rtl/bit_field/type/w0src_w1src.rb
112
+ - lib/rggen/systemverilog/rtl/bit_field/type/w0crs_w0src_w1crs_w1src_wcrs_wsrc.erb
113
+ - lib/rggen/systemverilog/rtl/bit_field/type/w0crs_w0src_w1crs_w1src_wcrs_wsrc.rb
114
+ - lib/rggen/systemverilog/rtl/bit_field/type/w0t_w1t.erb
115
+ - lib/rggen/systemverilog/rtl/bit_field/type/w0t_w1t.rb
130
116
  - lib/rggen/systemverilog/rtl/bit_field/type/w0trg_w1trg.erb
131
117
  - lib/rggen/systemverilog/rtl/bit_field/type/w0trg_w1trg.rb
118
+ - lib/rggen/systemverilog/rtl/bit_field/type/wrc_wrs.erb
119
+ - lib/rggen/systemverilog/rtl/bit_field/type/wrc_wrs.rb
120
+ - lib/rggen/systemverilog/rtl/bit_field_index.rb
132
121
  - lib/rggen/systemverilog/rtl/feature.rb
133
122
  - lib/rggen/systemverilog/rtl/global/array_port_format.rb
134
123
  - lib/rggen/systemverilog/rtl/global/fold_sv_interface_port.rb
124
+ - lib/rggen/systemverilog/rtl/indirect_index.rb
135
125
  - lib/rggen/systemverilog/rtl/partial_sum.rb
136
126
  - lib/rggen/systemverilog/rtl/register/sv_rtl_top.rb
137
127
  - lib/rggen/systemverilog/rtl/register/type.rb
@@ -149,6 +139,7 @@ files:
149
139
  - lib/rggen/systemverilog/rtl/register_block/sv_rtl_top.rb
150
140
  - lib/rggen/systemverilog/rtl/register_file/sv_rtl_top.rb
151
141
  - lib/rggen/systemverilog/rtl/register_index.rb
142
+ - lib/rggen/systemverilog/rtl/register_type.rb
152
143
  - lib/rggen/systemverilog/rtl/setup.rb
153
144
  - lib/rggen/systemverilog/version.rb
154
145
  homepage: https://github.com/rggen/rggen-systemverilog
@@ -174,8 +165,8 @@ required_rubygems_version: !ruby/object:Gem::Requirement
174
165
  - !ruby/object:Gem::Version
175
166
  version: '0'
176
167
  requirements: []
177
- rubygems_version: 3.1.2
168
+ rubygems_version: 3.2.3
178
169
  signing_key:
179
170
  specification_version: 4
180
- summary: rggen-systemverilog-0.21.0
171
+ summary: rggen-systemverilog-0.24.0
181
172
  test_files: []
@@ -1,15 +0,0 @@
1
- <%= module_name %> #(
2
- <% if [:w0c, :w1c].include?(bit_field.type) %>
3
- .CLEAR_VALUE (<%= clear_value %>),
4
- <% end %>
5
- .WIDTH (<%= width %>),
6
- .INITIAL_VALUE (<%= initial_value %>)
7
- ) u_bit_field (
8
- .i_clk (<%= clock %>),
9
- .i_rst_n (<%= reset%>),
10
- .bit_field_if (<%= bit_field_if %>),
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- .i_set (<%= set[loop_variables] %>),
12
- .i_mask (<%= mask %>),
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- .o_value (<%= value_out[loop_variables] %>),
14
- .o_value_unmasked (<%= value_out_unmasked %>)
15
- );
@@ -1,13 +0,0 @@
1
- <%= module_name %> #(
2
- <% if [:w0s, :w1s].include?(bit_field.type) %>
3
- .SET_VALUE (<%= set_value %>),
4
- <% end %>
5
- .WIDTH (<%= width %>),
6
- .INITIAL_VALUE (<%= initial_value %>)
7
- ) u_bit_field (
8
- .i_clk (<%= clock %>),
9
- .i_rst_n (<%= reset %>),
10
- .bit_field_if (<%= bit_field_if %>),
11
- .i_clear (<%= clear[loop_variables] %>),
12
- .o_value (<%= value_out[loop_variables] %>)
13
- );
@@ -1,10 +0,0 @@
1
- rggen_bit_field_w01crs #(
2
- .CLEAR_VALUE (<%= clear_value %>),
3
- .WIDTH (<%= width %>),
4
- .INITIAL_VALUE (<%= initial_value %>)
5
- ) u_bit_field (
6
- .i_clk (<%= clock %>),
7
- .i_rst_n (<%= reset %>),
8
- .bit_field_if (<%= bit_field_if %>),
9
- .o_value (<%= value_out[loop_variables] %>)
10
- );
@@ -1,10 +0,0 @@
1
- rggen_bit_field_w01src #(
2
- .SET_VALUE (<%= set_value %>),
3
- .WIDTH (<%= width %>),
4
- .INITIAL_VALUE (<%= initial_value %>)
5
- ) u_bit_field (
6
- .i_clk (<%= clock %>),
7
- .i_rst_n (<%= reset %>),
8
- .bit_field_if (<%= bit_field_if %>),
9
- .o_value (<%= value_out[loop_variables] %>)
10
- );