rggen-systemverilog 0.21.0 → 0.24.0

data/lib/rggen/systemverilog/rtl/register_type.rb

@@ -0,0 +1,68 @@
+# frozen_string_literal: true
+
+module RgGen
+  module SystemVerilog
+    module RTL
+      module RegisterType
+        include PartialSum
+
+        private
+
+        def readable
+          register.readable? && 1 || 0
+        end
+
+        def writable
+          register.writable? && 1 || 0
+        end
+
+        def bus_width
+          configuration.bus_width
+        end
+
+        def address_width
+          register_block.local_address_width
+        end
+
+        def offset_address
+          offsets = [*register_files, register].flat_map(&method(:collect_offsets))
+          offsets = partial_sums(offsets)
+          format_offsets(offsets)
+        end
+
+        def collect_offsets(component)
+          if component.register_file? && component.array?
+            [component.offset_address, byte_offset(component)]
+          else
+            component.offset_address
+          end
+        end
+
+        def byte_offset(component)
+          "#{component.byte_size(false)}*(#{component.local_index})"
+        end
+
+        def format_offsets(offsets)
+          offsets.map(&method(:format_offset)).join('+')
+        end
+
+        def format_offset(offset)
+          offset.is_a?(Integer) ? hex(offset, address_width) : offset
+        end
+
+        def width
+          register.width
+        end
+
+        def valid_bits
+          bits = register.bit_fields.map(&:bit_map).inject(:|)
+          hex(bits, register.width)
+        end
+
+        def register_index
+          register.local_index || 0
+        end
+      end
+    end
+  end
+end

data/lib/rggen/systemverilog/rtl/setup.rb

@@ -2,7 +2,7 @@
 
 require 'rggen/systemverilog/rtl'
 
-RgGen.setup :'rggen-sv-rtl', RgGen::SystemVerilog::RTL do |builder|
+RgGen.register_plugin RgGen::SystemVerilog::RTL do |builder|
   builder.enable :global, [
     :array_port_format, :fold_sv_interface_port
   ]

data/lib/rggen/systemverilog/version.rb

@@ -2,6 +2,6 @@
 
 module RgGen
   module SystemVerilog
-    VERSION = '0.21.0'
+    VERSION = '0.24.0'
   end
 end

metadata

@@ -1,29 +1,15 @@
 --- !ruby/object:Gem::Specification
 name: rggen-systemverilog
 version: !ruby/object:Gem::Version
-  version: 0.21.0
+  version: 0.24.0
 platform: ruby
 authors:
 - Taichi Ishitani
 autorequire: 
 bindir: bin
 cert_chain: []
-date: 2020-07-22 00:00:00.000000000 Z
+date: 2021-01-20 00:00:00.000000000 Z
 dependencies:
-- !ruby/object:Gem::Dependency
-  name: docile
-  requirement: !ruby/object:Gem::Requirement
-    requirements:
-    - - ">="
-      - !ruby/object:Gem::Version
-        version: 1.1.5
-  type: :runtime
-  prerelease: false
-  version_requirements: !ruby/object:Gem::Requirement
-    requirements:
-    - - ">="
-      - !ruby/object:Gem::Version
-        version: 1.1.5
 - !ruby/object:Gem::Dependency
   name: facets
   requirement: !ruby/object:Gem::Requirement
@@ -103,16 +89,16 @@ files:
 - lib/rggen/systemverilog/rtl.rb
 - lib/rggen/systemverilog/rtl/bit_field/sv_rtl_top.rb
 - lib/rggen/systemverilog/rtl/bit_field/type.rb
-- lib/rggen/systemverilog/rtl/bit_field/type/rc_w0c_w1c.erb
-- lib/rggen/systemverilog/rtl/bit_field/type/rc_w0c_w1c.rb
+- lib/rggen/systemverilog/rtl/bit_field/type/rc_w0c_w1c_wc_woc.erb
+- lib/rggen/systemverilog/rtl/bit_field/type/rc_w0c_w1c_wc_woc.rb
 - lib/rggen/systemverilog/rtl/bit_field/type/reserved.erb
 - lib/rggen/systemverilog/rtl/bit_field/type/reserved.rb
 - lib/rggen/systemverilog/rtl/bit_field/type/ro.erb
 - lib/rggen/systemverilog/rtl/bit_field/type/ro.rb
 - lib/rggen/systemverilog/rtl/bit_field/type/rof.erb
 - lib/rggen/systemverilog/rtl/bit_field/type/rof.rb
-- lib/rggen/systemverilog/rtl/bit_field/type/rs_w0s_w1s.erb
-- lib/rggen/systemverilog/rtl/bit_field/type/rs_w0s_w1s.rb
+- lib/rggen/systemverilog/rtl/bit_field/type/rs_w0s_w1s_ws_wos.erb
+- lib/rggen/systemverilog/rtl/bit_field/type/rs_w0s_w1s_ws_wos.rb
 - lib/rggen/systemverilog/rtl/bit_field/type/rw_w1_wo_wo1.erb
 - lib/rggen/systemverilog/rtl/bit_field/type/rw_w1_wo_wo1.rb
 - lib/rggen/systemverilog/rtl/bit_field/type/rwc.erb
@@ -123,15 +109,19 @@ files:
 - lib/rggen/systemverilog/rtl/bit_field/type/rwl.rb
 - lib/rggen/systemverilog/rtl/bit_field/type/rws.erb
 - lib/rggen/systemverilog/rtl/bit_field/type/rws.rb
-- lib/rggen/systemverilog/rtl/bit_field/type/w0crs_w1crs.erb
-- lib/rggen/systemverilog/rtl/bit_field/type/w0crs_w1crs.rb
-- lib/rggen/systemverilog/rtl/bit_field/type/w0src_w1src.erb
-- lib/rggen/systemverilog/rtl/bit_field/type/w0src_w1src.rb
+- lib/rggen/systemverilog/rtl/bit_field/type/w0crs_w0src_w1crs_w1src_wcrs_wsrc.erb
+- lib/rggen/systemverilog/rtl/bit_field/type/w0crs_w0src_w1crs_w1src_wcrs_wsrc.rb
+- lib/rggen/systemverilog/rtl/bit_field/type/w0t_w1t.erb
+- lib/rggen/systemverilog/rtl/bit_field/type/w0t_w1t.rb
 - lib/rggen/systemverilog/rtl/bit_field/type/w0trg_w1trg.erb
 - lib/rggen/systemverilog/rtl/bit_field/type/w0trg_w1trg.rb
+- lib/rggen/systemverilog/rtl/bit_field/type/wrc_wrs.erb
+- lib/rggen/systemverilog/rtl/bit_field/type/wrc_wrs.rb
+- lib/rggen/systemverilog/rtl/bit_field_index.rb
 - lib/rggen/systemverilog/rtl/feature.rb
 - lib/rggen/systemverilog/rtl/global/array_port_format.rb
 - lib/rggen/systemverilog/rtl/global/fold_sv_interface_port.rb
+- lib/rggen/systemverilog/rtl/indirect_index.rb
 - lib/rggen/systemverilog/rtl/partial_sum.rb
 - lib/rggen/systemverilog/rtl/register/sv_rtl_top.rb
 - lib/rggen/systemverilog/rtl/register/type.rb
@@ -149,6 +139,7 @@ files:
 - lib/rggen/systemverilog/rtl/register_block/sv_rtl_top.rb
 - lib/rggen/systemverilog/rtl/register_file/sv_rtl_top.rb
 - lib/rggen/systemverilog/rtl/register_index.rb
+- lib/rggen/systemverilog/rtl/register_type.rb
 - lib/rggen/systemverilog/rtl/setup.rb
 - lib/rggen/systemverilog/version.rb
 homepage: https://github.com/rggen/rggen-systemverilog
@@ -174,8 +165,8 @@ required_rubygems_version: !ruby/object:Gem::Requirement
     - !ruby/object:Gem::Version
       version: '0'
 requirements: []
-rubygems_version: 3.1.2
+rubygems_version: 3.2.3
 signing_key: 
 specification_version: 4
-summary: rggen-systemverilog-0.21.0
+summary: rggen-systemverilog-0.24.0
 test_files: []

data/lib/rggen/systemverilog/rtl/bit_field/type/rc_w0c_w1c.erb

@@ -1,15 +0,0 @@
-<%= module_name %> #(
-<% if [:w0c, :w1c].include?(bit_field.type) %>
-  .CLEAR_VALUE    (<%= clear_value %>),
-<% end %>
-  .WIDTH          (<%= width %>),
-  .INITIAL_VALUE  (<%= initial_value %>)
-) u_bit_field (
-  .i_clk            (<%= clock %>),
-  .i_rst_n          (<%= reset%>),
-  .bit_field_if     (<%= bit_field_if %>),
-  .i_set            (<%= set[loop_variables] %>),
-  .i_mask           (<%= mask %>),
-  .o_value          (<%= value_out[loop_variables] %>),
-  .o_value_unmasked (<%= value_out_unmasked %>)
-);

data/lib/rggen/systemverilog/rtl/bit_field/type/rs_w0s_w1s.erb

@@ -1,13 +0,0 @@
-<%= module_name %> #(
-<% if [:w0s, :w1s].include?(bit_field.type) %>
-  .SET_VALUE      (<%= set_value %>),
-<% end %>
-  .WIDTH          (<%= width %>),
-  .INITIAL_VALUE  (<%= initial_value %>)
-) u_bit_field (
-  .i_clk        (<%= clock %>),
-  .i_rst_n      (<%= reset %>),
-  .bit_field_if (<%= bit_field_if %>),
-  .i_clear      (<%= clear[loop_variables] %>),
-  .o_value      (<%= value_out[loop_variables] %>)
-);

data/lib/rggen/systemverilog/rtl/bit_field/type/w0crs_w1crs.erb

@@ -1,10 +0,0 @@
-rggen_bit_field_w01crs #(
-  .CLEAR_VALUE    (<%= clear_value %>),
-  .WIDTH          (<%= width %>),
-  .INITIAL_VALUE  (<%= initial_value %>)
-) u_bit_field (
-  .i_clk        (<%= clock %>),
-  .i_rst_n      (<%= reset %>),
-  .bit_field_if (<%= bit_field_if %>),
-  .o_value      (<%= value_out[loop_variables] %>)
-);

data/lib/rggen/systemverilog/rtl/bit_field/type/w0src_w1src.erb

@@ -1,10 +0,0 @@
-rggen_bit_field_w01src #(
-  .SET_VALUE      (<%= set_value %>),
-  .WIDTH          (<%= width %>),
-  .INITIAL_VALUE  (<%= initial_value %>)
-) u_bit_field (
-  .i_clk        (<%= clock %>),
-  .i_rst_n      (<%= reset %>),
-  .bit_field_if (<%= bit_field_if %>),
-  .o_value      (<%= value_out[loop_variables] %>)
-);