rggen-systemverilog 0.21.0 → 0.24.0

checksums.yaml

@@ -1,7 +1,7 @@
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data/LICENSE

@@ -1,6 +1,6 @@
 The MIT License (MIT)
 
-Copyright (c) 2019-2020 Taichi Ishitani
+Copyright (c) 2019-2021 Taichi Ishitani
 
 Permission is hereby granted, free of charge, to any person obtaining a copy
 of this software and associated documentation files (the "Software"), to deal

data/README.md

@@ -7,7 +7,7 @@
 
 # RgGen::SystemVerilog
 
-RgGen::SystemVerilog privides SystemVerilog RTL generator and UVM RAL model generator for RgGen.
+RgGen::SystemVerilog provides SystemVerilog RTL and UVM register model (UVM RAL) generators for RgGen.
 
 ## Installation
 
@@ -34,7 +34,7 @@ Feedbacks, bug reports, questions and etc. are wellcome! You can post them by us
 
 ## Copyright & License
 
-Copyright © 2019-2020 Taichi Ishitani. RgGen::SystemVerilog is licensed under the [MIT License](https://opensource.org/licenses/MIT), see [LICENSE](LICENSE) for futher details.
+Copyright © 2019-2021 Taichi Ishitani. RgGen::SystemVerilog is licensed under the [MIT License](https://opensource.org/licenses/MIT), see [LICENSE](LICENSE) for futher details.
 
 ## Code of Conduct
 

data/lib/rggen/systemverilog/common.rb

@@ -1,6 +1,5 @@
 # frozen_string_literal: true
 
-require 'docile'
 require 'facets/kernel/attr_singleton'
 
 require_relative 'version'
@@ -21,24 +20,3 @@ require_relative 'common/utility'
 require_relative 'common/component'
 require_relative 'common/feature'
 require_relative 'common/factories'
-
-module RgGen
-  module SystemVerilog
-    module Common
-      def self.register_component(builder, name, feature_class)
-        builder.output_component_registry(name) do
-          register_component [
-            :root, :register_block, :register_file, :register, :bit_field
-          ] do |category|
-            component Component, ComponentFactory
-            feature feature_class, FeatureFactory if category != :root
-          end
-        end
-      end
-
-      def self.load_features(features, root)
-        features.each { |feature| require File.join(root, feature) }
-      end
-    end
-  end
-end

data/lib/rggen/systemverilog/common/feature.rb

@@ -8,7 +8,7 @@ module RgGen
         template_engine Core::OutputBase::ERBEngine
 
         EntityContext =
-          Struct.new(:entity_type, :method, :declaration_type, :default_layer)
+          Struct.new(:entity_type, :method_name, :declaration_type, :default_layer)
 
         class << self
           private
@@ -58,7 +58,7 @@ module RgGen
 
         def create_entity(context, name, attributes, &block)
           merged_attributes = { name: name }.merge(Hash(attributes))
-          __send__(context.method, context.entity_type, merged_attributes, &block)
+          __send__(context.method_name, context.entity_type, merged_attributes, &block)
         end
 
         def add_entity(context, entity, name, layer)

data/lib/rggen/systemverilog/common/utility.rb

@@ -45,6 +45,10 @@ module RgGen
           end
         end
 
+        def all_bits_1
+          "'1"
+        end
+
         def all_bits_0
           "'0"
         end

data/lib/rggen/systemverilog/common/utility/identifier.rb

@@ -35,9 +35,9 @@ module RgGen
             @name.to_s
           end
 
-          def [](array_index_or_lsb, width = nil)
+          def [](array_index_or_lsb, lsb_or_width = nil, width = nil)
             if array_index_or_lsb
-              __create_new_identifier__(array_index_or_lsb, width)
+              __create_new_identifier__(array_index_or_lsb, lsb_or_width, width)
             else
               self
             end
@@ -45,35 +45,38 @@ module RgGen
 
           private
 
-          def __create_new_identifier__(array_index_or_lsb, width)
-            select = __create_select__(array_index_or_lsb, width)
+          def __create_new_identifier__(array_index_or_lsb, lsb_or_width, width)
+            select = __create_select__(array_index_or_lsb, lsb_or_width, width)
             Identifier.new("#{@name}#{select}") do |identifier|
               identifier.__sub_identifiers__(@sub_identifiers)
             end
           end
 
-          def __create_select__(array_index_or_lsb, width)
+          def __create_select__(array_index_or_lsb, lsb_or_width, width)
             if array_index_or_lsb.is_a?(::Array)
-              __array_select__(array_index_or_lsb)
-            elsif width
-              "[#{array_index_or_lsb}+:#{width}]"
+              __array_select__(array_index_or_lsb, lsb_or_width, width)
+            elsif lsb_or_width
+              "[#{array_index_or_lsb}+:#{lsb_or_width}]"
             else
               "[#{array_index_or_lsb}]"
             end
           end
 
-          def __array_select__(array_index)
+          def __array_select__(array_index, lsb, width)
             if @array_format == :serialized
-              "[#{__serialized_lsb__(array_index)}+:#{@width}]"
+              "[#{__serialized_lsb__(array_index, lsb)}+:#{width || @width}]"
             else
-              array_index
-                .map { |index| "[#{index}]" }
-                .join
+              [
+                *array_index.map { |index| "[#{index}]" },
+                lsb && __create_select__(lsb, width, nil)
+              ].compact.join
             end
           end
 
-          def __serialized_lsb__(array_index)
-            __reduce_array__([@width, __serialized_index__(array_index)], :*, 1)
+          def __serialized_lsb__(array_index, lsb)
+            serialized_index = __serialized_index__(array_index)
+            array_lsb = __reduce_array__([@width, serialized_index], :*, 1)
+            __reduce_array__([array_lsb, lsb], :+, 0)
           end
 
           def __serialized_index__(array_index)
@@ -97,6 +100,7 @@ module RgGen
           end
 
           def __reduce_array__(array, operator, initial_value)
+            array = array.compact
             if array.all?(&method(:integer?))
               array.reduce(initial_value, &operator)
             else

data/lib/rggen/systemverilog/ral.rb

@@ -7,35 +7,29 @@ require_relative 'ral/register_common'
 module RgGen
   module SystemVerilog
     module RAL
-      FEATURES = [
-        'ral/bit_field/type',
-        'ral/bit_field/type/reserved_rof',
-        'ral/bit_field/type/rwc_rws',
-        'ral/bit_field/type/rwe_rwl',
-        'ral/bit_field/type/w0trg_w1trg',
-        'ral/register/type',
-        'ral/register/type/external',
-        'ral/register/type/indirect',
-        'ral/register_block/sv_ral_model',
-        'ral/register_block/sv_ral_package',
-        'ral/register_file/sv_ral_model'
-      ].freeze
+      extend Core::Plugin
 
-      def self.version
-        SystemVerilog::VERSION
-      end
-
-      def self.register_component(builder)
-        Common.register_component(builder, :sv_ral, Feature)
-      end
+      setup_plugin :'rggen-sv-ral' do |plugin|
+        plugin.version SystemVerilog::VERSION
 
-      def self.load_features
-        Common.load_features(FEATURES, __dir__)
-      end
+        plugin.register_component :sv_ral do
+          component Common::Component, Common::ComponentFactory
+          feature Feature, Common::FeatureFactory
+        end
 
-      def self.default_setup(builder)
-        register_component(builder)
-        load_features
+        plugin.files [
+          'ral/bit_field/type',
+          'ral/bit_field/type/reserved_rof',
+          'ral/bit_field/type/rwc_rws',
+          'ral/bit_field/type/rwe_rwl',
+          'ral/bit_field/type/w0trg_w1trg',
+          'ral/register/type',
+          'ral/register/type/external',
+          'ral/register/type/indirect',
+          'ral/register_block/sv_ral_model',
+          'ral/register_block/sv_ral_package',
+          'ral/register_file/sv_ral_model'
+        ]
       end
     end
   end

data/lib/rggen/systemverilog/ral/bit_field/type.rb

@@ -29,7 +29,7 @@ RgGen.define_list_feature(:bit_field, :type) do
 
       def model_name
         name = helper.model_name
-        name&.is_a?(Proc) && instance_eval(&name) || name || :rggen_ral_field
+        name.is_a?(Proc) && instance_eval(&name) || name || :rggen_ral_field
       end
 
       def constructors

data/lib/rggen/systemverilog/ral/setup.rb

@@ -2,7 +2,7 @@
 
 require 'rggen/systemverilog/ral'
 
-RgGen.setup :'rggen-sv-ral', RgGen::SystemVerilog::RAL do |builder|
+RgGen.register_plugin RgGen::SystemVerilog::RAL do |builder|
   builder.enable :register_block, [:sv_ral_model, :sv_ral_package]
   builder.enable :register_file, [:sv_ral_model]
 end

data/lib/rggen/systemverilog/rtl.rb

@@ -4,54 +4,52 @@ require_relative 'common'
 require_relative 'rtl/feature'
 require_relative 'rtl/partial_sum'
 require_relative 'rtl/register_index'
+require_relative 'rtl/register_type'
+require_relative 'rtl/indirect_index'
+require_relative 'rtl/bit_field_index'
 
 module RgGen
   module SystemVerilog
     module RTL
-      FEATURES = [
-        'rtl/bit_field/sv_rtl_top',
-        'rtl/bit_field/type',
-        'rtl/bit_field/type/rc_w0c_w1c',
-        'rtl/bit_field/type/reserved',
-        'rtl/bit_field/type/ro',
-        'rtl/bit_field/type/rof',
-        'rtl/bit_field/type/rs_w0s_w1s',
-        'rtl/bit_field/type/rw_w1_wo_wo1',
-        'rtl/bit_field/type/rwc',
-        'rtl/bit_field/type/rwe',
-        'rtl/bit_field/type/rwl',
-        'rtl/bit_field/type/rws',
-        'rtl/bit_field/type/w0crs_w1crs',
-        'rtl/bit_field/type/w0src_w1src',
-        'rtl/bit_field/type/w0trg_w1trg',
-        'rtl/global/array_port_format',
-        'rtl/global/fold_sv_interface_port',
-        'rtl/register/sv_rtl_top',
-        'rtl/register/type',
-        'rtl/register/type/external',
-        'rtl/register/type/indirect',
-        'rtl/register_block/protocol',
-        'rtl/register_block/protocol/apb',
-        'rtl/register_block/protocol/axi4lite',
-        'rtl/register_block/sv_rtl_top',
-        'rtl/register_file/sv_rtl_top'
-      ].freeze
+      extend Core::Plugin
 
-      def self.version
-        SystemVerilog::VERSION
-      end
-
-      def self.register_component(builder)
-        Common.register_component(builder, :sv_rtl, Feature)
-      end
+      setup_plugin :'rggen-sv-rtl' do |plugin|
+        plugin.version SystemVerilog::VERSION
 
-      def self.load_features
-        Common.load_features(FEATURES, __dir__)
-      end
+        plugin.register_component :sv_rtl do
+          component Common::Component, Common::ComponentFactory
+          feature Feature, Common::FeatureFactory
+        end
 
-      def self.default_setup(builder)
-        register_component(builder)
-        load_features
+        plugin.files [
+          'rtl/bit_field/sv_rtl_top',
+          'rtl/bit_field/type',
+          'rtl/bit_field/type/rc_w0c_w1c_wc_woc',
+          'rtl/bit_field/type/reserved',
+          'rtl/bit_field/type/ro',
+          'rtl/bit_field/type/rof',
+          'rtl/bit_field/type/rs_w0s_w1s_ws_wos',
+          'rtl/bit_field/type/rw_w1_wo_wo1',
+          'rtl/bit_field/type/rwc',
+          'rtl/bit_field/type/rwe',
+          'rtl/bit_field/type/rwl',
+          'rtl/bit_field/type/rws',
+          'rtl/bit_field/type/w0crs_w0src_w1crs_w1src_wcrs_wsrc',
+          'rtl/bit_field/type/w0t_w1t',
+          'rtl/bit_field/type/w0trg_w1trg',
+          'rtl/bit_field/type/wrc_wrs',
+          'rtl/global/array_port_format',
+          'rtl/global/fold_sv_interface_port',
+          'rtl/register/sv_rtl_top',
+          'rtl/register/type',
+          'rtl/register/type/external',
+          'rtl/register/type/indirect',
+          'rtl/register_block/protocol',
+          'rtl/register_block/protocol/apb',
+          'rtl/register_block/protocol/axi4lite',
+          'rtl/register_block/sv_rtl_top',
+          'rtl/register_file/sv_rtl_top'
+        ]
       end
     end
   end

data/lib/rggen/systemverilog/rtl/bit_field/sv_rtl_top.rb

@@ -2,10 +2,8 @@
 
 RgGen.define_simple_feature(:bit_field, :sv_rtl_top) do
   sv_rtl do
-    export :local_index
-    export :local_indices
-    export :loop_variables
-    export :array_size
+    include RgGen::SystemVerilog::RTL::BitFieldIndex
+
     export :value
 
     build do
@@ -13,13 +11,13 @@ RgGen.define_simple_feature(:bit_field, :sv_rtl_top) do
         localparam :initial_value, {
           name: initial_value_name, data_type: :bit, width: bit_field.width,
           array_size: initial_value_size, array_format: initial_value_format,
-          default: initial_value_lhs
+          default: initial_value_rhs
         }
       elsif initial_value?
         parameter :initial_value, {
           name: initial_value_name, data_type: :bit, width: bit_field.width,
           array_size: initial_value_size, array_format: initial_value_format,
-          default: initial_value_lhs
+          default: initial_value_rhs
         }
       end
       interface :bit_field_sub_if, {
@@ -42,31 +40,8 @@ RgGen.define_simple_feature(:bit_field, :sv_rtl_top) do
       code << bit_field_if_connection << nl
     end
 
-    def local_index
-      (index_name = local_index_name) &&
-        create_identifier(index_name)
-    end
-
-    def local_indices
-      [*register.local_indices, local_index_name]
-    end
-
-    def loop_variables
-      (inside_loop? || nil) &&
-        [*register.loop_variables, local_index].compact
-    end
-
-    def array_size
-      (inside_loop? || nil) &&
-        [
-          *register_files.flat_map(&:array_size),
-          *register.array_size,
-          *bit_field.sequence_size
-        ].compact
-    end
-
     def value(offsets = nil, width = nil)
-      value_lsb = bit_field.lsb(offsets&.last || local_index_name)
+      value_lsb = bit_field.lsb(offsets&.last || local_index)
       value_width = width || bit_field.width
       register_if(offsets&.slice(0..-2)).value[value_lsb, value_width]
     end
@@ -77,14 +52,6 @@ RgGen.define_simple_feature(:bit_field, :sv_rtl_top) do
       define_method(m) { bit_field.__send__(__method__) }
     end
 
-    def local_index_name
-      (bit_field.sequential? || nil) &&
-        begin
-          depth = (register.loop_variables&.size || 0) + 1
-          loop_index(depth)
-        end
-    end
-
     def register_if(offsets)
       index = register.index(offsets || register.local_indices)
       register_block.register_if[index]
@@ -106,11 +73,11 @@ RgGen.define_simple_feature(:bit_field, :sv_rtl_top) do
         configuration.array_port_format
     end
 
-    def initial_value_lhs
-      initial_value_array? && initial_value_array_lhs || sized_initial_value
+    def initial_value_rhs
+      initial_value_array? && initial_value_array_rhs || sized_initial_value
     end
 
-    def initial_value_array_lhs
+    def initial_value_array_rhs
       if fixed_initial_value?
         array(sized_initial_values)
       elsif initial_value_format == :unpacked
@@ -129,12 +96,9 @@ RgGen.define_simple_feature(:bit_field, :sv_rtl_top) do
       bit_field.initial_values&.map { |v| hex(v, bit_field.width) }
     end
 
-    def inside_loop?
-      register.array? || bit_field.sequential?
-    end
-
     def loop_size
-      (loop_variable = local_index_name) &&
+      loop_variable = local_index
+      loop_variable &&
         { loop_variable => bit_field.sequence_size }
     end