rggen-systemverilog 0.21.0 → 0.24.0
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- checksums.yaml +4 -4
- data/LICENSE +1 -1
- data/README.md +2 -2
- data/lib/rggen/systemverilog/common.rb +0 -22
- data/lib/rggen/systemverilog/common/feature.rb +2 -2
- data/lib/rggen/systemverilog/common/utility.rb +4 -0
- data/lib/rggen/systemverilog/common/utility/identifier.rb +19 -15
- data/lib/rggen/systemverilog/ral.rb +20 -26
- data/lib/rggen/systemverilog/ral/bit_field/type.rb +1 -1
- data/lib/rggen/systemverilog/ral/setup.rb +1 -1
- data/lib/rggen/systemverilog/rtl.rb +39 -41
- data/lib/rggen/systemverilog/rtl/bit_field/sv_rtl_top.rb +10 -46
- data/lib/rggen/systemverilog/rtl/bit_field/type.rb +1 -2
- data/lib/rggen/systemverilog/rtl/bit_field/type/rc_w0c_w1c_wc_woc.erb +19 -0
- data/lib/rggen/systemverilog/rtl/bit_field/type/{rc_w0c_w1c.rb → rc_w0c_w1c_wc_woc.rb} +22 -11
- data/lib/rggen/systemverilog/rtl/bit_field/type/reserved.erb +17 -2
- data/lib/rggen/systemverilog/rtl/bit_field/type/ro.erb +15 -4
- data/lib/rggen/systemverilog/rtl/bit_field/type/rof.erb +15 -4
- data/lib/rggen/systemverilog/rtl/bit_field/type/rs_w0s_w1s_ws_wos.erb +19 -0
- data/lib/rggen/systemverilog/rtl/bit_field/type/{rs_w0s_w1s.rb → rs_w0s_w1s_ws_wos.rb} +21 -9
- data/lib/rggen/systemverilog/rtl/bit_field/type/rw_w1_wo_wo1.erb +15 -7
- data/lib/rggen/systemverilog/rtl/bit_field/type/rw_w1_wo_wo1.rb +2 -2
- data/lib/rggen/systemverilog/rtl/bit_field/type/rwc.erb +15 -7
- data/lib/rggen/systemverilog/rtl/bit_field/type/rwe.erb +16 -8
- data/lib/rggen/systemverilog/rtl/bit_field/type/rwl.erb +16 -8
- data/lib/rggen/systemverilog/rtl/bit_field/type/rws.erb +13 -7
- data/lib/rggen/systemverilog/rtl/bit_field/type/w0crs_w0src_w1crs_w1src_wcrs_wsrc.erb +19 -0
- data/lib/rggen/systemverilog/rtl/bit_field/type/w0crs_w0src_w1crs_w1src_wcrs_wsrc.rb +37 -0
- data/lib/rggen/systemverilog/rtl/bit_field/type/w0t_w1t.erb +18 -0
- data/lib/rggen/systemverilog/rtl/bit_field/type/{w0src_w1src.rb → w0t_w1t.rb} +6 -4
- data/lib/rggen/systemverilog/rtl/bit_field/type/wrc_wrs.erb +18 -0
- data/lib/rggen/systemverilog/rtl/bit_field/type/{w0crs_w1crs.rb → wrc_wrs.rb} +6 -4
- data/lib/rggen/systemverilog/rtl/bit_field_index.rb +53 -0
- data/lib/rggen/systemverilog/rtl/indirect_index.rb +35 -0
- data/lib/rggen/systemverilog/rtl/register/type.rb +1 -56
- data/lib/rggen/systemverilog/rtl/register/type/external.rb +0 -4
- data/lib/rggen/systemverilog/rtl/register/type/indirect.rb +2 -26
- data/lib/rggen/systemverilog/rtl/register_block/protocol.rb +14 -8
- data/lib/rggen/systemverilog/rtl/register_block/protocol/axi4lite.erb +1 -0
- data/lib/rggen/systemverilog/rtl/register_block/protocol/axi4lite.rb +55 -28
- data/lib/rggen/systemverilog/rtl/register_block/sv_rtl_top.rb +1 -1
- data/lib/rggen/systemverilog/rtl/register_index.rb +4 -4
- data/lib/rggen/systemverilog/rtl/register_type.rb +68 -0
- data/lib/rggen/systemverilog/rtl/setup.rb +1 -1
- data/lib/rggen/systemverilog/version.rb +1 -1
- metadata +17 -26
- data/lib/rggen/systemverilog/rtl/bit_field/type/rc_w0c_w1c.erb +0 -15
- data/lib/rggen/systemverilog/rtl/bit_field/type/rs_w0s_w1s.erb +0 -13
- data/lib/rggen/systemverilog/rtl/bit_field/type/w0crs_w1crs.erb +0 -10
- data/lib/rggen/systemverilog/rtl/bit_field/type/w0src_w1src.erb +0 -10
checksums.yaml
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---
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SHA256:
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metadata.gz:
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data.tar.gz:
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metadata.gz: 2cfff9e2a346d5c02dc5a6401e8b36fdd15d20b9d4d4030b5fcc56880521ccd4
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data.tar.gz: 75bd4c611fa964f30df059fe39d547daf688322ed1076654744381dc38a67068
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SHA512:
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metadata.gz:
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data.tar.gz:
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metadata.gz: 3c5e0b0b5c3352532161411d2ce6e8ca8728231377c7453953a1c1804b8c08bd134ba487264d7a63c192744278184de7923f598dfbde80096a41b6040467af45
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data.tar.gz: 37a27563ccee405d16d2778728e186331bdb9a7711b73d017eb1bf3fd4479000c2bf54621dbab43b903897755a05026a3c7ae25cb68b1624cef63a250bf3eda0
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data/LICENSE
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The MIT License (MIT)
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Copyright (c) 2019-
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Copyright (c) 2019-2021 Taichi Ishitani
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Permission is hereby granted, free of charge, to any person obtaining a copy
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of this software and associated documentation files (the "Software"), to deal
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data/README.md
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# RgGen::SystemVerilog
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RgGen::SystemVerilog
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RgGen::SystemVerilog provides SystemVerilog RTL and UVM register model (UVM RAL) generators for RgGen.
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## Installation
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@@ -34,7 +34,7 @@ Feedbacks, bug reports, questions and etc. are wellcome! You can post them by us
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## Copyright & License
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Copyright © 2019-
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Copyright © 2019-2021 Taichi Ishitani. RgGen::SystemVerilog is licensed under the [MIT License](https://opensource.org/licenses/MIT), see [LICENSE](LICENSE) for futher details.
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## Code of Conduct
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@@ -1,6 +1,5 @@
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# frozen_string_literal: true
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-
require 'docile'
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require 'facets/kernel/attr_singleton'
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require_relative 'version'
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require_relative 'common/component'
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require_relative 'common/feature'
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require_relative 'common/factories'
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-
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module RgGen
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module SystemVerilog
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module Common
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def self.register_component(builder, name, feature_class)
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builder.output_component_registry(name) do
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register_component [
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:root, :register_block, :register_file, :register, :bit_field
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] do |category|
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component Component, ComponentFactory
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feature feature_class, FeatureFactory if category != :root
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end
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end
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end
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-
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def self.load_features(features, root)
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features.each { |feature| require File.join(root, feature) }
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end
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end
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end
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end
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template_engine Core::OutputBase::ERBEngine
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EntityContext =
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Struct.new(:entity_type, :
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Struct.new(:entity_type, :method_name, :declaration_type, :default_layer)
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class << self
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private
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def create_entity(context, name, attributes, &block)
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merged_attributes = { name: name }.merge(Hash(attributes))
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-
__send__(context.
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+
__send__(context.method_name, context.entity_type, merged_attributes, &block)
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end
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def add_entity(context, entity, name, layer)
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@@ -35,9 +35,9 @@ module RgGen
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@name.to_s
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end
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-
def [](array_index_or_lsb, width = nil)
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def [](array_index_or_lsb, lsb_or_width = nil, width = nil)
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if array_index_or_lsb
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-
__create_new_identifier__(array_index_or_lsb, width)
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+
__create_new_identifier__(array_index_or_lsb, lsb_or_width, width)
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else
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self
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end
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private
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-
def __create_new_identifier__(array_index_or_lsb, width)
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-
select = __create_select__(array_index_or_lsb, width)
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def __create_new_identifier__(array_index_or_lsb, lsb_or_width, width)
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select = __create_select__(array_index_or_lsb, lsb_or_width, width)
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Identifier.new("#{@name}#{select}") do |identifier|
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identifier.__sub_identifiers__(@sub_identifiers)
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end
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end
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def __create_select__(array_index_or_lsb, width)
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def __create_select__(array_index_or_lsb, lsb_or_width, width)
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if array_index_or_lsb.is_a?(::Array)
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__array_select__(array_index_or_lsb)
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-
elsif
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"[#{array_index_or_lsb}+:#{
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__array_select__(array_index_or_lsb, lsb_or_width, width)
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elsif lsb_or_width
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"[#{array_index_or_lsb}+:#{lsb_or_width}]"
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else
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"[#{array_index_or_lsb}]"
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end
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end
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def __array_select__(array_index)
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def __array_select__(array_index, lsb, width)
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if @array_format == :serialized
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"[#{__serialized_lsb__(array_index)}+:#{@width}]"
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"[#{__serialized_lsb__(array_index, lsb)}+:#{width || @width}]"
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else
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-
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.map { |index| "[#{index}]" }
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-
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[
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*array_index.map { |index| "[#{index}]" },
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lsb && __create_select__(lsb, width, nil)
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].compact.join
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end
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end
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def __serialized_lsb__(array_index)
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-
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def __serialized_lsb__(array_index, lsb)
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serialized_index = __serialized_index__(array_index)
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array_lsb = __reduce_array__([@width, serialized_index], :*, 1)
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__reduce_array__([array_lsb, lsb], :+, 0)
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end
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def __serialized_index__(array_index)
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end
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def __reduce_array__(array, operator, initial_value)
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array = array.compact
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if array.all?(&method(:integer?))
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array.reduce(initial_value, &operator)
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else
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@@ -7,35 +7,29 @@ require_relative 'ral/register_common'
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module RgGen
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module SystemVerilog
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module RAL
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'ral/bit_field/type',
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'ral/bit_field/type/reserved_rof',
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'ral/bit_field/type/rwc_rws',
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'ral/bit_field/type/rwe_rwl',
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'ral/bit_field/type/w0trg_w1trg',
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'ral/register/type',
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'ral/register/type/external',
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'ral/register/type/indirect',
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'ral/register_block/sv_ral_model',
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'ral/register_block/sv_ral_package',
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'ral/register_file/sv_ral_model'
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].freeze
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extend Core::Plugin
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-
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-
SystemVerilog::VERSION
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-
end
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-
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def self.register_component(builder)
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Common.register_component(builder, :sv_ral, Feature)
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-
end
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setup_plugin :'rggen-sv-ral' do |plugin|
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plugin.version SystemVerilog::VERSION
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-
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-
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-
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plugin.register_component :sv_ral do
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component Common::Component, Common::ComponentFactory
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feature Feature, Common::FeatureFactory
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end
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-
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-
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-
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plugin.files [
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'ral/bit_field/type',
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'ral/bit_field/type/reserved_rof',
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'ral/bit_field/type/rwc_rws',
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+
'ral/bit_field/type/rwe_rwl',
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'ral/bit_field/type/w0trg_w1trg',
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+
'ral/register/type',
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'ral/register/type/external',
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'ral/register/type/indirect',
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'ral/register_block/sv_ral_model',
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'ral/register_block/sv_ral_package',
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+
'ral/register_file/sv_ral_model'
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+
]
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end
|
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end
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end
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@@ -29,7 +29,7 @@ RgGen.define_list_feature(:bit_field, :type) do
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def model_name
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name = helper.model_name
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-
name
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name.is_a?(Proc) && instance_eval(&name) || name || :rggen_ral_field
|
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end
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def constructors
|
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require 'rggen/systemverilog/ral'
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RgGen.
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RgGen.register_plugin RgGen::SystemVerilog::RAL do |builder|
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builder.enable :register_block, [:sv_ral_model, :sv_ral_package]
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builder.enable :register_file, [:sv_ral_model]
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end
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@@ -4,54 +4,52 @@ require_relative 'common'
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require_relative 'rtl/feature'
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require_relative 'rtl/partial_sum'
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require_relative 'rtl/register_index'
|
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+
require_relative 'rtl/register_type'
|
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require_relative 'rtl/indirect_index'
|
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require_relative 'rtl/bit_field_index'
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|
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module RgGen
|
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module SystemVerilog
|
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module RTL
|
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-
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'rtl/bit_field/sv_rtl_top',
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'rtl/bit_field/type',
|
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'rtl/bit_field/type/rc_w0c_w1c',
|
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|
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'rtl/bit_field/type/reserved',
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'rtl/bit_field/type/ro',
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'rtl/bit_field/type/rof',
|
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-
'rtl/bit_field/type/rs_w0s_w1s',
|
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-
'rtl/bit_field/type/rw_w1_wo_wo1',
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-
'rtl/bit_field/type/rwc',
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-
'rtl/bit_field/type/rwe',
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-
'rtl/bit_field/type/rwl',
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-
'rtl/bit_field/type/rws',
|
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-
'rtl/bit_field/type/w0crs_w1crs',
|
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-
'rtl/bit_field/type/w0src_w1src',
|
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-
'rtl/bit_field/type/w0trg_w1trg',
|
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-
'rtl/global/array_port_format',
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-
'rtl/global/fold_sv_interface_port',
|
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-
'rtl/register/sv_rtl_top',
|
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'rtl/register/type',
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'rtl/register/type/external',
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'rtl/register/type/indirect',
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'rtl/register_block/protocol',
|
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-
'rtl/register_block/protocol/apb',
|
35
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'rtl/register_block/protocol/axi4lite',
|
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-
'rtl/register_block/sv_rtl_top',
|
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-
'rtl/register_file/sv_rtl_top'
|
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-
].freeze
|
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extend Core::Plugin
|
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-
|
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-
SystemVerilog::VERSION
|
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-
end
|
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-
|
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-
def self.register_component(builder)
|
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-
Common.register_component(builder, :sv_rtl, Feature)
|
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-
end
|
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+
setup_plugin :'rggen-sv-rtl' do |plugin|
|
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plugin.version SystemVerilog::VERSION
|
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-
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-
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-
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plugin.register_component :sv_rtl do
|
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component Common::Component, Common::ComponentFactory
|
21
|
+
feature Feature, Common::FeatureFactory
|
22
|
+
end
|
51
23
|
|
52
|
-
|
53
|
-
|
54
|
-
|
24
|
+
plugin.files [
|
25
|
+
'rtl/bit_field/sv_rtl_top',
|
26
|
+
'rtl/bit_field/type',
|
27
|
+
'rtl/bit_field/type/rc_w0c_w1c_wc_woc',
|
28
|
+
'rtl/bit_field/type/reserved',
|
29
|
+
'rtl/bit_field/type/ro',
|
30
|
+
'rtl/bit_field/type/rof',
|
31
|
+
'rtl/bit_field/type/rs_w0s_w1s_ws_wos',
|
32
|
+
'rtl/bit_field/type/rw_w1_wo_wo1',
|
33
|
+
'rtl/bit_field/type/rwc',
|
34
|
+
'rtl/bit_field/type/rwe',
|
35
|
+
'rtl/bit_field/type/rwl',
|
36
|
+
'rtl/bit_field/type/rws',
|
37
|
+
'rtl/bit_field/type/w0crs_w0src_w1crs_w1src_wcrs_wsrc',
|
38
|
+
'rtl/bit_field/type/w0t_w1t',
|
39
|
+
'rtl/bit_field/type/w0trg_w1trg',
|
40
|
+
'rtl/bit_field/type/wrc_wrs',
|
41
|
+
'rtl/global/array_port_format',
|
42
|
+
'rtl/global/fold_sv_interface_port',
|
43
|
+
'rtl/register/sv_rtl_top',
|
44
|
+
'rtl/register/type',
|
45
|
+
'rtl/register/type/external',
|
46
|
+
'rtl/register/type/indirect',
|
47
|
+
'rtl/register_block/protocol',
|
48
|
+
'rtl/register_block/protocol/apb',
|
49
|
+
'rtl/register_block/protocol/axi4lite',
|
50
|
+
'rtl/register_block/sv_rtl_top',
|
51
|
+
'rtl/register_file/sv_rtl_top'
|
52
|
+
]
|
55
53
|
end
|
56
54
|
end
|
57
55
|
end
|
@@ -2,10 +2,8 @@
|
|
2
2
|
|
3
3
|
RgGen.define_simple_feature(:bit_field, :sv_rtl_top) do
|
4
4
|
sv_rtl do
|
5
|
-
|
6
|
-
|
7
|
-
export :loop_variables
|
8
|
-
export :array_size
|
5
|
+
include RgGen::SystemVerilog::RTL::BitFieldIndex
|
6
|
+
|
9
7
|
export :value
|
10
8
|
|
11
9
|
build do
|
@@ -13,13 +11,13 @@ RgGen.define_simple_feature(:bit_field, :sv_rtl_top) do
|
|
13
11
|
localparam :initial_value, {
|
14
12
|
name: initial_value_name, data_type: :bit, width: bit_field.width,
|
15
13
|
array_size: initial_value_size, array_format: initial_value_format,
|
16
|
-
default:
|
14
|
+
default: initial_value_rhs
|
17
15
|
}
|
18
16
|
elsif initial_value?
|
19
17
|
parameter :initial_value, {
|
20
18
|
name: initial_value_name, data_type: :bit, width: bit_field.width,
|
21
19
|
array_size: initial_value_size, array_format: initial_value_format,
|
22
|
-
default:
|
20
|
+
default: initial_value_rhs
|
23
21
|
}
|
24
22
|
end
|
25
23
|
interface :bit_field_sub_if, {
|
@@ -42,31 +40,8 @@ RgGen.define_simple_feature(:bit_field, :sv_rtl_top) do
|
|
42
40
|
code << bit_field_if_connection << nl
|
43
41
|
end
|
44
42
|
|
45
|
-
def local_index
|
46
|
-
(index_name = local_index_name) &&
|
47
|
-
create_identifier(index_name)
|
48
|
-
end
|
49
|
-
|
50
|
-
def local_indices
|
51
|
-
[*register.local_indices, local_index_name]
|
52
|
-
end
|
53
|
-
|
54
|
-
def loop_variables
|
55
|
-
(inside_loop? || nil) &&
|
56
|
-
[*register.loop_variables, local_index].compact
|
57
|
-
end
|
58
|
-
|
59
|
-
def array_size
|
60
|
-
(inside_loop? || nil) &&
|
61
|
-
[
|
62
|
-
*register_files.flat_map(&:array_size),
|
63
|
-
*register.array_size,
|
64
|
-
*bit_field.sequence_size
|
65
|
-
].compact
|
66
|
-
end
|
67
|
-
|
68
43
|
def value(offsets = nil, width = nil)
|
69
|
-
value_lsb = bit_field.lsb(offsets&.last ||
|
44
|
+
value_lsb = bit_field.lsb(offsets&.last || local_index)
|
70
45
|
value_width = width || bit_field.width
|
71
46
|
register_if(offsets&.slice(0..-2)).value[value_lsb, value_width]
|
72
47
|
end
|
@@ -77,14 +52,6 @@ RgGen.define_simple_feature(:bit_field, :sv_rtl_top) do
|
|
77
52
|
define_method(m) { bit_field.__send__(__method__) }
|
78
53
|
end
|
79
54
|
|
80
|
-
def local_index_name
|
81
|
-
(bit_field.sequential? || nil) &&
|
82
|
-
begin
|
83
|
-
depth = (register.loop_variables&.size || 0) + 1
|
84
|
-
loop_index(depth)
|
85
|
-
end
|
86
|
-
end
|
87
|
-
|
88
55
|
def register_if(offsets)
|
89
56
|
index = register.index(offsets || register.local_indices)
|
90
57
|
register_block.register_if[index]
|
@@ -106,11 +73,11 @@ RgGen.define_simple_feature(:bit_field, :sv_rtl_top) do
|
|
106
73
|
configuration.array_port_format
|
107
74
|
end
|
108
75
|
|
109
|
-
def
|
110
|
-
initial_value_array? &&
|
76
|
+
def initial_value_rhs
|
77
|
+
initial_value_array? && initial_value_array_rhs || sized_initial_value
|
111
78
|
end
|
112
79
|
|
113
|
-
def
|
80
|
+
def initial_value_array_rhs
|
114
81
|
if fixed_initial_value?
|
115
82
|
array(sized_initial_values)
|
116
83
|
elsif initial_value_format == :unpacked
|
@@ -129,12 +96,9 @@ RgGen.define_simple_feature(:bit_field, :sv_rtl_top) do
|
|
129
96
|
bit_field.initial_values&.map { |v| hex(v, bit_field.width) }
|
130
97
|
end
|
131
98
|
|
132
|
-
def inside_loop?
|
133
|
-
register.array? || bit_field.sequential?
|
134
|
-
end
|
135
|
-
|
136
99
|
def loop_size
|
137
|
-
|
100
|
+
loop_variable = local_index
|
101
|
+
loop_variable &&
|
138
102
|
{ loop_variable => bit_field.sequence_size }
|
139
103
|
end
|
140
104
|
|