rggen-systemverilog 0.21.0 → 0.24.0

data/lib/rggen/systemverilog/rtl/bit_field/type.rb

@@ -35,8 +35,7 @@ RgGen.define_list_feature(:bit_field, :type) do
       end
 
       def mask
-        reference_bit_field ||
-          hex(2**bit_field.width - 1, bit_field.width)
+        reference_bit_field || all_bits_1
       end
 
       def reference_bit_field

data/lib/rggen/systemverilog/rtl/bit_field/type/rc_w0c_w1c_wc_woc.erb

@@ -0,0 +1,19 @@
+rggen_bit_field #(
+  .WIDTH            (<%= width %>),
+  .INITIAL_VALUE    (<%= initial_value %>),
+  .SW_READ_ACTION   (<%= read_action %>),
+  .SW_WRITE_ACTION  (<%= write_action %>)
+) u_bit_field (
+  .i_clk              (<%= clock %>),
+  .i_rst_n            (<%= reset %>),
+  .bit_field_if       (<%= bit_field_if %>),
+  .i_sw_write_enable  (<%= write_enable %>),
+  .i_hw_write_enable  ('0),
+  .i_hw_write_data    ('0),
+  .i_hw_set           (<%= set[loop_variables] %>),
+  .i_hw_clear         ('0),
+  .i_value            ('0),
+  .i_mask             (<%= mask %>),
+  .o_value            (<%= value_out[loop_variables] %>),
+  .o_value_unmasked   (<%= value_out_unmasked %>)
+);

data/lib/rggen/systemverilog/rtl/bit_field/type/{rc_w0c_w1c.rb → rc_w0c_w1c_wc_woc.rb}

@@ -1,6 +1,6 @@
 # frozen_string_literal: true
 
-RgGen.define_list_item_feature(:bit_field, :type, [:rc, :w0c, :w1c]) do
+RgGen.define_list_item_feature(:bit_field, :type, [:rc, :w0c, :w1c, :wc, :woc]) do
   sv_rtl do
     build do
       input :set, {
@@ -23,21 +23,32 @@ RgGen.define_list_item_feature(:bit_field, :type, [:rc, :w0c, :w1c]) do
 
     private
 
-    def module_name
-      if bit_field.type == :rc
-        'rggen_bit_field_rc'
-      else
-        'rggen_bit_field_w01c'
-      end
+    def read_action
+      {
+        rc: 'RGGEN_READ_CLEAR',
+        w0c: 'RGGEN_READ_DEFAULT',
+        w1c: 'RGGEN_READ_DEFAULT',
+        wc: 'RGGEN_READ_DEFAULT',
+        woc: 'RGGEN_READ_NONE'
+      }[bit_field.type]
+    end
+
+    def write_action
+      {
+        rc: 'RGGEN_WRITE_NONE',
+        w0c: 'RGGEN_WRITE_0_CLEAR',
+        w1c: 'RGGEN_WRITE_1_CLEAR',
+        wc: 'RGGEN_WRITE_CLEAR',
+        woc: 'RGGEN_WRITE_CLEAR'
+      }[bit_field.type]
     end
 
-    def clear_value
-      bin({ w0c: 0, w1c: 1 }[bit_field.type], 1)
+    def write_enable
+      bit_field.writable? && all_bits_1 || all_bits_0
     end
 
     def value_out_unmasked
-      (bit_field.reference? || nil) &&
-        value_unmasked[loop_variables]
+      (bit_field.reference? || nil) && value_unmasked[loop_variables]
     end
   end
 end

data/lib/rggen/systemverilog/rtl/bit_field/type/reserved.erb

@@ -1,3 +1,18 @@
-rggen_bit_field_reserved u_bit_field (
-  .bit_field_if (<%= bit_field_if %>)
+rggen_bit_field #(
+  .WIDTH          (<%= width %>),
+  .SW_READ_ACTION (RGGEN_READ_NONE),
+  .STORAGE        (0)
+) u_bit_field (
+  .i_clk              ('0),
+  .i_rst_n            ('0),
+  .bit_field_if       (<%= bit_field_if %>),
+  .i_sw_write_enable  ('0),
+  .i_hw_write_enable  ('0),
+  .i_hw_write_data    ('0),
+  .i_hw_set           ('0),
+  .i_hw_clear         ('0),
+  .i_value            ('0),
+  .i_mask             ('0),
+  .o_value            (),
+  .o_value_unmasked   ()
 );

data/lib/rggen/systemverilog/rtl/bit_field/type/ro.erb

@@ -1,6 +1,17 @@
-rggen_bit_field_ro #(
-  .WIDTH  (<%= width %>)
+rggen_bit_field #(
+  .WIDTH    (<%= width %>),
+  .STORAGE  (0)
 ) u_bit_field (
-  .bit_field_if (<%= bit_field_if %>),
-  .i_value      (<%= reference_or_value_in %>)
+  .i_clk              ('0),
+  .i_rst_n            ('0),
+  .bit_field_if       (<%= bit_field_if %>),
+  .i_sw_write_enable  ('0),
+  .i_hw_write_enable  ('0),
+  .i_hw_write_data    ('0),
+  .i_hw_set           ('0),
+  .i_hw_clear         ('0),
+  .i_value            (<%= reference_or_value_in %>),
+  .i_mask             ('1),
+  .o_value            (),
+  .o_value_unmasked   ()
 );

data/lib/rggen/systemverilog/rtl/bit_field/type/rof.erb

@@ -1,6 +1,17 @@
-rggen_bit_field_ro #(
-  .WIDTH  (<%= width %>)
+rggen_bit_field #(
+  .WIDTH    (<%= width %>),
+  .STORAGE  (0)
 ) u_bit_field (
-  .bit_field_if (<%= bit_field_if %>),
-  .i_value      (<%= initial_value %>)
+  .i_clk              ('0),
+  .i_rst_n            ('0),
+  .bit_field_if       (<%= bit_field_if %>),
+  .i_sw_write_enable  ('0),
+  .i_hw_write_enable  ('0),
+  .i_hw_write_data    ('0),
+  .i_hw_set           ('0),
+  .i_hw_clear         ('0),
+  .i_value            (<%= initial_value %>),
+  .i_mask             ('1),
+  .o_value            (),
+  .o_value_unmasked   ()
 );

data/lib/rggen/systemverilog/rtl/bit_field/type/rs_w0s_w1s_ws_wos.erb

@@ -0,0 +1,19 @@
+rggen_bit_field #(
+  .WIDTH            (<%= width %>),
+  .INITIAL_VALUE    (<%= initial_value %>),
+  .SW_READ_ACTION   (<%= read_action %>),
+  .SW_WRITE_ACTION  (<%= write_action %>)
+) u_bit_field (
+  .i_clk              (<%= clock %>),
+  .i_rst_n            (<%= reset %>),
+  .bit_field_if       (<%= bit_field_if %>),
+  .i_sw_write_enable  (<%= write_enable %>),
+  .i_hw_write_enable  ('0),
+  .i_hw_write_data    ('0),
+  .i_hw_set           ('0),
+  .i_hw_clear         (<%= clear[loop_variables] %>),
+  .i_value            ('0),
+  .i_mask             ('1),
+  .o_value            (<%= value_out[loop_variables] %>),
+  .o_value_unmasked   ()
+);

data/lib/rggen/systemverilog/rtl/bit_field/type/{rs_w0s_w1s.rb → rs_w0s_w1s_ws_wos.rb}

@@ -1,6 +1,6 @@
 # frozen_string_literal: true
 
-RgGen.define_list_item_feature(:bit_field, :type, [:rs, :w0s, :w1s]) do
+RgGen.define_list_item_feature(:bit_field, :type, [:rs, :w0s, :w1s, :ws, :wos]) do
   sv_rtl do
     build do
       input :clear, {
@@ -17,16 +17,28 @@ RgGen.define_list_item_feature(:bit_field, :type, [:rs, :w0s, :w1s]) do
 
     private
 
-    def module_name
-      if bit_field.type == :rs
-        'rggen_bit_field_rs'
-      else
-        'rggen_bit_field_w01s'
-      end
+    def read_action
+      {
+        rs: 'RGGEN_READ_SET',
+        w0s: 'RGGEN_READ_DEFAULT',
+        w1s: 'RGGEN_READ_DEFAULT',
+        ws: 'RGGEN_READ_DEFAULT',
+        wos: 'RGGEN_READ_NONE'
+      }[bit_field.type]
     end
 
-    def set_value
-      bin({ w0s: 0, w1s: 1 }[bit_field.type], 1)
+    def write_action
+      {
+        rs: 'RGGEN_WRITE_NONE',
+        w0s: 'RGGEN_WRITE_0_SET',
+        w1s: 'RGGEN_WRITE_1_SET',
+        ws: 'RGGEN_WRITE_SET',
+        wos: 'RGGEN_WRITE_SET'
+      }[bit_field.type]
+    end
+
+    def write_enable
+      bit_field.writable? && all_bits_1 || all_bits_0
     end
   end
 end

data/lib/rggen/systemverilog/rtl/bit_field/type/rw_w1_wo_wo1.erb

@@ -1,11 +1,19 @@
-rggen_bit_field_rw_wo #(
+rggen_bit_field #(
   .WIDTH          (<%= width %>),
   .INITIAL_VALUE  (<%= initial_value %>),
-  .WRITE_ONLY     (<%= write_only %>),
-  .WRITE_ONCE     (<%= write_once %>)
+  .SW_READ_ACTION (<%= read_action %>),
+  .SW_WRITE_ONCE  (<%= write_once %>)
 ) u_bit_field (
-  .i_clk        (<%= clock %>),
-  .i_rst_n      (<%= reset %>),
-  .bit_field_if (<%= bit_field_if %>),
-  .o_value      (<%= value_out[loop_variables] %>)
+  .i_clk              (<%= clock %>),
+  .i_rst_n            (<%= reset %>),
+  .bit_field_if       (<%= bit_field_if %>),
+  .i_sw_write_enable  ('1),
+  .i_hw_write_enable  ('0),
+  .i_hw_write_data    ('0),
+  .i_hw_set           ('0),
+  .i_hw_clear         ('0),
+  .i_value            ('0),
+  .i_mask             ('1),
+  .o_value            (<%= value_out[loop_variables] %>),
+  .o_value_unmasked   ()
 );

data/lib/rggen/systemverilog/rtl/bit_field/type/rw_w1_wo_wo1.rb

@@ -13,8 +13,8 @@ RgGen.define_list_item_feature(:bit_field, :type, [:rw, :w1, :wo, :wo1]) do
 
     private
 
-    def write_only
-      bit_field.write_only? && 1 || 0
+    def read_action
+      bit_field.readable? && 'RGGEN_READ_DEFAULT' || 'RGGEN_READ_NONE'
     end
 
     def write_once

data/lib/rggen/systemverilog/rtl/bit_field/type/rwc.erb

@@ -1,10 +1,18 @@
-rggen_bit_field_rwc #(
+rggen_bit_field #(
   .WIDTH          (<%= width %>),
-  .INITIAL_VALUE  (<%= initial_value %>)
+  .INITIAL_VALUE  (<%= initial_value %>),
+  .HW_CLEAR_WIDTH (1)
 ) u_bit_field (
-  .i_clk        (<%= clock %>),
-  .i_rst_n      (<%= reset %>),
-  .bit_field_if (<%= bit_field_if %>),
-  .i_clear      (<%= clear_signal %>),
-  .o_value      (<%= value_out[loop_variables] %>)
+  .i_clk              (<%= clock %>),
+  .i_rst_n            (<%= reset %>),
+  .bit_field_if       (<%= bit_field_if %>),
+  .i_sw_write_enable  ('1),
+  .i_hw_write_enable  ('0),
+  .i_hw_write_data    ('0),
+  .i_hw_set           ('0),
+  .i_hw_clear         (<%= clear_signal %>),
+  .i_value            ('0),
+  .i_mask             ('1),
+  .o_value            (<%= value_out[loop_variables] %>),
+  .o_value_unmasked   ()
 );

data/lib/rggen/systemverilog/rtl/bit_field/type/rwe.erb

@@ -1,10 +1,18 @@
-rggen_bit_field_rwe #(
-  .WIDTH          (<%= width %>),
-  .INITIAL_VALUE  (<%= initial_value %>)
+rggen_bit_field #(
+  .WIDTH                    (<%= width %>),
+  .INITIAL_VALUE            (<%= initial_value %>),
+  .SW_WRITE_ENABLE_POLARITY (RGGEN_ACTIVE_HIGH)
 ) u_bit_field (
-  .i_clk        (<%= clock %>),
-  .i_rst_n      (<%= reset %>),
-  .bit_field_if (<%= bit_field_if %>),
-  .i_enable     (<%= enable_signal %>),
-  .o_value      (<%= value_out[loop_variables] %>)
+  .i_clk              (<%= clock %>),
+  .i_rst_n            (<%= reset %>),
+  .bit_field_if       (<%= bit_field_if %>),
+  .i_sw_write_enable  (<%= enable_signal %>),
+  .i_hw_write_enable  ('0),
+  .i_hw_write_data    ('0),
+  .i_hw_set           ('0),
+  .i_hw_clear         ('0),
+  .i_value            ('0),
+  .i_mask             ('1),
+  .o_value            (<%= value_out[loop_variables] %>),
+  .o_value_unmasked   ()
 );

data/lib/rggen/systemverilog/rtl/bit_field/type/rwl.erb

@@ -1,10 +1,18 @@
-rggen_bit_field_rwl #(
-  .WIDTH          (<%= width %>),
-  .INITIAL_VALUE  (<%= initial_value %>)
+rggen_bit_field #(
+  .WIDTH                    (<%= width %>),
+  .INITIAL_VALUE            (<%= initial_value %>),
+  .SW_WRITE_ENABLE_POLARITY (RGGEN_ACTIVE_LOW)
 ) u_bit_field (
-  .i_clk        (<%= clock %>),
-  .i_rst_n      (<%= reset %>),
-  .bit_field_if (<%= bit_field_if %>),
-  .i_lock       (<%= lock_signal %>),
-  .o_value      (<%= value_out[loop_variables] %>)
+  .i_clk              (<%= clock %>),
+  .i_rst_n            (<%= reset %>),
+  .bit_field_if       (<%= bit_field_if %>),
+  .i_sw_write_enable  (<%= lock_signal %>),
+  .i_hw_write_enable  ('0),
+  .i_hw_write_data    ('0),
+  .i_hw_set           ('0),
+  .i_hw_clear         ('0),
+  .i_value            ('0),
+  .i_mask             ('1),
+  .o_value            (<%= value_out[loop_variables] %>),
+  .o_value_unmasked   ()
 );

data/lib/rggen/systemverilog/rtl/bit_field/type/rws.erb

@@ -1,11 +1,17 @@
-rggen_bit_field_rws #(
+rggen_bit_field #(
   .WIDTH          (<%= width %>),
   .INITIAL_VALUE  (<%= initial_value %>)
 ) u_bit_field (
-  .i_clk        (<%= clock %>),
-  .i_rst_n      (<%= reset %>),
-  .bit_field_if (<%= bit_field_if %>),
-  .i_set        (<%= set_signal %>),
-  .i_value      (<%= value_in[loop_variables] %>),
-  .o_value      (<%= value_out[loop_variables] %>)
+  .i_clk              (<%= clock %>),
+  .i_rst_n            (<%= reset %>),
+  .bit_field_if       (<%= bit_field_if %>),
+  .i_sw_write_enable  ('1),
+  .i_hw_write_enable  (<%= set_signal %>),
+  .i_hw_write_data    (<%= value_in[loop_variables] %>),
+  .i_hw_set           ('0),
+  .i_hw_clear         ('0),
+  .i_value            ('0),
+  .i_mask             ('1),
+  .o_value            (<%= value_out[loop_variables] %>),
+  .o_value_unmasked   ()
 );

data/lib/rggen/systemverilog/rtl/bit_field/type/w0crs_w0src_w1crs_w1src_wcrs_wsrc.erb

@@ -0,0 +1,19 @@
+rggen_bit_field #(
+  .WIDTH            (<%= width %>),
+  .INITIAL_VALUE    (<%= initial_value %>),
+  .SW_READ_ACTION   (<%= read_action %>),
+  .SW_WRITE_ACTION  (<%= write_action %>)
+) u_bit_field (
+  .i_clk              (<%= clock %>),
+  .i_rst_n            (<%= reset %>),
+  .bit_field_if       (<%= bit_field_if %>),
+  .i_sw_write_enable  ('1),
+  .i_hw_write_enable  ('0),
+  .i_hw_write_data    ('0),
+  .i_hw_set           ('0),
+  .i_hw_clear         ('0),
+  .i_value            ('0),
+  .i_mask             ('1),
+  .o_value            (<%= value_out[loop_variables] %>),
+  .o_value_unmasked   ()
+);

data/lib/rggen/systemverilog/rtl/bit_field/type/w0crs_w0src_w1crs_w1src_wcrs_wsrc.rb

@@ -0,0 +1,37 @@
+# frozen_string_literal: true
+
+RgGen.define_list_item_feature(
+  :bit_field, :type, [:w0crs, :w0src, :w1crs, :w1src, :wcrs, :wsrc]
+) do
+  sv_rtl do
+    build do
+      output :value_out, {
+        name: "o_#{full_name}", data_type: :logic, width: width,
+        array_size: array_size, array_format: array_port_format
+      }
+    end
+
+    main_code :bit_field, from_template: true
+
+    private
+
+    def read_action
+      read_set? && 'RGGEN_READ_SET' || 'RGGEN_READ_CLEAR'
+    end
+
+    def read_set?
+      [:w0crs, :w1crs, :wcrs].include?(bit_field.type)
+    end
+
+    def write_action
+      {
+        w0crs: 'RGGEN_WRITE_0_CLEAR',
+        w0src: 'RGGEN_WRITE_0_SET',
+        w1crs: 'RGGEN_WRITE_1_CLEAR',
+        w1src: 'RGGEN_WRITE_1_SET',
+        wcrs: 'RGGEN_WRITE_CLEAR',
+        wsrc: 'RGGEN_WRITE_SET'
+      }[bit_field.type]
+    end
+  end
+end

data/lib/rggen/systemverilog/rtl/bit_field/type/w0t_w1t.erb

@@ -0,0 +1,18 @@
+rggen_bit_field #(
+  .WIDTH            (<%= width %>),
+  .INITIAL_VALUE    (<%= initial_value %>),
+  .SW_WRITE_ACTION  (<%= write_action %>)
+) u_bit_field (
+  .i_clk              (<%= clock %>),
+  .i_rst_n            (<%= reset %>),
+  .bit_field_if       (<%= bit_field_if %>),
+  .i_sw_write_enable  ('1),
+  .i_hw_write_enable  ('0),
+  .i_hw_write_data    ('0),
+  .i_hw_set           ('0),
+  .i_hw_clear         ('0),
+  .i_value            ('0),
+  .i_mask             ('1),
+  .o_value            (<%= value_out[loop_variables] %>),
+  .o_value_unmasked   ()
+);

data/lib/rggen/systemverilog/rtl/bit_field/type/{w0src_w1src.rb → w0t_w1t.rb}

@@ -1,6 +1,6 @@
 # frozen_string_literal: true
 
-RgGen.define_list_item_feature(:bit_field, :type, [:w0src, :w1src]) do
+RgGen.define_list_item_feature(:bit_field, :type, [:w0t, :w1t]) do
   sv_rtl do
     build do
       output :value_out, {
@@ -13,9 +13,11 @@ RgGen.define_list_item_feature(:bit_field, :type, [:w0src, :w1src]) do
 
     private
 
-    def set_value
-      value = (bit_field.type == :w0src && 0) || 1
-      bin(value, 1)
+    def write_action
+      {
+        w0t: 'RGGEN_WRITE_0_TOGGLE',
+        w1t: 'RGGEN_WRITE_1_TOGGLE'
+      }[bit_field.type]
     end
   end
 end