rggen-systemverilog 0.21.0 → 0.24.0

This diff represents the content of publicly available package versions that have been released to one of the supported registries. The information contained in this diff is provided for informational purposes only and reflects changes between package versions as they appear in their respective public registries.
Files changed (50) hide show
  1. checksums.yaml +4 -4
  2. data/LICENSE +1 -1
  3. data/README.md +2 -2
  4. data/lib/rggen/systemverilog/common.rb +0 -22
  5. data/lib/rggen/systemverilog/common/feature.rb +2 -2
  6. data/lib/rggen/systemverilog/common/utility.rb +4 -0
  7. data/lib/rggen/systemverilog/common/utility/identifier.rb +19 -15
  8. data/lib/rggen/systemverilog/ral.rb +20 -26
  9. data/lib/rggen/systemverilog/ral/bit_field/type.rb +1 -1
  10. data/lib/rggen/systemverilog/ral/setup.rb +1 -1
  11. data/lib/rggen/systemverilog/rtl.rb +39 -41
  12. data/lib/rggen/systemverilog/rtl/bit_field/sv_rtl_top.rb +10 -46
  13. data/lib/rggen/systemverilog/rtl/bit_field/type.rb +1 -2
  14. data/lib/rggen/systemverilog/rtl/bit_field/type/rc_w0c_w1c_wc_woc.erb +19 -0
  15. data/lib/rggen/systemverilog/rtl/bit_field/type/{rc_w0c_w1c.rb → rc_w0c_w1c_wc_woc.rb} +22 -11
  16. data/lib/rggen/systemverilog/rtl/bit_field/type/reserved.erb +17 -2
  17. data/lib/rggen/systemverilog/rtl/bit_field/type/ro.erb +15 -4
  18. data/lib/rggen/systemverilog/rtl/bit_field/type/rof.erb +15 -4
  19. data/lib/rggen/systemverilog/rtl/bit_field/type/rs_w0s_w1s_ws_wos.erb +19 -0
  20. data/lib/rggen/systemverilog/rtl/bit_field/type/{rs_w0s_w1s.rb → rs_w0s_w1s_ws_wos.rb} +21 -9
  21. data/lib/rggen/systemverilog/rtl/bit_field/type/rw_w1_wo_wo1.erb +15 -7
  22. data/lib/rggen/systemverilog/rtl/bit_field/type/rw_w1_wo_wo1.rb +2 -2
  23. data/lib/rggen/systemverilog/rtl/bit_field/type/rwc.erb +15 -7
  24. data/lib/rggen/systemverilog/rtl/bit_field/type/rwe.erb +16 -8
  25. data/lib/rggen/systemverilog/rtl/bit_field/type/rwl.erb +16 -8
  26. data/lib/rggen/systemverilog/rtl/bit_field/type/rws.erb +13 -7
  27. data/lib/rggen/systemverilog/rtl/bit_field/type/w0crs_w0src_w1crs_w1src_wcrs_wsrc.erb +19 -0
  28. data/lib/rggen/systemverilog/rtl/bit_field/type/w0crs_w0src_w1crs_w1src_wcrs_wsrc.rb +37 -0
  29. data/lib/rggen/systemverilog/rtl/bit_field/type/w0t_w1t.erb +18 -0
  30. data/lib/rggen/systemverilog/rtl/bit_field/type/{w0src_w1src.rb → w0t_w1t.rb} +6 -4
  31. data/lib/rggen/systemverilog/rtl/bit_field/type/wrc_wrs.erb +18 -0
  32. data/lib/rggen/systemverilog/rtl/bit_field/type/{w0crs_w1crs.rb → wrc_wrs.rb} +6 -4
  33. data/lib/rggen/systemverilog/rtl/bit_field_index.rb +53 -0
  34. data/lib/rggen/systemverilog/rtl/indirect_index.rb +35 -0
  35. data/lib/rggen/systemverilog/rtl/register/type.rb +1 -56
  36. data/lib/rggen/systemverilog/rtl/register/type/external.rb +0 -4
  37. data/lib/rggen/systemverilog/rtl/register/type/indirect.rb +2 -26
  38. data/lib/rggen/systemverilog/rtl/register_block/protocol.rb +14 -8
  39. data/lib/rggen/systemverilog/rtl/register_block/protocol/axi4lite.erb +1 -0
  40. data/lib/rggen/systemverilog/rtl/register_block/protocol/axi4lite.rb +55 -28
  41. data/lib/rggen/systemverilog/rtl/register_block/sv_rtl_top.rb +1 -1
  42. data/lib/rggen/systemverilog/rtl/register_index.rb +4 -4
  43. data/lib/rggen/systemverilog/rtl/register_type.rb +68 -0
  44. data/lib/rggen/systemverilog/rtl/setup.rb +1 -1
  45. data/lib/rggen/systemverilog/version.rb +1 -1
  46. metadata +17 -26
  47. data/lib/rggen/systemverilog/rtl/bit_field/type/rc_w0c_w1c.erb +0 -15
  48. data/lib/rggen/systemverilog/rtl/bit_field/type/rs_w0s_w1s.erb +0 -13
  49. data/lib/rggen/systemverilog/rtl/bit_field/type/w0crs_w1crs.erb +0 -10
  50. data/lib/rggen/systemverilog/rtl/bit_field/type/w0src_w1src.erb +0 -10
@@ -0,0 +1,18 @@
1
+ rggen_bit_field #(
2
+ .WIDTH (<%= width %>),
3
+ .INITIAL_VALUE (<%= initial_value %>),
4
+ .SW_READ_ACTION (<%= read_action %>)
5
+ ) u_bit_field (
6
+ .i_clk (<%= clock %>),
7
+ .i_rst_n (<%= reset %>),
8
+ .bit_field_if (<%= bit_field_if %>),
9
+ .i_sw_write_enable ('1),
10
+ .i_hw_write_enable ('0),
11
+ .i_hw_write_data ('0),
12
+ .i_hw_set ('0),
13
+ .i_hw_clear ('0),
14
+ .i_value ('0),
15
+ .i_mask ('1),
16
+ .o_value (<%= value_out[loop_variables] %>),
17
+ .o_value_unmasked ()
18
+ );
@@ -1,6 +1,6 @@
1
1
  # frozen_string_literal: true
2
2
 
3
- RgGen.define_list_item_feature(:bit_field, :type, [:w0crs, :w1crs]) do
3
+ RgGen.define_list_item_feature(:bit_field, :type, [:wrc, :wrs]) do
4
4
  sv_rtl do
5
5
  build do
6
6
  output :value_out, {
@@ -13,9 +13,11 @@ RgGen.define_list_item_feature(:bit_field, :type, [:w0crs, :w1crs]) do
13
13
 
14
14
  private
15
15
 
16
- def clear_value
17
- value = (bit_field.type == :w0crs && 0) || 1
18
- bin(value, 1)
16
+ def read_action
17
+ {
18
+ wrc: 'RGGEN_READ_CLEAR',
19
+ wrs: 'RGGEN_READ_SET'
20
+ }[bit_field.type]
19
21
  end
20
22
  end
21
23
  end
@@ -0,0 +1,53 @@
1
+ # frozen_string_literal: true
2
+
3
+ module RgGen
4
+ module SystemVerilog
5
+ module RTL
6
+ module BitFieldIndex
7
+ EXPORTED_METHODS = [
8
+ :local_index, :local_indices, :loop_variables, :array_size
9
+ ].freeze
10
+
11
+ def self.included(feature)
12
+ feature.module_eval do
13
+ EXPORTED_METHODS.each { |m| export m }
14
+ end
15
+ end
16
+
17
+ def local_index
18
+ index_name = local_index_name
19
+ index_name && create_identifier(index_name)
20
+ end
21
+
22
+ def local_indices
23
+ [*register.local_indices, local_index_name]
24
+ end
25
+
26
+ def loop_variables
27
+ (inside_loop? || nil) &&
28
+ [*register.loop_variables, local_index].compact
29
+ end
30
+
31
+ def array_size
32
+ (inside_loop? || nil) &&
33
+ [
34
+ *register_files.flat_map(&:array_size),
35
+ *register.array_size,
36
+ *bit_field.sequence_size
37
+ ].compact
38
+ end
39
+
40
+ private
41
+
42
+ def local_index_name
43
+ (bit_field.sequential? || nil) &&
44
+ loop_index((register.loop_variables&.size || 0) + 1)
45
+ end
46
+
47
+ def inside_loop?
48
+ register.inside_loop? || bit_field.sequential?
49
+ end
50
+ end
51
+ end
52
+ end
53
+ end
@@ -0,0 +1,35 @@
1
+ # frozen_string_literal: true
2
+
3
+ module RgGen
4
+ module SystemVerilog
5
+ module RTL
6
+ module IndirectIndex
7
+ private
8
+
9
+ def index_fields
10
+ @index_fields ||=
11
+ register.collect_index_fields(register_block.bit_fields)
12
+ end
13
+
14
+ def index_width
15
+ @index_width ||= index_fields.sum(&:width)
16
+ end
17
+
18
+ def index_values
19
+ loop_variables = register.local_loop_variables
20
+ register.index_entries.zip(index_fields).map do |entry, field|
21
+ if entry.array_index?
22
+ loop_variables.shift[0, field.width]
23
+ else
24
+ hex(entry.value, field.width)
25
+ end
26
+ end
27
+ end
28
+
29
+ def indirect_index_assignment
30
+ assign(indirect_index, concat(index_fields.map(&:value)))
31
+ end
32
+ end
33
+ end
34
+ end
35
+ end
@@ -3,65 +3,10 @@
3
3
  RgGen.define_list_feature(:register, :type) do
4
4
  sv_rtl do
5
5
  base_feature do
6
- include RgGen::SystemVerilog::RTL::PartialSum
6
+ include RgGen::SystemVerilog::RTL::RegisterType
7
7
 
8
8
  private
9
9
 
10
- def readable
11
- register.readable? && 1 || 0
12
- end
13
-
14
- def writable
15
- register.writable? && 1 || 0
16
- end
17
-
18
- def bus_width
19
- configuration.bus_width
20
- end
21
-
22
- def address_width
23
- register_block.local_address_width
24
- end
25
-
26
- def offset_address
27
- offsets = [*register_files, register].flat_map(&method(:collect_offsets))
28
- offsets = partial_sums(offsets)
29
- format_offsets(offsets)
30
- end
31
-
32
- def collect_offsets(component)
33
- if component.register_file? && component.array?
34
- [component.offset_address, byte_offset(component)]
35
- else
36
- component.offset_address
37
- end
38
- end
39
-
40
- def byte_offset(component)
41
- "#{component.byte_size(false)}*(#{component.local_index})"
42
- end
43
-
44
- def format_offsets(offsets)
45
- offsets.map(&method(:format_offset)).join('+')
46
- end
47
-
48
- def format_offset(offset)
49
- offset.is_a?(Integer) ? hex(offset, address_width) : offset
50
- end
51
-
52
- def width
53
- register.width
54
- end
55
-
56
- def valid_bits
57
- bits = register.bit_fields.map(&:bit_map).inject(:|)
58
- hex(bits, register.width)
59
- end
60
-
61
- def register_index
62
- register.local_index || 0
63
- end
64
-
65
10
  def register_if
66
11
  register_block.register_if[register.index]
67
12
  end
@@ -71,10 +71,6 @@ RgGen.define_list_item_feature(:register, :type, :external) do
71
71
 
72
72
  private
73
73
 
74
- def address_width
75
- register_block.local_address_width
76
- end
77
-
78
74
  def byte_width
79
75
  configuration.byte_width
80
76
  end
@@ -2,6 +2,8 @@
2
2
 
3
3
  RgGen.define_list_item_feature(:register, :type, :indirect) do
4
4
  sv_rtl do
5
+ include RgGen::SystemVerilog::RTL::IndirectIndex
6
+
5
7
  build do
6
8
  logic :indirect_index, { width: index_width }
7
9
  end
@@ -10,31 +12,5 @@ RgGen.define_list_item_feature(:register, :type, :indirect) do
10
12
  code << indirect_index_assignment << nl
11
13
  code << process_template
12
14
  end
13
-
14
- private
15
-
16
- def index_fields
17
- @index_fields ||=
18
- register.collect_index_fields(register_block.bit_fields)
19
- end
20
-
21
- def index_width
22
- @index_width ||= index_fields.map(&:width).sum
23
- end
24
-
25
- def index_values
26
- loop_variables = register.local_loop_variables
27
- register.index_entries.zip(index_fields).map do |entry, field|
28
- if entry.array_index?
29
- loop_variables.shift[0, field.width]
30
- else
31
- hex(entry.value, field.width)
32
- end
33
- end
34
- end
35
-
36
- def indirect_index_assignment
37
- assign(indirect_index, concat(index_fields.map(&:value)))
38
- end
39
15
  end
40
16
  end
@@ -2,19 +2,25 @@
2
2
 
3
3
  RgGen.define_list_feature(:register_block, :protocol) do
4
4
  shared_context do
5
- def feature_registry(registry = nil)
6
- @registry = registry if registry
7
- @registry
5
+ def feature_registry(registry)
6
+ feature_registries << registry
8
7
  end
9
8
 
10
9
  def available_protocols
11
- feature_registry
12
- .enabled_features(:protocol)
13
- .select(&method(:valid_protocol?))
10
+ feature_registries
11
+ .map(&method(:collect_available_protocols)).inject(:&)
14
12
  end
15
13
 
16
- def valid_protocol?(protocol)
17
- feature_registry.feature?(:protocol, protocol)
14
+ private
15
+
16
+ def feature_registries
17
+ @feature_registries ||= []
18
+ end
19
+
20
+ def collect_available_protocols(registry)
21
+ registry
22
+ .enabled_features(:protocol)
23
+ .select { |protocol| registry.feature?(:protocol, protocol) }
18
24
  end
19
25
  end
20
26
 
@@ -1,4 +1,5 @@
1
1
  rggen_axi4lite_adapter #(
2
+ .ID_WIDTH (<%= id_width %>),
2
3
  .ADDRESS_WIDTH (<%= address_width %>),
3
4
  .LOCAL_ADDRESS_WIDTH (<%= local_address_width %>),
4
5
  .BUS_WIDTH (<%= bus_width %>),
@@ -13,6 +13,9 @@ RgGen.define_list_item_feature(:register_block, :protocol, :axi4lite) do
13
13
 
14
14
  sv_rtl do
15
15
  build do
16
+ parameter :id_width, {
17
+ name: 'ID_WIDTH', data_type: :int, default: 0
18
+ }
16
19
  parameter :write_first, {
17
20
  name: 'WRITE_FIRST', data_type: :bit, default: 1
18
21
  }
@@ -28,6 +31,9 @@ RgGen.define_list_item_feature(:register_block, :protocol, :axi4lite) do
28
31
  output :awready, {
29
32
  name: 'o_awready', data_type: :logic, width: 1
30
33
  }
34
+ input :awid, {
35
+ name: 'i_awid', data_type: :logic, width: id_port_width
36
+ }
31
37
  input :awaddr, {
32
38
  name: 'i_awaddr', data_type: :logic, width: address_width
33
39
  }
@@ -49,6 +55,9 @@ RgGen.define_list_item_feature(:register_block, :protocol, :axi4lite) do
49
55
  output :bvalid, {
50
56
  name: 'o_bvalid', data_type: :logic, width: 1
51
57
  }
58
+ output :bid, {
59
+ name: 'o_bid', data_type: :logic, width: id_port_width
60
+ }
52
61
  input :bready, {
53
62
  name: 'i_bready', data_type: :logic, width: 1
54
63
  }
@@ -61,6 +70,9 @@ RgGen.define_list_item_feature(:register_block, :protocol, :axi4lite) do
61
70
  output :arready, {
62
71
  name: 'o_arready', data_type: :logic, width: 1
63
72
  }
73
+ input :arid, {
74
+ name: 'i_arid', data_type: :logic, width: id_port_width
75
+ }
64
76
  input :araddr, {
65
77
  name: 'i_araddr', data_type: :logic, width: address_width
66
78
  }
@@ -73,6 +85,9 @@ RgGen.define_list_item_feature(:register_block, :protocol, :axi4lite) do
73
85
  input :rready, {
74
86
  name: 'i_rready', data_type: :logic, width: 1
75
87
  }
88
+ output :rid, {
89
+ name: 'o_rid', data_type: :logic, width: id_port_width
90
+ }
76
91
  output :rdata, {
77
92
  name: 'o_rdata', data_type: :logic, width: bus_width
78
93
  }
@@ -81,13 +96,13 @@ RgGen.define_list_item_feature(:register_block, :protocol, :axi4lite) do
81
96
  }
82
97
  interface :axi4lite_if, {
83
98
  name: 'axi4lite_if', interface_type: 'rggen_axi4lite_if',
84
- parameter_values: [address_width, bus_width],
99
+ parameter_values: [id_width, address_width, bus_width],
85
100
  variables: [
86
- 'awvalid', 'awready', 'awaddr', 'awprot',
101
+ 'awvalid', 'awready', 'awid', 'awaddr', 'awprot',
87
102
  'wvalid', 'wready', 'wdata', 'wstrb',
88
- 'bvalid', 'bready', 'bresp',
89
- 'arvalid', 'arready', 'araddr', 'arprot',
90
- 'rvalid', 'rready', 'rdata', 'rresp'
103
+ 'bvalid', 'bready', 'bid', 'bresp',
104
+ 'arvalid', 'arready', 'arid', 'araddr', 'arprot',
105
+ 'rvalid', 'rready', 'rid', 'rdata', 'rresp'
91
106
  ]
92
107
  }
93
108
  end
@@ -95,29 +110,41 @@ RgGen.define_list_item_feature(:register_block, :protocol, :axi4lite) do
95
110
 
96
111
  main_code :register_block, from_template: true
97
112
  main_code :register_block do |code|
98
- unless configuration.fold_sv_interface_port?
99
- [
100
- [axi4lite_if.awvalid, awvalid],
101
- [awready, axi4lite_if.awready],
102
- [axi4lite_if.awaddr, awaddr],
103
- [axi4lite_if.awprot, awprot],
104
- [axi4lite_if.wvalid, wvalid],
105
- [wready, axi4lite_if.wready],
106
- [axi4lite_if.wdata, wdata],
107
- [axi4lite_if.wstrb, wstrb],
108
- [bvalid, axi4lite_if.bvalid],
109
- [axi4lite_if.bready, bready],
110
- [bresp, axi4lite_if.bresp],
111
- [axi4lite_if.arvalid, arvalid],
112
- [arready, axi4lite_if.arready],
113
- [axi4lite_if.araddr, araddr],
114
- [axi4lite_if.arprot, arprot],
115
- [rvalid, axi4lite_if.rvalid],
116
- [axi4lite_if.rready, rready],
117
- [rdata, axi4lite_if.rdata],
118
- [rresp, axi4lite_if.rresp]
119
- ].each { |lhs, rhs| code << assign(lhs, rhs) << nl }
120
- end
113
+ configuration.fold_sv_interface_port? || assign_axi4lite_signals(code)
114
+ end
115
+
116
+ private
117
+
118
+ def id_port_width
119
+ "((#{id_width}>0)?#{id_width}:1)"
120
+ end
121
+
122
+ def assign_axi4lite_signals(code)
123
+ [
124
+ [axi4lite_if.awvalid, awvalid],
125
+ [awready, axi4lite_if.awready],
126
+ [axi4lite_if.awid, awid],
127
+ [axi4lite_if.awaddr, awaddr],
128
+ [axi4lite_if.awprot, awprot],
129
+ [axi4lite_if.wvalid, wvalid],
130
+ [wready, axi4lite_if.wready],
131
+ [axi4lite_if.wdata, wdata],
132
+ [axi4lite_if.wstrb, wstrb],
133
+ [bvalid, axi4lite_if.bvalid],
134
+ [axi4lite_if.bready, bready],
135
+ [bid, axi4lite_if.bid],
136
+ [bresp, axi4lite_if.bresp],
137
+ [axi4lite_if.arvalid, arvalid],
138
+ [arready, axi4lite_if.arready],
139
+ [axi4lite_if.arid, arid],
140
+ [axi4lite_if.araddr, araddr],
141
+ [axi4lite_if.arprot, arprot],
142
+ [rvalid, axi4lite_if.rvalid],
143
+ [axi4lite_if.rready, rready],
144
+ [rid, axi4lite_if.rid],
145
+ [rdata, axi4lite_if.rdata],
146
+ [rresp, axi4lite_if.rresp]
147
+ ].each { |lhs, rhs| code << assign(lhs, rhs) << nl }
121
148
  end
122
149
  end
123
150
  end
@@ -23,7 +23,7 @@ RgGen.define_simple_feature(:register_block, :sv_rtl_top) do
23
23
  end
24
24
 
25
25
  def total_registers
26
- register_block.files_and_registers.map(&:count).sum
26
+ register_block.files_and_registers.sum(&:count)
27
27
  end
28
28
 
29
29
  private
@@ -9,7 +9,7 @@ module RgGen
9
9
  EXPORTED_METHODS = [
10
10
  :loop_variables, :local_loop_variables,
11
11
  :local_index, :local_indices,
12
- :index, :inside_roop?
12
+ :index, :inside_loop?
13
13
  ].freeze
14
14
 
15
15
  def self.included(feature)
@@ -23,7 +23,7 @@ module RgGen
23
23
  end
24
24
 
25
25
  def loop_variables
26
- (inside_roop? || nil) &&
26
+ (inside_loop? || nil) &&
27
27
  [*upper_register_file&.loop_variables, *local_loop_variables]
28
28
  end
29
29
 
@@ -59,8 +59,8 @@ module RgGen
59
59
  end
60
60
  end
61
61
 
62
- def inside_roop?
63
- component.array? || upper_register_file&.inside_roop? || false
62
+ def inside_loop?
63
+ component.array? || upper_register_file&.inside_loop? || false
64
64
  end
65
65
 
66
66
  private