rggen-systemverilog 0.21.0 → 0.24.0

data/lib/rggen/systemverilog/rtl/bit_field/type/wrc_wrs.erb

@@ -0,0 +1,18 @@
+rggen_bit_field #(
+  .WIDTH          (<%= width %>),
+  .INITIAL_VALUE  (<%= initial_value %>),
+  .SW_READ_ACTION (<%= read_action %>)
+) u_bit_field (
+  .i_clk              (<%= clock %>),
+  .i_rst_n            (<%= reset %>),
+  .bit_field_if       (<%= bit_field_if %>),
+  .i_sw_write_enable  ('1),
+  .i_hw_write_enable  ('0),
+  .i_hw_write_data    ('0),
+  .i_hw_set           ('0),
+  .i_hw_clear         ('0),
+  .i_value            ('0),
+  .i_mask             ('1),
+  .o_value            (<%= value_out[loop_variables] %>),
+  .o_value_unmasked   ()
+);

data/lib/rggen/systemverilog/rtl/bit_field/type/{w0crs_w1crs.rb → wrc_wrs.rb}

@@ -1,6 +1,6 @@
 # frozen_string_literal: true
 
-RgGen.define_list_item_feature(:bit_field, :type, [:w0crs, :w1crs]) do
+RgGen.define_list_item_feature(:bit_field, :type, [:wrc, :wrs]) do
   sv_rtl do
     build do
       output :value_out, {
@@ -13,9 +13,11 @@ RgGen.define_list_item_feature(:bit_field, :type, [:w0crs, :w1crs]) do
 
     private
 
-    def clear_value
-      value = (bit_field.type == :w0crs && 0) || 1
-      bin(value, 1)
+    def read_action
+      {
+        wrc: 'RGGEN_READ_CLEAR',
+        wrs: 'RGGEN_READ_SET'
+      }[bit_field.type]
     end
   end
 end

data/lib/rggen/systemverilog/rtl/bit_field_index.rb

@@ -0,0 +1,53 @@
+# frozen_string_literal: true
+
+module RgGen
+  module SystemVerilog
+    module RTL
+      module BitFieldIndex
+        EXPORTED_METHODS = [
+          :local_index, :local_indices, :loop_variables, :array_size
+        ].freeze
+
+        def self.included(feature)
+          feature.module_eval do
+            EXPORTED_METHODS.each { |m| export m }
+          end
+        end
+
+        def local_index
+          index_name = local_index_name
+          index_name && create_identifier(index_name)
+        end
+
+        def local_indices
+          [*register.local_indices, local_index_name]
+        end
+
+        def loop_variables
+          (inside_loop? || nil) &&
+            [*register.loop_variables, local_index].compact
+        end
+
+        def array_size
+          (inside_loop? || nil) &&
+            [
+              *register_files.flat_map(&:array_size),
+              *register.array_size,
+              *bit_field.sequence_size
+            ].compact
+        end
+
+        private
+
+        def local_index_name
+          (bit_field.sequential? || nil) &&
+            loop_index((register.loop_variables&.size || 0) + 1)
+        end
+
+        def inside_loop?
+          register.inside_loop? || bit_field.sequential?
+        end
+      end
+    end
+  end
+end

data/lib/rggen/systemverilog/rtl/indirect_index.rb

@@ -0,0 +1,35 @@
+# frozen_string_literal: true
+
+module RgGen
+  module SystemVerilog
+    module RTL
+      module IndirectIndex
+        private
+
+        def index_fields
+          @index_fields ||=
+            register.collect_index_fields(register_block.bit_fields)
+        end
+
+        def index_width
+          @index_width ||= index_fields.sum(&:width)
+        end
+
+        def index_values
+          loop_variables = register.local_loop_variables
+          register.index_entries.zip(index_fields).map do |entry, field|
+            if entry.array_index?
+              loop_variables.shift[0, field.width]
+            else
+              hex(entry.value, field.width)
+            end
+          end
+        end
+
+        def indirect_index_assignment
+          assign(indirect_index, concat(index_fields.map(&:value)))
+        end
+      end
+    end
+  end
+end

data/lib/rggen/systemverilog/rtl/register/type.rb

@@ -3,65 +3,10 @@
 RgGen.define_list_feature(:register, :type) do
   sv_rtl do
     base_feature do
-      include RgGen::SystemVerilog::RTL::PartialSum
+      include RgGen::SystemVerilog::RTL::RegisterType
 
       private
 
-      def readable
-        register.readable? && 1 || 0
-      end
-
-      def writable
-        register.writable? && 1 || 0
-      end
-
-      def bus_width
-        configuration.bus_width
-      end
-
-      def address_width
-        register_block.local_address_width
-      end
-
-      def offset_address
-        offsets = [*register_files, register].flat_map(&method(:collect_offsets))
-        offsets = partial_sums(offsets)
-        format_offsets(offsets)
-      end
-
-      def collect_offsets(component)
-        if component.register_file? && component.array?
-          [component.offset_address, byte_offset(component)]
-        else
-          component.offset_address
-        end
-      end
-
-      def byte_offset(component)
-        "#{component.byte_size(false)}*(#{component.local_index})"
-      end
-
-      def format_offsets(offsets)
-        offsets.map(&method(:format_offset)).join('+')
-      end
-
-      def format_offset(offset)
-        offset.is_a?(Integer) ? hex(offset, address_width) : offset
-      end
-
-      def width
-        register.width
-      end
-
-      def valid_bits
-        bits = register.bit_fields.map(&:bit_map).inject(:|)
-        hex(bits, register.width)
-      end
-
-      def register_index
-        register.local_index || 0
-      end
-
       def register_if
         register_block.register_if[register.index]
       end

data/lib/rggen/systemverilog/rtl/register/type/external.rb

@@ -71,10 +71,6 @@ RgGen.define_list_item_feature(:register, :type, :external) do
 
     private
 
-    def address_width
-      register_block.local_address_width
-    end
-
     def byte_width
       configuration.byte_width
     end

data/lib/rggen/systemverilog/rtl/register/type/indirect.rb

@@ -2,6 +2,8 @@
 
 RgGen.define_list_item_feature(:register, :type, :indirect) do
   sv_rtl do
+    include RgGen::SystemVerilog::RTL::IndirectIndex
+
     build do
       logic :indirect_index, { width: index_width }
     end
@@ -10,31 +12,5 @@ RgGen.define_list_item_feature(:register, :type, :indirect) do
       code << indirect_index_assignment << nl
       code << process_template
     end
-
-    private
-
-    def index_fields
-      @index_fields ||=
-        register.collect_index_fields(register_block.bit_fields)
-    end
-
-    def index_width
-      @index_width ||= index_fields.map(&:width).sum
-    end
-
-    def index_values
-      loop_variables = register.local_loop_variables
-      register.index_entries.zip(index_fields).map do |entry, field|
-        if entry.array_index?
-          loop_variables.shift[0, field.width]
-        else
-          hex(entry.value, field.width)
-        end
-      end
-    end
-
-    def indirect_index_assignment
-      assign(indirect_index, concat(index_fields.map(&:value)))
-    end
   end
 end

data/lib/rggen/systemverilog/rtl/register_block/protocol.rb

@@ -2,19 +2,25 @@
 
 RgGen.define_list_feature(:register_block, :protocol) do
   shared_context do
-    def feature_registry(registry = nil)
-      @registry = registry if registry
-      @registry
+    def feature_registry(registry)
+      feature_registries << registry
     end
 
     def available_protocols
-      feature_registry
-        .enabled_features(:protocol)
-        .select(&method(:valid_protocol?))
+      feature_registries
+        .map(&method(:collect_available_protocols)).inject(:&)
     end
 
-    def valid_protocol?(protocol)
-      feature_registry.feature?(:protocol, protocol)
+    private
+
+    def feature_registries
+      @feature_registries ||= []
+    end
+
+    def collect_available_protocols(registry)
+      registry
+        .enabled_features(:protocol)
+        .select { |protocol| registry.feature?(:protocol, protocol) }
     end
   end
 

data/lib/rggen/systemverilog/rtl/register_block/protocol/axi4lite.erb

@@ -1,4 +1,5 @@
 rggen_axi4lite_adapter #(
+  .ID_WIDTH             (<%= id_width %>),
   .ADDRESS_WIDTH        (<%= address_width %>),
   .LOCAL_ADDRESS_WIDTH  (<%= local_address_width %>),
   .BUS_WIDTH            (<%= bus_width %>),

data/lib/rggen/systemverilog/rtl/register_block/protocol/axi4lite.rb

@@ -13,6 +13,9 @@ RgGen.define_list_item_feature(:register_block, :protocol, :axi4lite) do
 
   sv_rtl do
     build do
+      parameter :id_width, {
+        name: 'ID_WIDTH', data_type: :int, default: 0
+      }
       parameter :write_first, {
         name: 'WRITE_FIRST', data_type: :bit, default: 1
       }
@@ -28,6 +31,9 @@ RgGen.define_list_item_feature(:register_block, :protocol, :axi4lite) do
         output :awready, {
           name: 'o_awready', data_type: :logic, width: 1
         }
+        input :awid, {
+          name: 'i_awid', data_type: :logic, width: id_port_width
+        }
         input :awaddr, {
           name: 'i_awaddr', data_type: :logic, width: address_width
         }
@@ -49,6 +55,9 @@ RgGen.define_list_item_feature(:register_block, :protocol, :axi4lite) do
         output :bvalid, {
           name: 'o_bvalid', data_type: :logic, width: 1
         }
+        output :bid, {
+          name: 'o_bid', data_type: :logic, width: id_port_width
+        }
         input :bready, {
           name: 'i_bready', data_type: :logic, width: 1
         }
@@ -61,6 +70,9 @@ RgGen.define_list_item_feature(:register_block, :protocol, :axi4lite) do
         output :arready, {
           name: 'o_arready', data_type: :logic, width: 1
         }
+        input :arid, {
+          name: 'i_arid', data_type: :logic, width: id_port_width
+        }
         input :araddr, {
           name: 'i_araddr', data_type: :logic, width: address_width
         }
@@ -73,6 +85,9 @@ RgGen.define_list_item_feature(:register_block, :protocol, :axi4lite) do
         input :rready, {
           name: 'i_rready', data_type: :logic, width: 1
         }
+        output :rid, {
+          name: 'o_rid', data_type: :logic, width: id_port_width
+        }
         output :rdata, {
           name: 'o_rdata', data_type: :logic, width: bus_width
         }
@@ -81,13 +96,13 @@ RgGen.define_list_item_feature(:register_block, :protocol, :axi4lite) do
         }
         interface :axi4lite_if, {
           name: 'axi4lite_if', interface_type: 'rggen_axi4lite_if',
-          parameter_values: [address_width, bus_width],
+          parameter_values: [id_width, address_width, bus_width],
           variables: [
-            'awvalid', 'awready', 'awaddr', 'awprot',
+            'awvalid', 'awready', 'awid', 'awaddr', 'awprot',
             'wvalid', 'wready', 'wdata', 'wstrb',
-            'bvalid', 'bready', 'bresp',
-            'arvalid', 'arready', 'araddr', 'arprot',
-            'rvalid', 'rready', 'rdata', 'rresp'
+            'bvalid', 'bready', 'bid', 'bresp',
+            'arvalid', 'arready', 'arid', 'araddr', 'arprot',
+            'rvalid', 'rready', 'rid', 'rdata', 'rresp'
           ]
         }
       end
@@ -95,29 +110,41 @@ RgGen.define_list_item_feature(:register_block, :protocol, :axi4lite) do
 
     main_code :register_block, from_template: true
     main_code :register_block do |code|
-      unless configuration.fold_sv_interface_port?
-        [
-          [axi4lite_if.awvalid, awvalid],
-          [awready, axi4lite_if.awready],
-          [axi4lite_if.awaddr, awaddr],
-          [axi4lite_if.awprot, awprot],
-          [axi4lite_if.wvalid, wvalid],
-          [wready, axi4lite_if.wready],
-          [axi4lite_if.wdata, wdata],
-          [axi4lite_if.wstrb, wstrb],
-          [bvalid, axi4lite_if.bvalid],
-          [axi4lite_if.bready, bready],
-          [bresp, axi4lite_if.bresp],
-          [axi4lite_if.arvalid, arvalid],
-          [arready, axi4lite_if.arready],
-          [axi4lite_if.araddr, araddr],
-          [axi4lite_if.arprot, arprot],
-          [rvalid, axi4lite_if.rvalid],
-          [axi4lite_if.rready, rready],
-          [rdata, axi4lite_if.rdata],
-          [rresp, axi4lite_if.rresp]
-        ].each { |lhs, rhs| code << assign(lhs, rhs) << nl }
-      end
+      configuration.fold_sv_interface_port? || assign_axi4lite_signals(code)
+    end
+
+    private
+
+    def id_port_width
+      "((#{id_width}>0)?#{id_width}:1)"
+    end
+
+    def assign_axi4lite_signals(code)
+      [
+        [axi4lite_if.awvalid, awvalid],
+        [awready, axi4lite_if.awready],
+        [axi4lite_if.awid, awid],
+        [axi4lite_if.awaddr, awaddr],
+        [axi4lite_if.awprot, awprot],
+        [axi4lite_if.wvalid, wvalid],
+        [wready, axi4lite_if.wready],
+        [axi4lite_if.wdata, wdata],
+        [axi4lite_if.wstrb, wstrb],
+        [bvalid, axi4lite_if.bvalid],
+        [axi4lite_if.bready, bready],
+        [bid, axi4lite_if.bid],
+        [bresp, axi4lite_if.bresp],
+        [axi4lite_if.arvalid, arvalid],
+        [arready, axi4lite_if.arready],
+        [axi4lite_if.arid, arid],
+        [axi4lite_if.araddr, araddr],
+        [axi4lite_if.arprot, arprot],
+        [rvalid, axi4lite_if.rvalid],
+        [axi4lite_if.rready, rready],
+        [rid, axi4lite_if.rid],
+        [rdata, axi4lite_if.rdata],
+        [rresp, axi4lite_if.rresp]
+      ].each { |lhs, rhs| code << assign(lhs, rhs) << nl }
     end
   end
 end

data/lib/rggen/systemverilog/rtl/register_block/sv_rtl_top.rb

@@ -23,7 +23,7 @@ RgGen.define_simple_feature(:register_block, :sv_rtl_top) do
     end
 
     def total_registers
-      register_block.files_and_registers.map(&:count).sum
+      register_block.files_and_registers.sum(&:count)
     end
 
     private

data/lib/rggen/systemverilog/rtl/register_index.rb

@@ -9,7 +9,7 @@ module RgGen
         EXPORTED_METHODS = [
           :loop_variables, :local_loop_variables,
           :local_index, :local_indices,
-          :index, :inside_roop?
+          :index, :inside_loop?
         ].freeze
 
         def self.included(feature)
@@ -23,7 +23,7 @@ module RgGen
         end
 
         def loop_variables
-          (inside_roop? || nil) &&
+          (inside_loop? || nil) &&
             [*upper_register_file&.loop_variables, *local_loop_variables]
         end
 
@@ -59,8 +59,8 @@ module RgGen
           end
         end
 
-        def inside_roop?
-          component.array? || upper_register_file&.inside_roop? || false
+        def inside_loop?
+          component.array? || upper_register_file&.inside_loop? || false
         end
 
         private