rggen-systemverilog 0.19.0 → 0.20.0

data/lib/rggen/systemverilog/rtl/register_block/protocol/axi4lite.rb

@@ -13,75 +13,73 @@ RgGen.define_list_item_feature(:register_block, :protocol, :axi4lite) do
 
   sv_rtl do
     build do
-      parameter :register_block, :write_first, {
-        name: 'WRITE_FIRST',
-        data_type: :bit,
-        default: 1
+      parameter :write_first, {
+        name: 'WRITE_FIRST', data_type: :bit, default: 1
       }
       if configuration.fold_sv_interface_port?
-        interface_port :register_block, :axi4lite_if, {
+        interface_port :axi4lite_if, {
           name: 'axi4lite_if',
           interface_type: 'rggen_axi4lite_if', modport: 'slave'
         }
       else
-        input :register_block, :awvalid, {
+        input :awvalid, {
           name: 'i_awvalid', data_type: :logic, width: 1
         }
-        output :register_block, :awready, {
+        output :awready, {
           name: 'o_awready', data_type: :logic, width: 1
         }
-        input :register_block, :awaddr, {
+        input :awaddr, {
           name: 'i_awaddr', data_type: :logic, width: address_width
         }
-        input :register_block, :awprot, {
+        input :awprot, {
           name: 'i_awprot', data_type: :logic, width: 3
         }
-        input :register_block, :wvalid, {
+        input :wvalid, {
           name: 'i_wvalid', data_type: :logic, width: 1
         }
-        output :register_block, :wready, {
+        output :wready, {
           name: 'o_wready', data_type: :logic, width: 1
         }
-        input :register_block, :wdata, {
+        input :wdata, {
           name: 'i_wdata', data_type: :logic, width: bus_width
         }
-        input :register_block, :wstrb, {
+        input :wstrb, {
           name: 'i_wstrb', data_type: :logic, width: byte_width
         }
-        output :register_block, :bvalid, {
+        output :bvalid, {
           name: 'o_bvalid', data_type: :logic, width: 1
         }
-        input :register_block, :bready, {
+        input :bready, {
           name: 'i_bready', data_type: :logic, width: 1
         }
-        output :register_block, :bresp, {
+        output :bresp, {
           name: 'o_bresp', data_type: :logic, width: 2
         }
-        input :register_block, :arvalid, {
+        input :arvalid, {
           name: 'i_arvalid', data_type: :logic, width: 1
         }
-        output :register_block, :arready, {
+        output :arready, {
           name: 'o_arready', data_type: :logic, width: 1
         }
-        input :register_block, :araddr, {
+        input :araddr, {
           name: 'i_araddr', data_type: :logic, width: address_width
         }
-        input :register_block, :arprot, {
+        input :arprot, {
           name: 'i_arprot', data_type: :logic, width: 3
         }
-        output :register_block, :rvalid, {
+        output :rvalid, {
           name: 'o_rvalid', data_type: :logic, width: 1
         }
-        input :register_block, :rready, {
+        input :rready, {
           name: 'i_rready', data_type: :logic, width: 1
         }
-        output :register_block, :rdata, {
+        output :rdata, {
           name: 'o_rdata', data_type: :logic, width: bus_width
         }
-        output :register_block, :rresp, {
+        output :rresp, {
           name: 'o_rresp', data_type: :logic, width: 2
         }
-        interface :register_block, :axi4lite_if, {
+        interface :axi4lite_if, {
           name: 'axi4lite_if', interface_type: 'rggen_axi4lite_if',
           parameter_values: [address_width, bus_width],
           variables: [

data/lib/rggen/systemverilog/rtl/register_block/sv_rtl_top.rb

@@ -5,17 +5,16 @@ RgGen.define_simple_feature(:register_block, :sv_rtl_top) do
     export :total_registers
 
     build do
-      input :register_block, :clock, {
+      input :clock, {
         name: 'i_clk', data_type: :logic, width: 1
       }
-      input :register_block, :reset, {
+      input :reset, {
         name: 'i_rst_n', data_type: :logic, width: 1
       }
-      interface :register_block, :register_if, {
+      interface :register_if, {
         name: 'register_if', interface_type: 'rggen_register_if',
         parameter_values: [address_width, bus_width, value_width],
-        array_size: [total_registers],
-        variables: ['value']
+        array_size: [total_registers], variables: ['value']
       }
     end
 
@@ -24,7 +23,7 @@ RgGen.define_simple_feature(:register_block, :sv_rtl_top) do
     end
 
     def total_registers
-      register_block.registers.map(&:count).sum
+      register_block.files_and_registers.map(&:count).sum
     end
 
     private
@@ -65,19 +64,21 @@ RgGen.define_simple_feature(:register_block, :sv_rtl_top) do
     end
 
     def parameters
-      register_block.declarations(:register_block, :parameter)
+      register_block.declarations[:parameter]
     end
 
     def ports
-      register_block.declarations(:register_block, :port)
+      register_block.declarations[:port]
     end
 
     def variables
-      register_block.declarations(:register_block, :variable)
+      register_block.declarations[:variable]
     end
 
     def sv_module_body(code)
-      register_block.generate_code(:register_block, :top_down, code)
+      { register_block: nil, register_file: 1 }.each do |kind, depth|
+        register_block.generate_code(code, kind, :top_down, depth)
+      end
     end
   end
 end

data/lib/rggen/systemverilog/rtl/register_file/sv_rtl_top.rb

@@ -0,0 +1,30 @@
+# frozen_string_literal: true
+
+RgGen.define_simple_feature(:register_file, :sv_rtl_top) do
+  sv_rtl do
+    include RgGen::SystemVerilog::RTL::RegisterIndex
+
+    main_code :register_file do
+      local_scope("g_#{register_file.name}") do |scope|
+        scope.top_scope top_scope?
+        scope.loop_size loop_size
+        scope.body(&method(:body_code))
+      end
+    end
+
+    private
+
+    def top_scope?
+      register_file(:upper).nil?
+    end
+
+    def loop_size
+      (register_file.array? || nil) &&
+        local_loop_variables.zip(register_file.array_size).to_h
+    end
+
+    def body_code(code)
+      register_file.generate_code(code, :register_file, :top_down, 1)
+    end
+  end
+end

data/lib/rggen/systemverilog/rtl/register_index.rb

@@ -0,0 +1,112 @@
+# frozen_string_literal: true
+
+module RgGen
+  module SystemVerilog
+    module RTL
+      module RegisterIndex
+        include PartialSum
+
+        EXPORTED_METHODS = [
+          :loop_variables, :local_loop_variables,
+          :local_index, :local_indices,
+          :index, :inside_roop?
+        ].freeze
+
+        def self.included(feature)
+          feature.module_eval do
+            EXPORTED_METHODS.each { |m| export m }
+
+            pre_build do
+              @base_index = files_and_registers.sum(&:count)
+            end
+          end
+        end
+
+        def loop_variables
+          (inside_roop? || nil) &&
+            [*upper_register_file&.loop_variables, *local_loop_variables]
+        end
+
+        def local_loop_variables
+          (component.array? || nil) &&
+            begin
+              start_depth = (upper_register_file&.loop_variables&.size || 0) + 1
+              Array.new(component.array_size.size) do |i|
+                create_identifier(loop_index(i + start_depth))
+              end
+            end
+        end
+
+        def local_index
+          (component.array? || nil) &&
+            local_index_coefficients
+              .zip(local_loop_variables)
+              .map { |operands| product(operands, false) }
+              .join('+')
+        end
+
+        def local_indices
+          [*upper_register_file&.local_indices, local_index]
+        end
+
+        def index(offset_or_offsets = nil)
+          operands = index_operands(offset_or_offsets)
+          partial_indices = partial_sums(operands)
+          if partial_indices.empty? || partial_indices.all?(&method(:integer?))
+            partial_indices.sum
+          else
+            partial_indices.join('+')
+          end
+        end
+
+        def inside_roop?
+          component.array? || upper_register_file&.inside_roop? || false
+        end
+
+        private
+
+        def upper_register_file
+          component.register_file
+        end
+
+        def local_index_coefficients
+          coefficients = []
+          component.array_size.reverse.inject(1) do |total, size|
+            coefficients.unshift(total)
+            total * size
+          end
+          coefficients
+        end
+
+        def index_operands(offset_or_offsets)
+          offsets = offset_or_offsets && Array(offset_or_offsets)
+          [
+            *upper_register_file&.index(offsets&.slice(0..-2)),
+            @base_index,
+            *local_register_index(offsets&.slice(-1))
+          ]
+        end
+
+        def local_register_index(offset)
+          (component.array? || nil) &&
+            begin
+              operands = [component.count(false), offset || local_index]
+              product(operands, true)
+            end
+        end
+
+        def product(operands, need_bracket)
+          if operands.all?(&method(:integer?))
+            operands.reduce(:*)
+          elsif operands.first == 1
+            operands.last
+          elsif need_bracket
+            "#{operands.first}*(#{operands.last})"
+          else
+            operands.join('*')
+          end
+        end
+      end
+    end
+  end
+end

data/lib/rggen/systemverilog/rtl/setup.rb

@@ -8,6 +8,7 @@ RgGen.setup :'rggen-sv-rtl', RgGen::SystemVerilog::RTL do |builder|
   ]
   builder.enable :register_block, [:sv_rtl_top, :protocol]
   builder.enable :register_block, :protocol, [:apb, :axi4lite]
+  builder.enable :register_file, [:sv_rtl_top]
   builder.enable :register, [:sv_rtl_top]
   builder.enable :bit_field, [:sv_rtl_top]
 end

data/lib/rggen/systemverilog/version.rb

@@ -2,6 +2,6 @@
 
 module RgGen
   module SystemVerilog
-    VERSION = '0.19.0'
+    VERSION = '0.20.0'
   end
 end

metadata

@@ -1,14 +1,14 @@
 --- !ruby/object:Gem::Specification
 name: rggen-systemverilog
 version: !ruby/object:Gem::Version
-  version: 0.19.0
+  version: 0.20.0
 platform: ruby
 authors:
 - Taichi Ishitani
 autorequire: 
 bindir: bin
 cert_chain: []
-date: 2020-02-17 00:00:00.000000000 Z
+date: 2020-07-06 00:00:00.000000000 Z
 dependencies:
 - !ruby/object:Gem::Dependency
   name: docile
@@ -93,8 +93,12 @@ files:
 - lib/rggen/systemverilog/ral/register/type/external.rb
 - lib/rggen/systemverilog/ral/register/type/indirect.erb
 - lib/rggen/systemverilog/ral/register/type/indirect.rb
-- lib/rggen/systemverilog/ral/register_block/sv_ral_block_model.erb
+- lib/rggen/systemverilog/ral/register_block/sv_ral_model.erb
+- lib/rggen/systemverilog/ral/register_block/sv_ral_model.rb
 - lib/rggen/systemverilog/ral/register_block/sv_ral_package.rb
+- lib/rggen/systemverilog/ral/register_common.rb
+- lib/rggen/systemverilog/ral/register_file/sv_ral_model.erb
+- lib/rggen/systemverilog/ral/register_file/sv_ral_model.rb
 - lib/rggen/systemverilog/ral/setup.rb
 - lib/rggen/systemverilog/rtl.rb
 - lib/rggen/systemverilog/rtl/bit_field/sv_rtl_top.rb
@@ -128,6 +132,7 @@ files:
 - lib/rggen/systemverilog/rtl/feature.rb
 - lib/rggen/systemverilog/rtl/global/array_port_format.rb
 - lib/rggen/systemverilog/rtl/global/fold_sv_interface_port.rb
+- lib/rggen/systemverilog/rtl/partial_sum.rb
 - lib/rggen/systemverilog/rtl/register/sv_rtl_top.rb
 - lib/rggen/systemverilog/rtl/register/type.rb
 - lib/rggen/systemverilog/rtl/register/type/default.erb
@@ -142,6 +147,8 @@ files:
 - lib/rggen/systemverilog/rtl/register_block/protocol/axi4lite.rb
 - lib/rggen/systemverilog/rtl/register_block/sv_rtl_macros.erb
 - lib/rggen/systemverilog/rtl/register_block/sv_rtl_top.rb
+- lib/rggen/systemverilog/rtl/register_file/sv_rtl_top.rb
+- lib/rggen/systemverilog/rtl/register_index.rb
 - lib/rggen/systemverilog/rtl/setup.rb
 - lib/rggen/systemverilog/version.rb
 homepage: https://github.com/rggen/rggen-systemverilog
@@ -170,5 +177,5 @@ requirements: []
 rubygems_version: 3.1.2
 signing_key: 
 specification_version: 4
-summary: rggen-systemverilog-0.19.0
+summary: rggen-systemverilog-0.20.0
 test_files: []

data/lib/rggen/systemverilog/ral/register_block/sv_ral_block_model.erb

@@ -1,11 +0,0 @@
-function new(string name);
-  super.new(name);
-endfunction
-function void build();
-<% reg_model_constructors.each do |constructor| %>
-  <%= constructor %>
-<% end %>
-endfunction
-function uvm_reg_map create_default_map();
-  return create_map("default_map", 0, <%= byte_width %>, UVM_LITTLE_ENDIAN, 1);
-endfunction