rggen-systemverilog 0.19.0 → 0.20.0

data/lib/rggen/systemverilog/ral/register/type/indirect.erb

@@ -4,10 +4,10 @@ endfunction
 function void build();
 <% field_model_constructors.each do |constructor| %>
   <%= constructor %>
-<% end%>
+<% end %>
 endfunction
 function void setup_index_fields();
-<% index_properties.each do |reg_name, field_name, value| %>
-  setup_index_field("<%= reg_name %>", "<%= field_name%>", <%= value %>);
+<% index_properties.each do |field_name, value| %>
+  setup_index_field("<%= field_name %>", <%= value %>);
 <% end %>
 endfunction

data/lib/rggen/systemverilog/ral/register/type/indirect.rb

@@ -2,7 +2,6 @@
 
 RgGen.define_list_item_feature(:register, :type, :indirect) do
   sv_ral do
-    unmapped
     offset_address { register.offset_address }
 
     main_code :ral_package do
@@ -24,12 +23,16 @@ RgGen.define_list_item_feature(:register, :type, :indirect) do
           else
             "array_index[#{array_position += 1}]"
           end
-        [field.register.name, field.name, value]
+        [field_full_name(field), value]
       end
     end
 
     def index_fields
       register.collect_index_fields(register_block.bit_fields)
     end
+
+    def field_full_name(field)
+      [field.register.full_name('.'), field.name].join('.')
+    end
   end
 end

data/lib/rggen/systemverilog/ral/register_block/sv_ral_model.erb

@@ -0,0 +1,8 @@
+function new(string name);
+  super.new(name, <%= byte_width %>, 0);
+endfunction
+function void build();
+<% child_model_constructors.each do |constructor| %>
+  <%= constructor %>
+<% end %>
+endfunction

data/lib/rggen/systemverilog/ral/register_block/sv_ral_model.rb

@@ -0,0 +1,36 @@
+# frozen_string_literal: true
+
+RgGen.define_simple_feature(:register_block, :sv_ral_model) do
+  sv_ral do
+    main_code :ral_package do
+      class_definition(model_name) do |sv_class|
+        sv_class.base 'rggen_ral_block'
+        sv_class.parameters parameters
+        sv_class.variables variables
+        sv_class.body { process_template }
+      end
+    end
+
+    private
+
+    def model_name
+      "#{register_block.name}_block_model"
+    end
+
+    def parameters
+      register_block.declarations[:parameter]
+    end
+
+    def variables
+      register_block.declarations[:variable]
+    end
+
+    def byte_width
+      configuration.byte_width
+    end
+
+    def child_model_constructors
+      register_block.children.flat_map(&:constructors)
+    end
+  end
+end

data/lib/rggen/systemverilog/ral/register_block/sv_ral_package.rb

@@ -8,23 +8,12 @@ RgGen.define_simple_feature(:register_block, :sv_ral_package) do
           package.package_imports packages
           package.include_files include_files
           package.body do |code|
-            register_block.generate_code(:ral_package, :bottom_up, code)
+            register_block.generate_code(code, :ral_package, :bottom_up)
           end
         end
       end
     end
 
-    main_code :ral_package do
-      class_definition(model_name) do |sv_class|
-        sv_class.base 'rggen_ral_block'
-        sv_class.parameters parameters
-        sv_class.variables variables
-        sv_class.body do
-          process_template(File.join(__dir__, 'sv_ral_block_model.erb'))
-        end
-      end
-    end
-
     private
 
     def package_name
@@ -41,25 +30,5 @@ RgGen.define_simple_feature(:register_block, :sv_ral_package) do
     def include_files
       ['uvm_macros.svh', 'rggen_ral_macros.svh']
     end
-
-    def model_name
-      "#{register_block.name}_block_model"
-    end
-
-    def parameters
-      register_block.declarations(:register_block, :parameter)
-    end
-
-    def variables
-      register_block.declarations(:register_block, :variable)
-    end
-
-    def reg_model_constructors
-      register_block.registers.flat_map(&:constructors)
-    end
-
-    def byte_width
-      configuration.byte_width
-    end
   end
 end

data/lib/rggen/systemverilog/ral/register_common.rb

@@ -0,0 +1,46 @@
+# frozen_string_literal: true
+
+module RgGen
+  module SystemVerilog
+    module RAL
+      module RegisterCommon
+        private
+
+        def array_indices
+          if component.array?
+            index_table = component.array_size.map { |size| (0...size).to_a }
+            index_table[0].product(*index_table[1..-1])
+          else
+            [nil]
+          end
+        end
+
+        def offset_address(index)
+          address =
+            if register? && helper.offset_address
+              instance_exec(index, &helper.offset_address)
+            else
+              default_offset_address(index)
+            end
+          hex(address, register_block.local_address_width)
+        end
+
+        def default_offset_address(index)
+          component.offset_address + component.byte_size(false) * index
+        end
+
+        def hdl_path(array_index)
+          [
+            "g_#{component.name}",
+            *Array(array_index).map { |i| "g[#{i}]" },
+            *unit_instance_name
+          ].join('.')
+        end
+
+        def unit_instance_name
+          register? && 'u_register' || nil
+        end
+      end
+    end
+  end
+end

data/lib/rggen/systemverilog/ral/register_file/sv_ral_model.erb

@@ -0,0 +1,8 @@
+function new(string name);
+  super.new(name, <%= byte_width %>, 0);
+endfunction
+function void build();
+<% child_model_constructors.each do |constructor| %>
+  <%= constructor %>
+<% end %>
+endfunction

data/lib/rggen/systemverilog/ral/register_file/sv_ral_model.rb

@@ -0,0 +1,57 @@
+# frozen_string_literal: true
+
+RgGen.define_simple_feature(:register_file, :sv_ral_model) do
+  sv_ral do
+    include RgGen::SystemVerilog::RAL::RegisterCommon
+
+    export :constructors
+
+    build do
+      variable :ral_model, {
+        name: register_file.name, data_type: model_name,
+        array_size: register_file.array_size, random: true
+      }
+    end
+
+    def constructors
+      array_indices.map.with_index(&method(:constructor_code))
+    end
+
+    main_code :ral_package do
+      class_definition(model_name) do |sv_class|
+        sv_class.base 'rggen_ral_reg_file'
+        sv_class.variables variables
+        sv_class.body { process_template }
+      end
+    end
+
+    private
+
+    def model_name
+      "#{register_file.full_name('_')}_reg_file_model"
+    end
+
+    def constructor_code(array_index, index)
+      macro_call(:rggen_ral_create_reg_file, arguments(array_index, index))
+    end
+
+    def arguments(array_index, index)
+      [
+        ral_model[array_index], array(array_index), offset_address(index),
+        string(hdl_path(array_index))
+      ]
+    end
+
+    def variables
+      register_file.declarations[:variable]
+    end
+
+    def byte_width
+      configuration.byte_width
+    end
+
+    def child_model_constructors
+      register_file.children.flat_map(&:constructors)
+    end
+  end
+end

data/lib/rggen/systemverilog/ral/setup.rb

@@ -3,5 +3,6 @@
 require 'rggen/systemverilog/ral'
 
 RgGen.setup :'rggen-sv-ral', RgGen::SystemVerilog::RAL do |builder|
-  builder.enable :register_block, [:sv_ral_package]
+  builder.enable :register_block, [:sv_ral_model, :sv_ral_package]
+  builder.enable :register_file, [:sv_ral_model]
 end

data/lib/rggen/systemverilog/rtl.rb

@@ -2,6 +2,8 @@
 
 require_relative 'common'
 require_relative 'rtl/feature'
+require_relative 'rtl/partial_sum'
+require_relative 'rtl/register_index'
 
 module RgGen
   module SystemVerilog
@@ -31,7 +33,8 @@ module RgGen
         'rtl/register_block/protocol',
         'rtl/register_block/protocol/apb',
         'rtl/register_block/protocol/axi4lite',
-        'rtl/register_block/sv_rtl_top'
+        'rtl/register_block/sv_rtl_top',
+        'rtl/register_file/sv_rtl_top'
       ].freeze
 
       def self.version

data/lib/rggen/systemverilog/rtl/bit_field/sv_rtl_top.rb

@@ -3,25 +3,26 @@
 RgGen.define_simple_feature(:bit_field, :sv_rtl_top) do
   sv_rtl do
     export :local_index
+    export :local_indices
     export :loop_variables
     export :array_size
     export :value
 
     build do
       if fixed_initial_value?
-        localparam :bit_field, :initial_value, {
+        localparam :initial_value, {
           name: initial_value_name, data_type: :bit, width: bit_field.width,
           array_size: initial_value_size, array_format: initial_value_format,
           default: initial_value_lhs
         }
       elsif initial_value?
-        parameter :register_block, :initial_value, {
+        parameter :initial_value, {
           name: initial_value_name, data_type: :bit, width: bit_field.width,
           array_size: initial_value_size, array_format: initial_value_format,
           default: initial_value_lhs
         }
       end
-      interface :bit_field, :bit_field_sub_if, {
+      interface :bit_field_sub_if, {
         name: 'bit_field_sub_if',
         interface_type: 'rggen_bit_field_if',
         parameter_values: [bit_field.width]
@@ -42,13 +43,12 @@ RgGen.define_simple_feature(:bit_field, :sv_rtl_top) do
     end
 
     def local_index
-      (bit_field.sequential? || nil) &&
+      (index_name = local_index_name) &&
         create_identifier(index_name)
     end
 
-    def index_name
-      depth = (register.loop_variables&.size || 0) + 1
-      loop_index(depth)
+    def local_indices
+      [*register.local_indices, local_index_name]
     end
 
     def loop_variables
@@ -58,15 +58,17 @@ RgGen.define_simple_feature(:bit_field, :sv_rtl_top) do
 
     def array_size
       (inside_loop? || nil) &&
-        [*register.array_size, bit_field.sequence_size].compact
+        [
+          *register_files.flat_map(&:array_size),
+          *register.array_size,
+          *bit_field.sequence_size
+        ].compact
     end
 
-    def value(register_offset = nil, bit_field_offset = nil, width = nil)
-      bit_field_offset ||= local_index
-      width ||= bit_field.width
-      register_block
-        .register_if[register.index(register_offset)]
-        .value[bit_field.lsb(bit_field_offset), width]
+    def value(offsets = nil, width = nil)
+      value_lsb = bit_field.lsb(offsets&.last || local_index_name)
+      value_width = width || bit_field.width
+      register_if(offsets&.slice(0..-2)).value[value_lsb, value_width]
     end
 
     private
@@ -75,6 +77,19 @@ RgGen.define_simple_feature(:bit_field, :sv_rtl_top) do
       define_method(m) { bit_field.__send__(__method__) }
     end
 
+    def local_index_name
+      (bit_field.sequential? || nil) &&
+        begin
+          depth = (register.loop_variables&.size || 0) + 1
+          loop_index(depth)
+        end
+    end
+
+    def register_if(offsets)
+      index = register.index(offsets || register.local_indices)
+      register_block.register_if[index]
+    end
+
     def initial_value_name
       identifiers = []
       identifiers << bit_field.full_name('_') unless fixed_initial_value?
@@ -119,20 +134,20 @@ RgGen.define_simple_feature(:bit_field, :sv_rtl_top) do
     end
 
     def loop_size
-      (bit_field.sequential? || nil) &&
-        { index_name => bit_field.sequence_size }
+      (loop_variable = local_index_name) &&
+        { loop_variable => bit_field.sequence_size }
     end
 
     def parameters
-      bit_field.declarations(:bit_field, :parameter)
+      bit_field.declarations[:parameter]
     end
 
     def variables
-      bit_field.declarations(:bit_field, :variable)
+      bit_field.declarations[:variable]
     end
 
     def body_code(code)
-      bit_field.generate_code(:bit_field, :top_down, code)
+      bit_field.generate_code(code, :bit_field, :top_down)
     end
 
     def bit_field_if_connection

data/lib/rggen/systemverilog/rtl/bit_field/type.rb

@@ -43,11 +43,7 @@ RgGen.define_list_feature(:bit_field, :type) do
         bit_field.reference? &&
           bit_field
             .find_reference(register_block.bit_fields)
-            .value(
-              register.local_index,
-              bit_field.local_index,
-              bit_field.reference_width
-            )
+            .value(bit_field.local_indices, bit_field.reference_width)
       end
 
       def bit_field_if

data/lib/rggen/systemverilog/rtl/bit_field/type/rc_w0c_w1c.rb

@@ -3,16 +3,16 @@
 RgGen.define_list_item_feature(:bit_field, :type, [:rc, :w0c, :w1c]) do
   sv_rtl do
     build do
-      input :register_block, :set, {
+      input :set, {
         name: "i_#{full_name}_set", data_type: :logic, width: width,
         array_size: array_size, array_format: array_port_format
       }
-      output :register_block, :value_out, {
+      output :value_out, {
         name: "o_#{full_name}", data_type: :logic, width: width,
         array_size: array_size, array_format: array_port_format
       }
       if bit_field.reference?
-        output :register_block, :value_unmasked, {
+        output :value_unmasked, {
           name: "o_#{full_name}_unmasked", data_type: :logic, width: width,
           array_size: array_size, array_format: array_port_format
         }

data/lib/rggen/systemverilog/rtl/bit_field/type/ro.rb

@@ -4,7 +4,7 @@ RgGen.define_list_item_feature(:bit_field, :type, :ro) do
   sv_rtl do
     build do
       unless bit_field.reference?
-        input :register_block, :value_in, {
+        input :value_in, {
           name: "i_#{full_name}", data_type: :logic, width: width,
           array_size: array_size, array_format: array_port_format
         }

data/lib/rggen/systemverilog/rtl/bit_field/type/rs_w0s_w1s.rb

@@ -3,11 +3,11 @@
 RgGen.define_list_item_feature(:bit_field, :type, [:rs, :w0s, :w1s]) do
   sv_rtl do
     build do
-      input :register_block, :clear, {
+      input :clear, {
         name: "i_#{full_name}_clear", data_type: :logic, width: width,
         array_size: array_size, array_format: array_port_format
       }
-      output :register_block, :value_out, {
+      output :value_out, {
         name: "o_#{full_name}", data_type: :logic, width: width,
         array_size: array_size, array_format: array_port_format
       }