rggen-systemverilog 0.19.0 → 0.20.0

data/lib/rggen/systemverilog/rtl/bit_field/type/rw_w1_wo_wo1.rb

@@ -3,7 +3,7 @@
 RgGen.define_list_item_feature(:bit_field, :type, [:rw, :w1, :wo, :wo1]) do
   sv_rtl do
     build do
-      output :register_block, :value_out, {
+      output :value_out, {
         name: "o_#{full_name}", data_type: :logic, width: width,
         array_size: array_size, array_format: array_port_format
       }

data/lib/rggen/systemverilog/rtl/bit_field/type/rwc.rb

@@ -4,12 +4,12 @@ RgGen.define_list_item_feature(:bit_field, :type, :rwc) do
   sv_rtl do
     build do
       unless bit_field.reference?
-        input :register_block, :clear, {
+        input :clear, {
           name: "i_#{full_name}_clear", data_type: :logic, width: 1,
           array_size: array_size, array_format: array_port_format
         }
       end
-      output :register_block, :value_out, {
+      output :value_out, {
         name: "o_#{full_name}", data_type: :logic, width: width,
         array_size: array_size, array_format: array_port_format
       }

data/lib/rggen/systemverilog/rtl/bit_field/type/rwe.rb

@@ -4,12 +4,12 @@ RgGen.define_list_item_feature(:bit_field, :type, :rwe) do
   sv_rtl do
     build do
       unless bit_field.reference?
-        input :register_block, :enable, {
+        input :enable, {
           name: "i_#{full_name}_enable", data_type: :logic, width: 1,
           array_size: array_size, array_format: array_port_format
         }
       end
-      output :register_block, :value_out, {
+      output :value_out, {
         name: "o_#{full_name}", data_type: :logic, width: width,
         array_size: array_size, array_format: array_port_format
       }

data/lib/rggen/systemverilog/rtl/bit_field/type/rwl.rb

@@ -4,12 +4,12 @@ RgGen.define_list_item_feature(:bit_field, :type, :rwl) do
   sv_rtl do
     build do
       unless bit_field.reference?
-        input :register_block, :lock, {
+        input :lock, {
           name: "i_#{full_name}_lock", data_type: :logic, width: 1,
           array_size: array_size, array_format: array_port_format
         }
       end
-      output :register_block, :value_out, {
+      output :value_out, {
         name: "o_#{full_name}", data_type: :logic, width: width,
         array_size: array_size, array_format: array_port_format
       }

data/lib/rggen/systemverilog/rtl/bit_field/type/rws.rb

@@ -4,16 +4,16 @@ RgGen.define_list_item_feature(:bit_field, :type, :rws) do
   sv_rtl do
     build do
       unless bit_field.reference?
-        input :register_block, :set, {
+        input :set, {
           name: "i_#{full_name}_set", data_type: :logic, width: 1,
           array_size: array_size, array_format: array_port_format
         }
       end
-      input :register_block, :value_in, {
+      input :value_in, {
         name: "i_#{full_name}", data_type: :logic, width: width,
         array_size: array_size, array_format: array_port_format
       }
-      output :register_block, :value_out, {
+      output :value_out, {
         name: "o_#{full_name}", data_type: :logic, width: width,
         array_size: array_size, array_format: array_port_format
       }

data/lib/rggen/systemverilog/rtl/bit_field/type/w0crs_w1crs.rb

@@ -3,7 +3,7 @@
 RgGen.define_list_item_feature(:bit_field, :type, [:w0crs, :w1crs]) do
   sv_rtl do
     build do
-      output :register_block, :value_out, {
+      output :value_out, {
         name: "o_#{full_name}", data_type: :logic, width: width,
         array_size: array_size, array_format: array_port_format
       }

data/lib/rggen/systemverilog/rtl/bit_field/type/w0src_w1src.rb

@@ -3,7 +3,7 @@
 RgGen.define_list_item_feature(:bit_field, :type, [:w0src, :w1src]) do
   sv_rtl do
     build do
-      output :register_block, :value_out, {
+      output :value_out, {
         name: "o_#{full_name}", data_type: :logic, width: width,
         array_size: array_size, array_format: array_port_format
       }

data/lib/rggen/systemverilog/rtl/bit_field/type/w0trg_w1trg.rb

@@ -3,7 +3,7 @@
 RgGen.define_list_item_feature(:bit_field, :type, [:w0trg, :w1trg]) do
   sv_rtl do
     build do
-      output :register_block, :trigger, {
+      output :trigger, {
         name: "o_#{full_name}_trigger", data_type: :logic, width: width,
         array_size: array_size, array_format: array_port_format
       }

data/lib/rggen/systemverilog/rtl/feature.rb

@@ -6,43 +6,39 @@ module RgGen
       class Feature < Common::Feature
         private
 
-        def create_variable(data_type, attributes = {}, &block)
+        def create_variable(data_type, attributes, &block)
           DataObject.new(
             :variable, attributes.merge(data_type: data_type), &block
           )
         end
 
-        def create_interface(_, attributes = {}, &block)
+        def create_if_instance(_, attributes, &block)
           InterfaceInstance.new(attributes, &block)
         end
 
-        def create_argument(direction, attributes = {}, &block)
+        def create_argument(direction, attributes, &block)
           DataObject.new(
             :argument, attributes.merge(direction: direction), &block
           )
         end
 
-        def create_interface_port(_, attributes = {}, &block)
+        def create_if_port(_, attributes, &block)
           InterfacePort.new(attributes, &block)
         end
 
-        def create_parameter(parameter_type, attributes = {}, &block)
+        def create_parameter(parameter_type, attributes, &block)
           DataObject.new(
             :parameter, attributes.merge(parameter_type: parameter_type), &block
           )
         end
 
-        [
-          [:logic, :create_variable, :variable],
-          [:interface, :create_interface, :variable],
-          [:input, :create_argument, :port],
-          [:output, :create_argument, :port],
-          [:interface_port, :create_interface_port, :port],
-          [:parameter, :create_parameter, :parameter],
-          [:localparam, :create_parameter, :parameter]
-        ].each do |entity, creation_method, declaration_type|
-          define_entity(entity, creation_method, declaration_type)
-        end
+        define_entity :logic, :create_variable, :variable, -> { component }
+        define_entity :interface, :create_if_instance, :variable, -> { component }
+        define_entity :input, :create_argument, :port, -> { register_block }
+        define_entity :output, :create_argument, :port, -> { register_block }
+        define_entity :interface_port, :create_if_port, :port, -> { register_block }
+        define_entity :parameter, :create_parameter, :parameter, -> { register_block }
+        define_entity :localparam, :create_parameter, :parameter, -> { component }
       end
     end
   end

data/lib/rggen/systemverilog/rtl/partial_sum.rb

@@ -0,0 +1,29 @@
+# frozen_string_literal: true
+
+module RgGen
+  module SystemVerilog
+    module RTL
+      module PartialSum
+        private
+
+        def partial_sums(operands)
+          sums =
+            operands
+              .chunk(&method(:integer?))
+              .flat_map(&method(:calc_partial_sum))
+              .reject { |value| integer?(value) && value.zero? }
+          sums.empty? && [0] || sums
+        end
+
+        def calc_partial_sum(kind_ans_values)
+          kind, values = kind_ans_values
+          kind && values.sum || values
+        end
+
+        def integer?(value)
+          value.is_a?(Integer)
+        end
+      end
+    end
+  end
+end

data/lib/rggen/systemverilog/rtl/register/sv_rtl_top.rb

@@ -2,18 +2,11 @@
 
 RgGen.define_simple_feature(:register, :sv_rtl_top) do
   sv_rtl do
-    export :index
-    export :local_index
-    export :loop_variables
-
-    pre_build do
-      @base_index =
-        register_block.registers.map(&:count).sum
-    end
+    include RgGen::SystemVerilog::RTL::RegisterIndex
 
     build do
-      if register.bit_fields?
-        interface :register, :bit_field_if, {
+      unless register.bit_fields.empty?
+        interface :bit_field_if, {
           name: 'bit_field_if',
           interface_type: 'rggen_bit_field_if',
           parameter_values: [register.width]
@@ -21,62 +14,32 @@ RgGen.define_simple_feature(:register, :sv_rtl_top) do
       end
     end
 
-    main_code :register_block do
+    main_code :register_file do
       local_scope("g_#{register.name}") do |scope|
-        scope.top_scope
+        scope.top_scope top_scope?
         scope.loop_size loop_size
         scope.variables variables
         scope.body(&method(:body_code))
       end
     end
 
-    def index(offset = nil)
-      operands =
-        register.array? ? [@base_index, offset || local_index] : [@base_index]
-      if operands.all? { |operand| operand.is_a?(Integer) }
-        operands.sum
-      else
-        operands.join('+')
-      end
-    end
-
-    def local_index
-      (register.array? || nil) &&
-        loop_variables
-          .zip(local_index_coefficients)
-          .map { |v, c| [c, v].compact.join('*') }
-          .join('+')
-    end
-
-    def loop_variables
-      (register.array? || nil) &&
-        register.array_size.map.with_index(1) do |_size, i|
-          create_identifier(loop_index(i))
-        end
-    end
-
     private
 
-    def local_index_coefficients
-      coefficients = []
-      register.array_size.reverse.inject(1) do |total, size|
-        coefficients.unshift(coefficients.size.zero? ? nil : total)
-        total * size
-      end
-      coefficients
+    def top_scope?
+      register_file.nil?
     end
 
     def loop_size
       (register.array? || nil) &&
-        loop_variables.zip(register.array_size).to_h
+        local_loop_variables.zip(register.array_size).to_h
     end
 
     def variables
-      register.declarations(:register, :variable)
+      register.declarations[:variable]
     end
 
     def body_code(code)
-      register.generate_code(:register, :top_down, code)
+      register.generate_code(code, :register, :top_down)
     end
   end
 end

data/lib/rggen/systemverilog/rtl/register/type.rb

@@ -3,6 +3,8 @@
 RgGen.define_list_feature(:register, :type) do
   sv_rtl do
     base_feature do
+      include RgGen::SystemVerilog::RTL::PartialSum
+
       private
 
       def readable
@@ -22,7 +24,29 @@ RgGen.define_list_feature(:register, :type) do
       end
 
       def offset_address
-        hex(register.offset_address, address_width)
+        offsets = [*register_files, register].flat_map(&method(:collect_offsets))
+        offsets = partial_sums(offsets)
+        format_offsets(offsets)
+      end
+
+      def collect_offsets(component)
+        if component.register_file? && component.array?
+          [component.offset_address, byte_offset(component)]
+        else
+          component.offset_address
+        end
+      end
+
+      def byte_offset(component)
+        "#{component.byte_size(false)}*(#{component.local_index})"
+      end
+
+      def format_offsets(offsets)
+        offsets.map(&method(:format_offset)).join('+')
+      end
+
+      def format_offset(offset)
+        offset.is_a?(Integer) ? hex(offset, address_width) : offset
       end
 
       def width

data/lib/rggen/systemverilog/rtl/register/type/external.rb

@@ -4,45 +4,45 @@ RgGen.define_list_item_feature(:register, :type, :external) do
   sv_rtl do
     build do
       if configuration.fold_sv_interface_port?
-        interface_port :register_block, :bus_if, {
+        interface_port :bus_if, {
           name: "#{register.name}_bus_if",
           interface_type: 'rggen_bus_if',
           modport: 'master'
         }
       else
-        output :register_block, :valid, {
+        output :valid, {
           name: "o_#{register.name}_valid",
           data_type: :logic, width: 1
         }
-        output :register_block, :access, {
+        output :access, {
           name: "o_#{register.name}_access",
           data_type: :logic, width: '$bits(rggen_access)'
         }
-        output :register_block, :address, {
+        output :address, {
           name: "o_#{register.name}_address",
           data_type: :logic, width: address_width
         }
-        output :register_block, :write_data, {
+        output :write_data, {
           name: "o_#{register.name}_data",
           data_type: :logic, width: bus_width
         }
-        output :register_block, :strobe, {
+        output :strobe, {
           name: "o_#{register.name}_strobe",
           data_type: :logic, width: byte_width
         }
-        input :register_block, :ready, {
+        input :ready, {
           name: "i_#{register.name}_ready",
           data_type: :logic, width: 1
         }
-        input :register_block, :status, {
+        input :status, {
           name: "i_#{register.name}_status",
           data_type: :logic, width: 2
         }
-        input :register_block, :read_data, {
+        input :read_data, {
           name: "i_#{register.name}_data",
           data_type: :logic, width: bus_width
         }
-        interface :register, :bus_if, {
+        interface :bus_if, {
           name: 'bus_if', interface_type: 'rggen_bus_if',
           parameter_values: [address_width, bus_width],
           variables: [

data/lib/rggen/systemverilog/rtl/register/type/indirect.rb

@@ -3,7 +3,7 @@
 RgGen.define_list_item_feature(:register, :type, :indirect) do
   sv_rtl do
     build do
-      logic :register, :indirect_index, { width: index_width }
+      logic :indirect_index, { width: index_width }
     end
 
     main_code :register do |code|
@@ -23,7 +23,7 @@ RgGen.define_list_item_feature(:register, :type, :indirect) do
     end
 
     def index_values
-      loop_variables = register.loop_variables
+      loop_variables = register.local_loop_variables
       register.index_entries.zip(index_fields).map do |entry, field|
         if entry.array_index?
           loop_variables.shift[0, field.width]

data/lib/rggen/systemverilog/rtl/register_block/protocol.rb

@@ -65,10 +65,10 @@ RgGen.define_list_feature(:register_block, :protocol) do
 
     base_feature do
       build do
-        parameter :register_block, :error_status, {
+        parameter :error_status, {
           name: 'ERROR_STATUS', data_type: :bit, width: 1, default: 0
         }
-        parameter :register_block, :default_read_data, {
+        parameter :default_read_data, {
           name: 'DEFAULT_READ_DATA', data_type: :bit, width: bus_width,
           default: hex(0, bus_width)
         }

data/lib/rggen/systemverilog/rtl/register_block/protocol/apb.rb

@@ -22,42 +22,41 @@ RgGen.define_list_item_feature(:register_block, :protocol, :apb) do
   sv_rtl do
     build do
       if configuration.fold_sv_interface_port?
-        interface_port :register_block, :apb_if, {
+        interface_port :apb_if, {
           name: 'apb_if', interface_type: 'rggen_apb_if', modport: 'slave'
         }
       else
-        input :register_block, :psel, {
+        input :psel, {
           name: 'i_psel', data_type: :logic, width: 1
         }
-        input :register_block, :penable, {
+        input :penable, {
           name: 'i_penable', data_type: :logic, width: 1
         }
-        input :register_block, :paddr, {
+        input :paddr, {
           name: 'i_paddr', data_type: :logic, width: address_width
         }
-        input :register_block, :pprot, {
+        input :pprot, {
           name: 'i_pprot', data_type: :logic, width: 3
         }
-        input :register_block, :pwrite, {
+        input :pwrite, {
           name: 'i_pwrite', data_type: :logic, width: 1
         }
-        input :register_block, :pstrb, {
-          name: 'i_pstrb', data_type: :logic,
-          width: byte_width
+        input :pstrb, {
+          name: 'i_pstrb', data_type: :logic, width: byte_width
         }
-        input :register_block, :pwdata, {
+        input :pwdata, {
           name: 'i_pwdata', data_type: :logic, width: bus_width
         }
-        output :register_block, :pready, {
+        output :pready, {
           name: 'o_pready', data_type: :logic, width: 1
         }
-        output :register_block, :prdata, {
+        output :prdata, {
           name: 'o_prdata', data_type: :logic, width: bus_width
         }
-        output :register_block, :pslverr, {
+        output :pslverr, {
           name: 'o_pslverr', data_type: :logic, width: 1
         }
-        interface :register_block, :apb_if, {
+        interface :apb_if, {
           name: 'apb_if', interface_type: 'rggen_apb_if',
           parameter_values: [address_width, bus_width],
           variables: [