rggen-systemverilog 0.19.0 → 0.20.0
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- checksums.yaml +4 -4
- data/lib/rggen/systemverilog/common.rb +2 -2
- data/lib/rggen/systemverilog/common/component.rb +2 -6
- data/lib/rggen/systemverilog/common/feature.rb +39 -26
- data/lib/rggen/systemverilog/common/utility/interface_port.rb +7 -3
- data/lib/rggen/systemverilog/common/utility/local_scope.rb +2 -2
- data/lib/rggen/systemverilog/common/utility/structure_definition.rb +1 -3
- data/lib/rggen/systemverilog/ral.rb +4 -1
- data/lib/rggen/systemverilog/ral/bit_field/type.rb +15 -10
- data/lib/rggen/systemverilog/ral/bit_field/type/rwe_rwl.rb +1 -11
- data/lib/rggen/systemverilog/ral/feature.rb +4 -4
- data/lib/rggen/systemverilog/ral/register/type.rb +10 -52
- data/lib/rggen/systemverilog/ral/register/type/default.erb +1 -1
- data/lib/rggen/systemverilog/ral/register/type/external.rb +6 -10
- data/lib/rggen/systemverilog/ral/register/type/indirect.erb +3 -3
- data/lib/rggen/systemverilog/ral/register/type/indirect.rb +5 -2
- data/lib/rggen/systemverilog/ral/register_block/sv_ral_model.erb +8 -0
- data/lib/rggen/systemverilog/ral/register_block/sv_ral_model.rb +36 -0
- data/lib/rggen/systemverilog/ral/register_block/sv_ral_package.rb +1 -32
- data/lib/rggen/systemverilog/ral/register_common.rb +46 -0
- data/lib/rggen/systemverilog/ral/register_file/sv_ral_model.erb +8 -0
- data/lib/rggen/systemverilog/ral/register_file/sv_ral_model.rb +57 -0
- data/lib/rggen/systemverilog/ral/setup.rb +2 -1
- data/lib/rggen/systemverilog/rtl.rb +4 -1
- data/lib/rggen/systemverilog/rtl/bit_field/sv_rtl_top.rb +34 -19
- data/lib/rggen/systemverilog/rtl/bit_field/type.rb +1 -5
- data/lib/rggen/systemverilog/rtl/bit_field/type/rc_w0c_w1c.rb +3 -3
- data/lib/rggen/systemverilog/rtl/bit_field/type/ro.rb +1 -1
- data/lib/rggen/systemverilog/rtl/bit_field/type/rs_w0s_w1s.rb +2 -2
- data/lib/rggen/systemverilog/rtl/bit_field/type/rw_w1_wo_wo1.rb +1 -1
- data/lib/rggen/systemverilog/rtl/bit_field/type/rwc.rb +2 -2
- data/lib/rggen/systemverilog/rtl/bit_field/type/rwe.rb +2 -2
- data/lib/rggen/systemverilog/rtl/bit_field/type/rwl.rb +2 -2
- data/lib/rggen/systemverilog/rtl/bit_field/type/rws.rb +3 -3
- data/lib/rggen/systemverilog/rtl/bit_field/type/w0crs_w1crs.rb +1 -1
- data/lib/rggen/systemverilog/rtl/bit_field/type/w0src_w1src.rb +1 -1
- data/lib/rggen/systemverilog/rtl/bit_field/type/w0trg_w1trg.rb +1 -1
- data/lib/rggen/systemverilog/rtl/feature.rb +12 -16
- data/lib/rggen/systemverilog/rtl/partial_sum.rb +29 -0
- data/lib/rggen/systemverilog/rtl/register/sv_rtl_top.rb +10 -47
- data/lib/rggen/systemverilog/rtl/register/type.rb +25 -1
- data/lib/rggen/systemverilog/rtl/register/type/external.rb +10 -10
- data/lib/rggen/systemverilog/rtl/register/type/indirect.rb +2 -2
- data/lib/rggen/systemverilog/rtl/register_block/protocol.rb +2 -2
- data/lib/rggen/systemverilog/rtl/register_block/protocol/apb.rb +13 -14
- data/lib/rggen/systemverilog/rtl/register_block/protocol/axi4lite.rb +23 -25
- data/lib/rggen/systemverilog/rtl/register_block/sv_rtl_top.rb +11 -10
- data/lib/rggen/systemverilog/rtl/register_file/sv_rtl_top.rb +30 -0
- data/lib/rggen/systemverilog/rtl/register_index.rb +112 -0
- data/lib/rggen/systemverilog/rtl/setup.rb +1 -0
- data/lib/rggen/systemverilog/version.rb +1 -1
- metadata +11 -4
- data/lib/rggen/systemverilog/ral/register_block/sv_ral_block_model.erb +0 -11
@@ -3,7 +3,7 @@
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RgGen.define_list_item_feature(:bit_field, :type, [:rw, :w1, :wo, :wo1]) do
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sv_rtl do
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build do
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-
output :
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+
output :value_out, {
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name: "o_#{full_name}", data_type: :logic, width: width,
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array_size: array_size, array_format: array_port_format
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}
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@@ -4,12 +4,12 @@ RgGen.define_list_item_feature(:bit_field, :type, :rwc) do
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sv_rtl do
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build do
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unless bit_field.reference?
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-
input :
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+
input :clear, {
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name: "i_#{full_name}_clear", data_type: :logic, width: 1,
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array_size: array_size, array_format: array_port_format
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}
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end
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-
output :
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+
output :value_out, {
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name: "o_#{full_name}", data_type: :logic, width: width,
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array_size: array_size, array_format: array_port_format
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}
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@@ -4,12 +4,12 @@ RgGen.define_list_item_feature(:bit_field, :type, :rwe) do
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sv_rtl do
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build do
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unless bit_field.reference?
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-
input :
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+
input :enable, {
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name: "i_#{full_name}_enable", data_type: :logic, width: 1,
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array_size: array_size, array_format: array_port_format
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}
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end
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-
output :
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+
output :value_out, {
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name: "o_#{full_name}", data_type: :logic, width: width,
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array_size: array_size, array_format: array_port_format
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}
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@@ -4,12 +4,12 @@ RgGen.define_list_item_feature(:bit_field, :type, :rwl) do
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sv_rtl do
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build do
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unless bit_field.reference?
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-
input :
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+
input :lock, {
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name: "i_#{full_name}_lock", data_type: :logic, width: 1,
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array_size: array_size, array_format: array_port_format
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}
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end
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-
output :
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+
output :value_out, {
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name: "o_#{full_name}", data_type: :logic, width: width,
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array_size: array_size, array_format: array_port_format
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}
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@@ -4,16 +4,16 @@ RgGen.define_list_item_feature(:bit_field, :type, :rws) do
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sv_rtl do
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build do
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unless bit_field.reference?
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-
input :
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+
input :set, {
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name: "i_#{full_name}_set", data_type: :logic, width: 1,
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array_size: array_size, array_format: array_port_format
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}
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end
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-
input :
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input :value_in, {
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name: "i_#{full_name}", data_type: :logic, width: width,
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array_size: array_size, array_format: array_port_format
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}
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-
output :
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output :value_out, {
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name: "o_#{full_name}", data_type: :logic, width: width,
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array_size: array_size, array_format: array_port_format
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}
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@@ -3,7 +3,7 @@
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RgGen.define_list_item_feature(:bit_field, :type, [:w0crs, :w1crs]) do
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sv_rtl do
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build do
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-
output :
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+
output :value_out, {
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name: "o_#{full_name}", data_type: :logic, width: width,
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array_size: array_size, array_format: array_port_format
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}
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@@ -3,7 +3,7 @@
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RgGen.define_list_item_feature(:bit_field, :type, [:w0src, :w1src]) do
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sv_rtl do
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build do
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-
output :
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output :value_out, {
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name: "o_#{full_name}", data_type: :logic, width: width,
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array_size: array_size, array_format: array_port_format
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}
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@@ -3,7 +3,7 @@
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RgGen.define_list_item_feature(:bit_field, :type, [:w0trg, :w1trg]) do
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sv_rtl do
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build do
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-
output :
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+
output :trigger, {
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name: "o_#{full_name}_trigger", data_type: :logic, width: width,
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array_size: array_size, array_format: array_port_format
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}
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@@ -6,43 +6,39 @@ module RgGen
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class Feature < Common::Feature
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private
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9
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-
def create_variable(data_type, attributes
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+
def create_variable(data_type, attributes, &block)
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DataObject.new(
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:variable, attributes.merge(data_type: data_type), &block
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)
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end
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-
def
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+
def create_if_instance(_, attributes, &block)
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InterfaceInstance.new(attributes, &block)
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end
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18
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-
def create_argument(direction, attributes
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+
def create_argument(direction, attributes, &block)
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DataObject.new(
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:argument, attributes.merge(direction: direction), &block
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)
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end
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-
def
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+
def create_if_port(_, attributes, &block)
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InterfacePort.new(attributes, &block)
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end
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28
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-
def create_parameter(parameter_type, attributes
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+
def create_parameter(parameter_type, attributes, &block)
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30
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DataObject.new(
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:parameter, attributes.merge(parameter_type: parameter_type), &block
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)
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end
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-
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-
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-
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-
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-
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-
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-
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-
[:localparam, :create_parameter, :parameter]
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-
].each do |entity, creation_method, declaration_type|
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-
define_entity(entity, creation_method, declaration_type)
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-
end
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+
define_entity :logic, :create_variable, :variable, -> { component }
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define_entity :interface, :create_if_instance, :variable, -> { component }
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define_entity :input, :create_argument, :port, -> { register_block }
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define_entity :output, :create_argument, :port, -> { register_block }
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+
define_entity :interface_port, :create_if_port, :port, -> { register_block }
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+
define_entity :parameter, :create_parameter, :parameter, -> { register_block }
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define_entity :localparam, :create_parameter, :parameter, -> { component }
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end
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end
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end
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@@ -0,0 +1,29 @@
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1
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+
# frozen_string_literal: true
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+
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+
module RgGen
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+
module SystemVerilog
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+
module RTL
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+
module PartialSum
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+
private
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+
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+
def partial_sums(operands)
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+
sums =
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+
operands
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.chunk(&method(:integer?))
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+
.flat_map(&method(:calc_partial_sum))
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+
.reject { |value| integer?(value) && value.zero? }
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sums.empty? && [0] || sums
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+
end
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+
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+
def calc_partial_sum(kind_ans_values)
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+
kind, values = kind_ans_values
|
20
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kind && values.sum || values
|
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+
end
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+
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+
def integer?(value)
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+
value.is_a?(Integer)
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+
end
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+
end
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end
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end
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+
end
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@@ -2,18 +2,11 @@
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2
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3
3
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RgGen.define_simple_feature(:register, :sv_rtl_top) do
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sv_rtl do
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-
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-
export :local_index
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-
export :loop_variables
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-
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-
pre_build do
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-
@base_index =
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-
register_block.registers.map(&:count).sum
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-
end
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+
include RgGen::SystemVerilog::RTL::RegisterIndex
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6
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|
14
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build do
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-
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-
interface :
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8
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+
unless register.bit_fields.empty?
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+
interface :bit_field_if, {
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name: 'bit_field_if',
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interface_type: 'rggen_bit_field_if',
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parameter_values: [register.width]
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@@ -21,62 +14,32 @@ RgGen.define_simple_feature(:register, :sv_rtl_top) do
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end
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15
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end
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-
main_code :
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+
main_code :register_file do
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18
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local_scope("g_#{register.name}") do |scope|
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26
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-
scope.top_scope
|
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+
scope.top_scope top_scope?
|
27
20
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scope.loop_size loop_size
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scope.variables variables
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scope.body(&method(:body_code))
|
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23
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end
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end
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25
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33
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-
def index(offset = nil)
|
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-
operands =
|
35
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-
register.array? ? [@base_index, offset || local_index] : [@base_index]
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36
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-
if operands.all? { |operand| operand.is_a?(Integer) }
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-
operands.sum
|
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-
else
|
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-
operands.join('+')
|
40
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-
end
|
41
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-
end
|
42
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-
|
43
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-
def local_index
|
44
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-
(register.array? || nil) &&
|
45
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-
loop_variables
|
46
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-
.zip(local_index_coefficients)
|
47
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-
.map { |v, c| [c, v].compact.join('*') }
|
48
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-
.join('+')
|
49
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-
end
|
50
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-
|
51
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-
def loop_variables
|
52
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-
(register.array? || nil) &&
|
53
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-
register.array_size.map.with_index(1) do |_size, i|
|
54
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-
create_identifier(loop_index(i))
|
55
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-
end
|
56
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-
end
|
57
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-
|
58
26
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private
|
59
27
|
|
60
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-
def
|
61
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-
|
62
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-
register.array_size.reverse.inject(1) do |total, size|
|
63
|
-
coefficients.unshift(coefficients.size.zero? ? nil : total)
|
64
|
-
total * size
|
65
|
-
end
|
66
|
-
coefficients
|
28
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+
def top_scope?
|
29
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+
register_file.nil?
|
67
30
|
end
|
68
31
|
|
69
32
|
def loop_size
|
70
33
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(register.array? || nil) &&
|
71
|
-
|
34
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+
local_loop_variables.zip(register.array_size).to_h
|
72
35
|
end
|
73
36
|
|
74
37
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def variables
|
75
|
-
register.declarations
|
38
|
+
register.declarations[:variable]
|
76
39
|
end
|
77
40
|
|
78
41
|
def body_code(code)
|
79
|
-
register.generate_code(:register, :top_down
|
42
|
+
register.generate_code(code, :register, :top_down)
|
80
43
|
end
|
81
44
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end
|
82
45
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end
|
@@ -3,6 +3,8 @@
|
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3
3
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RgGen.define_list_feature(:register, :type) do
|
4
4
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sv_rtl do
|
5
5
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base_feature do
|
6
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+
include RgGen::SystemVerilog::RTL::PartialSum
|
7
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+
|
6
8
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private
|
7
9
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|
8
10
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def readable
|
@@ -22,7 +24,29 @@ RgGen.define_list_feature(:register, :type) do
|
|
22
24
|
end
|
23
25
|
|
24
26
|
def offset_address
|
25
|
-
|
27
|
+
offsets = [*register_files, register].flat_map(&method(:collect_offsets))
|
28
|
+
offsets = partial_sums(offsets)
|
29
|
+
format_offsets(offsets)
|
30
|
+
end
|
31
|
+
|
32
|
+
def collect_offsets(component)
|
33
|
+
if component.register_file? && component.array?
|
34
|
+
[component.offset_address, byte_offset(component)]
|
35
|
+
else
|
36
|
+
component.offset_address
|
37
|
+
end
|
38
|
+
end
|
39
|
+
|
40
|
+
def byte_offset(component)
|
41
|
+
"#{component.byte_size(false)}*(#{component.local_index})"
|
42
|
+
end
|
43
|
+
|
44
|
+
def format_offsets(offsets)
|
45
|
+
offsets.map(&method(:format_offset)).join('+')
|
46
|
+
end
|
47
|
+
|
48
|
+
def format_offset(offset)
|
49
|
+
offset.is_a?(Integer) ? hex(offset, address_width) : offset
|
26
50
|
end
|
27
51
|
|
28
52
|
def width
|
@@ -4,45 +4,45 @@ RgGen.define_list_item_feature(:register, :type, :external) do
|
|
4
4
|
sv_rtl do
|
5
5
|
build do
|
6
6
|
if configuration.fold_sv_interface_port?
|
7
|
-
interface_port :
|
7
|
+
interface_port :bus_if, {
|
8
8
|
name: "#{register.name}_bus_if",
|
9
9
|
interface_type: 'rggen_bus_if',
|
10
10
|
modport: 'master'
|
11
11
|
}
|
12
12
|
else
|
13
|
-
output :
|
13
|
+
output :valid, {
|
14
14
|
name: "o_#{register.name}_valid",
|
15
15
|
data_type: :logic, width: 1
|
16
16
|
}
|
17
|
-
output :
|
17
|
+
output :access, {
|
18
18
|
name: "o_#{register.name}_access",
|
19
19
|
data_type: :logic, width: '$bits(rggen_access)'
|
20
20
|
}
|
21
|
-
output :
|
21
|
+
output :address, {
|
22
22
|
name: "o_#{register.name}_address",
|
23
23
|
data_type: :logic, width: address_width
|
24
24
|
}
|
25
|
-
output :
|
25
|
+
output :write_data, {
|
26
26
|
name: "o_#{register.name}_data",
|
27
27
|
data_type: :logic, width: bus_width
|
28
28
|
}
|
29
|
-
output :
|
29
|
+
output :strobe, {
|
30
30
|
name: "o_#{register.name}_strobe",
|
31
31
|
data_type: :logic, width: byte_width
|
32
32
|
}
|
33
|
-
input :
|
33
|
+
input :ready, {
|
34
34
|
name: "i_#{register.name}_ready",
|
35
35
|
data_type: :logic, width: 1
|
36
36
|
}
|
37
|
-
input :
|
37
|
+
input :status, {
|
38
38
|
name: "i_#{register.name}_status",
|
39
39
|
data_type: :logic, width: 2
|
40
40
|
}
|
41
|
-
input :
|
41
|
+
input :read_data, {
|
42
42
|
name: "i_#{register.name}_data",
|
43
43
|
data_type: :logic, width: bus_width
|
44
44
|
}
|
45
|
-
interface :
|
45
|
+
interface :bus_if, {
|
46
46
|
name: 'bus_if', interface_type: 'rggen_bus_if',
|
47
47
|
parameter_values: [address_width, bus_width],
|
48
48
|
variables: [
|
@@ -3,7 +3,7 @@
|
|
3
3
|
RgGen.define_list_item_feature(:register, :type, :indirect) do
|
4
4
|
sv_rtl do
|
5
5
|
build do
|
6
|
-
logic :
|
6
|
+
logic :indirect_index, { width: index_width }
|
7
7
|
end
|
8
8
|
|
9
9
|
main_code :register do |code|
|
@@ -23,7 +23,7 @@ RgGen.define_list_item_feature(:register, :type, :indirect) do
|
|
23
23
|
end
|
24
24
|
|
25
25
|
def index_values
|
26
|
-
loop_variables = register.
|
26
|
+
loop_variables = register.local_loop_variables
|
27
27
|
register.index_entries.zip(index_fields).map do |entry, field|
|
28
28
|
if entry.array_index?
|
29
29
|
loop_variables.shift[0, field.width]
|
@@ -65,10 +65,10 @@ RgGen.define_list_feature(:register_block, :protocol) do
|
|
65
65
|
|
66
66
|
base_feature do
|
67
67
|
build do
|
68
|
-
parameter :
|
68
|
+
parameter :error_status, {
|
69
69
|
name: 'ERROR_STATUS', data_type: :bit, width: 1, default: 0
|
70
70
|
}
|
71
|
-
parameter :
|
71
|
+
parameter :default_read_data, {
|
72
72
|
name: 'DEFAULT_READ_DATA', data_type: :bit, width: bus_width,
|
73
73
|
default: hex(0, bus_width)
|
74
74
|
}
|
@@ -22,42 +22,41 @@ RgGen.define_list_item_feature(:register_block, :protocol, :apb) do
|
|
22
22
|
sv_rtl do
|
23
23
|
build do
|
24
24
|
if configuration.fold_sv_interface_port?
|
25
|
-
interface_port :
|
25
|
+
interface_port :apb_if, {
|
26
26
|
name: 'apb_if', interface_type: 'rggen_apb_if', modport: 'slave'
|
27
27
|
}
|
28
28
|
else
|
29
|
-
input :
|
29
|
+
input :psel, {
|
30
30
|
name: 'i_psel', data_type: :logic, width: 1
|
31
31
|
}
|
32
|
-
input :
|
32
|
+
input :penable, {
|
33
33
|
name: 'i_penable', data_type: :logic, width: 1
|
34
34
|
}
|
35
|
-
input :
|
35
|
+
input :paddr, {
|
36
36
|
name: 'i_paddr', data_type: :logic, width: address_width
|
37
37
|
}
|
38
|
-
input :
|
38
|
+
input :pprot, {
|
39
39
|
name: 'i_pprot', data_type: :logic, width: 3
|
40
40
|
}
|
41
|
-
input :
|
41
|
+
input :pwrite, {
|
42
42
|
name: 'i_pwrite', data_type: :logic, width: 1
|
43
43
|
}
|
44
|
-
input :
|
45
|
-
name: 'i_pstrb', data_type: :logic,
|
46
|
-
width: byte_width
|
44
|
+
input :pstrb, {
|
45
|
+
name: 'i_pstrb', data_type: :logic, width: byte_width
|
47
46
|
}
|
48
|
-
input :
|
47
|
+
input :pwdata, {
|
49
48
|
name: 'i_pwdata', data_type: :logic, width: bus_width
|
50
49
|
}
|
51
|
-
output :
|
50
|
+
output :pready, {
|
52
51
|
name: 'o_pready', data_type: :logic, width: 1
|
53
52
|
}
|
54
|
-
output :
|
53
|
+
output :prdata, {
|
55
54
|
name: 'o_prdata', data_type: :logic, width: bus_width
|
56
55
|
}
|
57
|
-
output :
|
56
|
+
output :pslverr, {
|
58
57
|
name: 'o_pslverr', data_type: :logic, width: 1
|
59
58
|
}
|
60
|
-
interface :
|
59
|
+
interface :apb_if, {
|
61
60
|
name: 'apb_if', interface_type: 'rggen_apb_if',
|
62
61
|
parameter_values: [address_width, bus_width],
|
63
62
|
variables: [
|