rggen-systemverilog 0.19.0 → 0.20.0

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Files changed (53) hide show
  1. checksums.yaml +4 -4
  2. data/lib/rggen/systemverilog/common.rb +2 -2
  3. data/lib/rggen/systemverilog/common/component.rb +2 -6
  4. data/lib/rggen/systemverilog/common/feature.rb +39 -26
  5. data/lib/rggen/systemverilog/common/utility/interface_port.rb +7 -3
  6. data/lib/rggen/systemverilog/common/utility/local_scope.rb +2 -2
  7. data/lib/rggen/systemverilog/common/utility/structure_definition.rb +1 -3
  8. data/lib/rggen/systemverilog/ral.rb +4 -1
  9. data/lib/rggen/systemverilog/ral/bit_field/type.rb +15 -10
  10. data/lib/rggen/systemverilog/ral/bit_field/type/rwe_rwl.rb +1 -11
  11. data/lib/rggen/systemverilog/ral/feature.rb +4 -4
  12. data/lib/rggen/systemverilog/ral/register/type.rb +10 -52
  13. data/lib/rggen/systemverilog/ral/register/type/default.erb +1 -1
  14. data/lib/rggen/systemverilog/ral/register/type/external.rb +6 -10
  15. data/lib/rggen/systemverilog/ral/register/type/indirect.erb +3 -3
  16. data/lib/rggen/systemverilog/ral/register/type/indirect.rb +5 -2
  17. data/lib/rggen/systemverilog/ral/register_block/sv_ral_model.erb +8 -0
  18. data/lib/rggen/systemverilog/ral/register_block/sv_ral_model.rb +36 -0
  19. data/lib/rggen/systemverilog/ral/register_block/sv_ral_package.rb +1 -32
  20. data/lib/rggen/systemverilog/ral/register_common.rb +46 -0
  21. data/lib/rggen/systemverilog/ral/register_file/sv_ral_model.erb +8 -0
  22. data/lib/rggen/systemverilog/ral/register_file/sv_ral_model.rb +57 -0
  23. data/lib/rggen/systemverilog/ral/setup.rb +2 -1
  24. data/lib/rggen/systemverilog/rtl.rb +4 -1
  25. data/lib/rggen/systemverilog/rtl/bit_field/sv_rtl_top.rb +34 -19
  26. data/lib/rggen/systemverilog/rtl/bit_field/type.rb +1 -5
  27. data/lib/rggen/systemverilog/rtl/bit_field/type/rc_w0c_w1c.rb +3 -3
  28. data/lib/rggen/systemverilog/rtl/bit_field/type/ro.rb +1 -1
  29. data/lib/rggen/systemverilog/rtl/bit_field/type/rs_w0s_w1s.rb +2 -2
  30. data/lib/rggen/systemverilog/rtl/bit_field/type/rw_w1_wo_wo1.rb +1 -1
  31. data/lib/rggen/systemverilog/rtl/bit_field/type/rwc.rb +2 -2
  32. data/lib/rggen/systemverilog/rtl/bit_field/type/rwe.rb +2 -2
  33. data/lib/rggen/systemverilog/rtl/bit_field/type/rwl.rb +2 -2
  34. data/lib/rggen/systemverilog/rtl/bit_field/type/rws.rb +3 -3
  35. data/lib/rggen/systemverilog/rtl/bit_field/type/w0crs_w1crs.rb +1 -1
  36. data/lib/rggen/systemverilog/rtl/bit_field/type/w0src_w1src.rb +1 -1
  37. data/lib/rggen/systemverilog/rtl/bit_field/type/w0trg_w1trg.rb +1 -1
  38. data/lib/rggen/systemverilog/rtl/feature.rb +12 -16
  39. data/lib/rggen/systemverilog/rtl/partial_sum.rb +29 -0
  40. data/lib/rggen/systemverilog/rtl/register/sv_rtl_top.rb +10 -47
  41. data/lib/rggen/systemverilog/rtl/register/type.rb +25 -1
  42. data/lib/rggen/systemverilog/rtl/register/type/external.rb +10 -10
  43. data/lib/rggen/systemverilog/rtl/register/type/indirect.rb +2 -2
  44. data/lib/rggen/systemverilog/rtl/register_block/protocol.rb +2 -2
  45. data/lib/rggen/systemverilog/rtl/register_block/protocol/apb.rb +13 -14
  46. data/lib/rggen/systemverilog/rtl/register_block/protocol/axi4lite.rb +23 -25
  47. data/lib/rggen/systemverilog/rtl/register_block/sv_rtl_top.rb +11 -10
  48. data/lib/rggen/systemverilog/rtl/register_file/sv_rtl_top.rb +30 -0
  49. data/lib/rggen/systemverilog/rtl/register_index.rb +112 -0
  50. data/lib/rggen/systemverilog/rtl/setup.rb +1 -0
  51. data/lib/rggen/systemverilog/version.rb +1 -1
  52. metadata +11 -4
  53. data/lib/rggen/systemverilog/ral/register_block/sv_ral_block_model.erb +0 -11
@@ -3,7 +3,7 @@
3
3
  RgGen.define_list_item_feature(:bit_field, :type, [:rw, :w1, :wo, :wo1]) do
4
4
  sv_rtl do
5
5
  build do
6
- output :register_block, :value_out, {
6
+ output :value_out, {
7
7
  name: "o_#{full_name}", data_type: :logic, width: width,
8
8
  array_size: array_size, array_format: array_port_format
9
9
  }
@@ -4,12 +4,12 @@ RgGen.define_list_item_feature(:bit_field, :type, :rwc) do
4
4
  sv_rtl do
5
5
  build do
6
6
  unless bit_field.reference?
7
- input :register_block, :clear, {
7
+ input :clear, {
8
8
  name: "i_#{full_name}_clear", data_type: :logic, width: 1,
9
9
  array_size: array_size, array_format: array_port_format
10
10
  }
11
11
  end
12
- output :register_block, :value_out, {
12
+ output :value_out, {
13
13
  name: "o_#{full_name}", data_type: :logic, width: width,
14
14
  array_size: array_size, array_format: array_port_format
15
15
  }
@@ -4,12 +4,12 @@ RgGen.define_list_item_feature(:bit_field, :type, :rwe) do
4
4
  sv_rtl do
5
5
  build do
6
6
  unless bit_field.reference?
7
- input :register_block, :enable, {
7
+ input :enable, {
8
8
  name: "i_#{full_name}_enable", data_type: :logic, width: 1,
9
9
  array_size: array_size, array_format: array_port_format
10
10
  }
11
11
  end
12
- output :register_block, :value_out, {
12
+ output :value_out, {
13
13
  name: "o_#{full_name}", data_type: :logic, width: width,
14
14
  array_size: array_size, array_format: array_port_format
15
15
  }
@@ -4,12 +4,12 @@ RgGen.define_list_item_feature(:bit_field, :type, :rwl) do
4
4
  sv_rtl do
5
5
  build do
6
6
  unless bit_field.reference?
7
- input :register_block, :lock, {
7
+ input :lock, {
8
8
  name: "i_#{full_name}_lock", data_type: :logic, width: 1,
9
9
  array_size: array_size, array_format: array_port_format
10
10
  }
11
11
  end
12
- output :register_block, :value_out, {
12
+ output :value_out, {
13
13
  name: "o_#{full_name}", data_type: :logic, width: width,
14
14
  array_size: array_size, array_format: array_port_format
15
15
  }
@@ -4,16 +4,16 @@ RgGen.define_list_item_feature(:bit_field, :type, :rws) do
4
4
  sv_rtl do
5
5
  build do
6
6
  unless bit_field.reference?
7
- input :register_block, :set, {
7
+ input :set, {
8
8
  name: "i_#{full_name}_set", data_type: :logic, width: 1,
9
9
  array_size: array_size, array_format: array_port_format
10
10
  }
11
11
  end
12
- input :register_block, :value_in, {
12
+ input :value_in, {
13
13
  name: "i_#{full_name}", data_type: :logic, width: width,
14
14
  array_size: array_size, array_format: array_port_format
15
15
  }
16
- output :register_block, :value_out, {
16
+ output :value_out, {
17
17
  name: "o_#{full_name}", data_type: :logic, width: width,
18
18
  array_size: array_size, array_format: array_port_format
19
19
  }
@@ -3,7 +3,7 @@
3
3
  RgGen.define_list_item_feature(:bit_field, :type, [:w0crs, :w1crs]) do
4
4
  sv_rtl do
5
5
  build do
6
- output :register_block, :value_out, {
6
+ output :value_out, {
7
7
  name: "o_#{full_name}", data_type: :logic, width: width,
8
8
  array_size: array_size, array_format: array_port_format
9
9
  }
@@ -3,7 +3,7 @@
3
3
  RgGen.define_list_item_feature(:bit_field, :type, [:w0src, :w1src]) do
4
4
  sv_rtl do
5
5
  build do
6
- output :register_block, :value_out, {
6
+ output :value_out, {
7
7
  name: "o_#{full_name}", data_type: :logic, width: width,
8
8
  array_size: array_size, array_format: array_port_format
9
9
  }
@@ -3,7 +3,7 @@
3
3
  RgGen.define_list_item_feature(:bit_field, :type, [:w0trg, :w1trg]) do
4
4
  sv_rtl do
5
5
  build do
6
- output :register_block, :trigger, {
6
+ output :trigger, {
7
7
  name: "o_#{full_name}_trigger", data_type: :logic, width: width,
8
8
  array_size: array_size, array_format: array_port_format
9
9
  }
@@ -6,43 +6,39 @@ module RgGen
6
6
  class Feature < Common::Feature
7
7
  private
8
8
 
9
- def create_variable(data_type, attributes = {}, &block)
9
+ def create_variable(data_type, attributes, &block)
10
10
  DataObject.new(
11
11
  :variable, attributes.merge(data_type: data_type), &block
12
12
  )
13
13
  end
14
14
 
15
- def create_interface(_, attributes = {}, &block)
15
+ def create_if_instance(_, attributes, &block)
16
16
  InterfaceInstance.new(attributes, &block)
17
17
  end
18
18
 
19
- def create_argument(direction, attributes = {}, &block)
19
+ def create_argument(direction, attributes, &block)
20
20
  DataObject.new(
21
21
  :argument, attributes.merge(direction: direction), &block
22
22
  )
23
23
  end
24
24
 
25
- def create_interface_port(_, attributes = {}, &block)
25
+ def create_if_port(_, attributes, &block)
26
26
  InterfacePort.new(attributes, &block)
27
27
  end
28
28
 
29
- def create_parameter(parameter_type, attributes = {}, &block)
29
+ def create_parameter(parameter_type, attributes, &block)
30
30
  DataObject.new(
31
31
  :parameter, attributes.merge(parameter_type: parameter_type), &block
32
32
  )
33
33
  end
34
34
 
35
- [
36
- [:logic, :create_variable, :variable],
37
- [:interface, :create_interface, :variable],
38
- [:input, :create_argument, :port],
39
- [:output, :create_argument, :port],
40
- [:interface_port, :create_interface_port, :port],
41
- [:parameter, :create_parameter, :parameter],
42
- [:localparam, :create_parameter, :parameter]
43
- ].each do |entity, creation_method, declaration_type|
44
- define_entity(entity, creation_method, declaration_type)
45
- end
35
+ define_entity :logic, :create_variable, :variable, -> { component }
36
+ define_entity :interface, :create_if_instance, :variable, -> { component }
37
+ define_entity :input, :create_argument, :port, -> { register_block }
38
+ define_entity :output, :create_argument, :port, -> { register_block }
39
+ define_entity :interface_port, :create_if_port, :port, -> { register_block }
40
+ define_entity :parameter, :create_parameter, :parameter, -> { register_block }
41
+ define_entity :localparam, :create_parameter, :parameter, -> { component }
46
42
  end
47
43
  end
48
44
  end
@@ -0,0 +1,29 @@
1
+ # frozen_string_literal: true
2
+
3
+ module RgGen
4
+ module SystemVerilog
5
+ module RTL
6
+ module PartialSum
7
+ private
8
+
9
+ def partial_sums(operands)
10
+ sums =
11
+ operands
12
+ .chunk(&method(:integer?))
13
+ .flat_map(&method(:calc_partial_sum))
14
+ .reject { |value| integer?(value) && value.zero? }
15
+ sums.empty? && [0] || sums
16
+ end
17
+
18
+ def calc_partial_sum(kind_ans_values)
19
+ kind, values = kind_ans_values
20
+ kind && values.sum || values
21
+ end
22
+
23
+ def integer?(value)
24
+ value.is_a?(Integer)
25
+ end
26
+ end
27
+ end
28
+ end
29
+ end
@@ -2,18 +2,11 @@
2
2
 
3
3
  RgGen.define_simple_feature(:register, :sv_rtl_top) do
4
4
  sv_rtl do
5
- export :index
6
- export :local_index
7
- export :loop_variables
8
-
9
- pre_build do
10
- @base_index =
11
- register_block.registers.map(&:count).sum
12
- end
5
+ include RgGen::SystemVerilog::RTL::RegisterIndex
13
6
 
14
7
  build do
15
- if register.bit_fields?
16
- interface :register, :bit_field_if, {
8
+ unless register.bit_fields.empty?
9
+ interface :bit_field_if, {
17
10
  name: 'bit_field_if',
18
11
  interface_type: 'rggen_bit_field_if',
19
12
  parameter_values: [register.width]
@@ -21,62 +14,32 @@ RgGen.define_simple_feature(:register, :sv_rtl_top) do
21
14
  end
22
15
  end
23
16
 
24
- main_code :register_block do
17
+ main_code :register_file do
25
18
  local_scope("g_#{register.name}") do |scope|
26
- scope.top_scope
19
+ scope.top_scope top_scope?
27
20
  scope.loop_size loop_size
28
21
  scope.variables variables
29
22
  scope.body(&method(:body_code))
30
23
  end
31
24
  end
32
25
 
33
- def index(offset = nil)
34
- operands =
35
- register.array? ? [@base_index, offset || local_index] : [@base_index]
36
- if operands.all? { |operand| operand.is_a?(Integer) }
37
- operands.sum
38
- else
39
- operands.join('+')
40
- end
41
- end
42
-
43
- def local_index
44
- (register.array? || nil) &&
45
- loop_variables
46
- .zip(local_index_coefficients)
47
- .map { |v, c| [c, v].compact.join('*') }
48
- .join('+')
49
- end
50
-
51
- def loop_variables
52
- (register.array? || nil) &&
53
- register.array_size.map.with_index(1) do |_size, i|
54
- create_identifier(loop_index(i))
55
- end
56
- end
57
-
58
26
  private
59
27
 
60
- def local_index_coefficients
61
- coefficients = []
62
- register.array_size.reverse.inject(1) do |total, size|
63
- coefficients.unshift(coefficients.size.zero? ? nil : total)
64
- total * size
65
- end
66
- coefficients
28
+ def top_scope?
29
+ register_file.nil?
67
30
  end
68
31
 
69
32
  def loop_size
70
33
  (register.array? || nil) &&
71
- loop_variables.zip(register.array_size).to_h
34
+ local_loop_variables.zip(register.array_size).to_h
72
35
  end
73
36
 
74
37
  def variables
75
- register.declarations(:register, :variable)
38
+ register.declarations[:variable]
76
39
  end
77
40
 
78
41
  def body_code(code)
79
- register.generate_code(:register, :top_down, code)
42
+ register.generate_code(code, :register, :top_down)
80
43
  end
81
44
  end
82
45
  end
@@ -3,6 +3,8 @@
3
3
  RgGen.define_list_feature(:register, :type) do
4
4
  sv_rtl do
5
5
  base_feature do
6
+ include RgGen::SystemVerilog::RTL::PartialSum
7
+
6
8
  private
7
9
 
8
10
  def readable
@@ -22,7 +24,29 @@ RgGen.define_list_feature(:register, :type) do
22
24
  end
23
25
 
24
26
  def offset_address
25
- hex(register.offset_address, address_width)
27
+ offsets = [*register_files, register].flat_map(&method(:collect_offsets))
28
+ offsets = partial_sums(offsets)
29
+ format_offsets(offsets)
30
+ end
31
+
32
+ def collect_offsets(component)
33
+ if component.register_file? && component.array?
34
+ [component.offset_address, byte_offset(component)]
35
+ else
36
+ component.offset_address
37
+ end
38
+ end
39
+
40
+ def byte_offset(component)
41
+ "#{component.byte_size(false)}*(#{component.local_index})"
42
+ end
43
+
44
+ def format_offsets(offsets)
45
+ offsets.map(&method(:format_offset)).join('+')
46
+ end
47
+
48
+ def format_offset(offset)
49
+ offset.is_a?(Integer) ? hex(offset, address_width) : offset
26
50
  end
27
51
 
28
52
  def width
@@ -4,45 +4,45 @@ RgGen.define_list_item_feature(:register, :type, :external) do
4
4
  sv_rtl do
5
5
  build do
6
6
  if configuration.fold_sv_interface_port?
7
- interface_port :register_block, :bus_if, {
7
+ interface_port :bus_if, {
8
8
  name: "#{register.name}_bus_if",
9
9
  interface_type: 'rggen_bus_if',
10
10
  modport: 'master'
11
11
  }
12
12
  else
13
- output :register_block, :valid, {
13
+ output :valid, {
14
14
  name: "o_#{register.name}_valid",
15
15
  data_type: :logic, width: 1
16
16
  }
17
- output :register_block, :access, {
17
+ output :access, {
18
18
  name: "o_#{register.name}_access",
19
19
  data_type: :logic, width: '$bits(rggen_access)'
20
20
  }
21
- output :register_block, :address, {
21
+ output :address, {
22
22
  name: "o_#{register.name}_address",
23
23
  data_type: :logic, width: address_width
24
24
  }
25
- output :register_block, :write_data, {
25
+ output :write_data, {
26
26
  name: "o_#{register.name}_data",
27
27
  data_type: :logic, width: bus_width
28
28
  }
29
- output :register_block, :strobe, {
29
+ output :strobe, {
30
30
  name: "o_#{register.name}_strobe",
31
31
  data_type: :logic, width: byte_width
32
32
  }
33
- input :register_block, :ready, {
33
+ input :ready, {
34
34
  name: "i_#{register.name}_ready",
35
35
  data_type: :logic, width: 1
36
36
  }
37
- input :register_block, :status, {
37
+ input :status, {
38
38
  name: "i_#{register.name}_status",
39
39
  data_type: :logic, width: 2
40
40
  }
41
- input :register_block, :read_data, {
41
+ input :read_data, {
42
42
  name: "i_#{register.name}_data",
43
43
  data_type: :logic, width: bus_width
44
44
  }
45
- interface :register, :bus_if, {
45
+ interface :bus_if, {
46
46
  name: 'bus_if', interface_type: 'rggen_bus_if',
47
47
  parameter_values: [address_width, bus_width],
48
48
  variables: [
@@ -3,7 +3,7 @@
3
3
  RgGen.define_list_item_feature(:register, :type, :indirect) do
4
4
  sv_rtl do
5
5
  build do
6
- logic :register, :indirect_index, { width: index_width }
6
+ logic :indirect_index, { width: index_width }
7
7
  end
8
8
 
9
9
  main_code :register do |code|
@@ -23,7 +23,7 @@ RgGen.define_list_item_feature(:register, :type, :indirect) do
23
23
  end
24
24
 
25
25
  def index_values
26
- loop_variables = register.loop_variables
26
+ loop_variables = register.local_loop_variables
27
27
  register.index_entries.zip(index_fields).map do |entry, field|
28
28
  if entry.array_index?
29
29
  loop_variables.shift[0, field.width]
@@ -65,10 +65,10 @@ RgGen.define_list_feature(:register_block, :protocol) do
65
65
 
66
66
  base_feature do
67
67
  build do
68
- parameter :register_block, :error_status, {
68
+ parameter :error_status, {
69
69
  name: 'ERROR_STATUS', data_type: :bit, width: 1, default: 0
70
70
  }
71
- parameter :register_block, :default_read_data, {
71
+ parameter :default_read_data, {
72
72
  name: 'DEFAULT_READ_DATA', data_type: :bit, width: bus_width,
73
73
  default: hex(0, bus_width)
74
74
  }
@@ -22,42 +22,41 @@ RgGen.define_list_item_feature(:register_block, :protocol, :apb) do
22
22
  sv_rtl do
23
23
  build do
24
24
  if configuration.fold_sv_interface_port?
25
- interface_port :register_block, :apb_if, {
25
+ interface_port :apb_if, {
26
26
  name: 'apb_if', interface_type: 'rggen_apb_if', modport: 'slave'
27
27
  }
28
28
  else
29
- input :register_block, :psel, {
29
+ input :psel, {
30
30
  name: 'i_psel', data_type: :logic, width: 1
31
31
  }
32
- input :register_block, :penable, {
32
+ input :penable, {
33
33
  name: 'i_penable', data_type: :logic, width: 1
34
34
  }
35
- input :register_block, :paddr, {
35
+ input :paddr, {
36
36
  name: 'i_paddr', data_type: :logic, width: address_width
37
37
  }
38
- input :register_block, :pprot, {
38
+ input :pprot, {
39
39
  name: 'i_pprot', data_type: :logic, width: 3
40
40
  }
41
- input :register_block, :pwrite, {
41
+ input :pwrite, {
42
42
  name: 'i_pwrite', data_type: :logic, width: 1
43
43
  }
44
- input :register_block, :pstrb, {
45
- name: 'i_pstrb', data_type: :logic,
46
- width: byte_width
44
+ input :pstrb, {
45
+ name: 'i_pstrb', data_type: :logic, width: byte_width
47
46
  }
48
- input :register_block, :pwdata, {
47
+ input :pwdata, {
49
48
  name: 'i_pwdata', data_type: :logic, width: bus_width
50
49
  }
51
- output :register_block, :pready, {
50
+ output :pready, {
52
51
  name: 'o_pready', data_type: :logic, width: 1
53
52
  }
54
- output :register_block, :prdata, {
53
+ output :prdata, {
55
54
  name: 'o_prdata', data_type: :logic, width: bus_width
56
55
  }
57
- output :register_block, :pslverr, {
56
+ output :pslverr, {
58
57
  name: 'o_pslverr', data_type: :logic, width: 1
59
58
  }
60
- interface :register_block, :apb_if, {
59
+ interface :apb_if, {
61
60
  name: 'apb_if', interface_type: 'rggen_apb_if',
62
61
  parameter_values: [address_width, bus_width],
63
62
  variables: [