rggen-systemverilog 0.19.0 → 0.20.0
This diff represents the content of publicly available package versions that have been released to one of the supported registries. The information contained in this diff is provided for informational purposes only and reflects changes between package versions as they appear in their respective public registries.
- checksums.yaml +4 -4
- data/lib/rggen/systemverilog/common.rb +2 -2
- data/lib/rggen/systemverilog/common/component.rb +2 -6
- data/lib/rggen/systemverilog/common/feature.rb +39 -26
- data/lib/rggen/systemverilog/common/utility/interface_port.rb +7 -3
- data/lib/rggen/systemverilog/common/utility/local_scope.rb +2 -2
- data/lib/rggen/systemverilog/common/utility/structure_definition.rb +1 -3
- data/lib/rggen/systemverilog/ral.rb +4 -1
- data/lib/rggen/systemverilog/ral/bit_field/type.rb +15 -10
- data/lib/rggen/systemverilog/ral/bit_field/type/rwe_rwl.rb +1 -11
- data/lib/rggen/systemverilog/ral/feature.rb +4 -4
- data/lib/rggen/systemverilog/ral/register/type.rb +10 -52
- data/lib/rggen/systemverilog/ral/register/type/default.erb +1 -1
- data/lib/rggen/systemverilog/ral/register/type/external.rb +6 -10
- data/lib/rggen/systemverilog/ral/register/type/indirect.erb +3 -3
- data/lib/rggen/systemverilog/ral/register/type/indirect.rb +5 -2
- data/lib/rggen/systemverilog/ral/register_block/sv_ral_model.erb +8 -0
- data/lib/rggen/systemverilog/ral/register_block/sv_ral_model.rb +36 -0
- data/lib/rggen/systemverilog/ral/register_block/sv_ral_package.rb +1 -32
- data/lib/rggen/systemverilog/ral/register_common.rb +46 -0
- data/lib/rggen/systemverilog/ral/register_file/sv_ral_model.erb +8 -0
- data/lib/rggen/systemverilog/ral/register_file/sv_ral_model.rb +57 -0
- data/lib/rggen/systemverilog/ral/setup.rb +2 -1
- data/lib/rggen/systemverilog/rtl.rb +4 -1
- data/lib/rggen/systemverilog/rtl/bit_field/sv_rtl_top.rb +34 -19
- data/lib/rggen/systemverilog/rtl/bit_field/type.rb +1 -5
- data/lib/rggen/systemverilog/rtl/bit_field/type/rc_w0c_w1c.rb +3 -3
- data/lib/rggen/systemverilog/rtl/bit_field/type/ro.rb +1 -1
- data/lib/rggen/systemverilog/rtl/bit_field/type/rs_w0s_w1s.rb +2 -2
- data/lib/rggen/systemverilog/rtl/bit_field/type/rw_w1_wo_wo1.rb +1 -1
- data/lib/rggen/systemverilog/rtl/bit_field/type/rwc.rb +2 -2
- data/lib/rggen/systemverilog/rtl/bit_field/type/rwe.rb +2 -2
- data/lib/rggen/systemverilog/rtl/bit_field/type/rwl.rb +2 -2
- data/lib/rggen/systemverilog/rtl/bit_field/type/rws.rb +3 -3
- data/lib/rggen/systemverilog/rtl/bit_field/type/w0crs_w1crs.rb +1 -1
- data/lib/rggen/systemverilog/rtl/bit_field/type/w0src_w1src.rb +1 -1
- data/lib/rggen/systemverilog/rtl/bit_field/type/w0trg_w1trg.rb +1 -1
- data/lib/rggen/systemverilog/rtl/feature.rb +12 -16
- data/lib/rggen/systemverilog/rtl/partial_sum.rb +29 -0
- data/lib/rggen/systemverilog/rtl/register/sv_rtl_top.rb +10 -47
- data/lib/rggen/systemverilog/rtl/register/type.rb +25 -1
- data/lib/rggen/systemverilog/rtl/register/type/external.rb +10 -10
- data/lib/rggen/systemverilog/rtl/register/type/indirect.rb +2 -2
- data/lib/rggen/systemverilog/rtl/register_block/protocol.rb +2 -2
- data/lib/rggen/systemverilog/rtl/register_block/protocol/apb.rb +13 -14
- data/lib/rggen/systemverilog/rtl/register_block/protocol/axi4lite.rb +23 -25
- data/lib/rggen/systemverilog/rtl/register_block/sv_rtl_top.rb +11 -10
- data/lib/rggen/systemverilog/rtl/register_file/sv_rtl_top.rb +30 -0
- data/lib/rggen/systemverilog/rtl/register_index.rb +112 -0
- data/lib/rggen/systemverilog/rtl/setup.rb +1 -0
- data/lib/rggen/systemverilog/version.rb +1 -1
- metadata +11 -4
- data/lib/rggen/systemverilog/ral/register_block/sv_ral_block_model.erb +0 -11
checksums.yaml
CHANGED
@@ -1,7 +1,7 @@
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---
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SHA256:
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metadata.gz:
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data.tar.gz:
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metadata.gz: 2074da98933b8ffc3d433d76d62acf272535b39d75db5322d4268ff4e80a9aa2
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data.tar.gz: 17b8d6a0250efcf5f1f29f12445b1b08940b6abb2dc9811b77a5ed0865e92693
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SHA512:
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metadata.gz:
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data.tar.gz:
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metadata.gz: fcb60eb491c928338cc398fab428b80c3b3a132d3f6395b4ac73765d1503c2d403653d4285f8740079cc9f8155ef8d36042bf2c3f1b0d481fef2f3d08ab0a6f2
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data.tar.gz: 97f26f59a360bfcd36fb47e2aa1455396d5b93e978c3de18a0395cb65bbdeab5ac3820f28a57dec8401af836064b3aace1f34241541ef59bb8fbd236cdf0e896
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@@ -28,10 +28,10 @@ module RgGen
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def self.register_component(builder, name, feature_class)
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builder.output_component_registry(name) do
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register_component [
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:
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:root, :register_block, :register_file, :register, :bit_field
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] do |category|
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component Component, ComponentFactory
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feature feature_class, FeatureFactory if category != :
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feature feature_class, FeatureFactory if category != :root
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end
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end
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end
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module SystemVerilog
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module Common
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class Component < Core::OutputBase::Component
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def declarations
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[
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@features.each_value.map(&body),
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@children.map(&body)
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].flatten
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def declarations
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@declarations ||= Hash.new { |h, k| h[k] = [] }
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end
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def package_imports(domain)
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template_engine Core::OutputBase::ERBEngine
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EntityContext =
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Struct.new(:entity_type, :
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Struct.new(:entity_type, :method, :declaration_type, :default_layer)
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class << self
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private
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def define_entity(entity_type,
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def define_entity(entity_type, method, declaration_type, default_layer)
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context =
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EntityContext.new(entity_type,
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define_method(entity_type) do |
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EntityContext.new(entity_type, method, declaration_type, default_layer)
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define_method(entity_type) do |name, *args, &block|
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if args.size >= 3
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message = 'wrong number of arguments ' \
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"(given #{args.size + 1}, expected 1..3)"
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raise ArgumentError.new(message)
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end
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define_entity(context, name, args, &block)
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end
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end
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end
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def declarations(domain, type)
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@declarations[domain][type]
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end
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def package_imports(domain)
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@package_imports[domain]
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end
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def post_initialize
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super
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@declarations = Hash.new do |h0, k0|
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h0[k0] = Hash.new { |h1, k1| h1[k1] = [] }
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end
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@package_imports = Hash.new { |h, k| h[k] = [] }
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end
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def
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def define_entity(context, name, args, &block)
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layer, attributes = parse_entity_arguments(args)
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entity = create_entity(context, name, attributes, &block)
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add_entity(context, entity, name, layer)
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end
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def parse_entity_arguments(args)
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if args.empty?
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[nil, nil]
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elsif args.size == 1 && args.first.is_a?(Hash)
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[nil, args.first]
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elsif args.size == 1
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[args.first, nil]
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else
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args[0..1]
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end
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end
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def create_entity(context, name, attributes, &block)
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merged_attributes = { name: name }.merge(Hash(attributes))
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__send__(context.method, context.entity_type, merged_attributes, &block)
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end
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def add_entity(
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add_declaration(context,
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add_identifier(
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def add_entity(context, entity, name, layer)
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add_declaration(context, entity, layer)
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add_identifier(entity, name)
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end
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def add_declaration(context,
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def add_declaration(context, entity, layer)
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(layer || instance_exec(&context.default_layer))
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.declarations[context.declaration_type] << entity.declaration
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end
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def add_identifier(
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instance_variable_set("@#{name}", identifier)
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def add_identifier(entity, name)
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instance_variable_set("@#{name}", entity.identifier)
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attr_singleton_reader(name)
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export(name)
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end
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define_attribute :modport
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define_attribute :array_size
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def modport(
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@modport_name =
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def modport(name_and_ports, ports = nil)
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@modport_name, @modport_ports =
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if ports
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[name_and_ports, ports]
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else
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Array(name_and_ports)[0..1]
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end
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end
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def declaration
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module SystemVerilog
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module Common
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module Utility
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class StructureDefinition <
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Core::Utility::CodeUtility::StructureDefinition
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class StructureDefinition < Core::Utility::CodeUtility::StructureDefinition
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include Core::Utility::AttributeSetter
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def initialize(default_attributes = {}, &block)
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require_relative 'common'
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require_relative 'ral/feature'
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require_relative 'ral/register_common'
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module RgGen
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module SystemVerilog
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'ral/register/type',
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'ral/register/type/external',
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'ral/register/type/indirect',
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'ral/register_block/
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'ral/register_block/sv_ral_model',
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'ral/register_block/sv_ral_package',
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'ral/register_file/sv_ral_model'
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].freeze
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def self.version
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export :constructors
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build do
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variable :
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name: bit_field.name,
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array_size: array_size,
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random: true
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variable :ral_model, {
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name: bit_field.name, data_type: model_name,
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array_size: array_size, random: true
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}
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end
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def constructors
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(bit_field.sequence_size&.times || [nil]).map do |index|
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macro_call(
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:rggen_ral_create_field_model, arguments(index)
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)
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macro_call(:rggen_ral_create_field, arguments(index))
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end
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end
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def arguments(index)
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[
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ral_model[index], bit_field.lsb(index), bit_field.width,
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ral_model[index], bit_field.lsb(index), bit_field.width, string(access),
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volatile, reset_value(index), valid_reset, index || -1, string(reference)
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]
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end
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def valid_reset
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bit_field.initial_value? && 1 || 0
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end
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def reference
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if bit_field.reference?
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reference_field = bit_field.reference
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[reference_field.register.full_name('.'), reference_field.name].join('.')
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else
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''
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end
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end
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end
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default_feature do
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RgGen.define_list_item_feature(:bit_field, :type, [:rwe, :rwl]) do
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sv_ral do
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model_name do
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"rggen_ral_#{bit_field.type}_field
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end
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private
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def reference_names
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reference = bit_field.reference
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register = reference&.register
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[register&.name, reference&.name]
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.map { |name| string(name) }
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.join(', ')
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"rggen_ral_#{bit_field.type}_field"
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end
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end
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end
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class Feature < Common::Feature
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private
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def create_variable(_, attributes
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def create_variable(_, attributes, &block)
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DataObject.new(
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:variable, attributes.merge(array_format: :unpacked), &block
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)
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end
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def create_parameter(_, attributes
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def create_parameter(_, attributes, &block)
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DataObject.new(:parameter, attributes, &block)
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end
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define_entity :variable, :create_variable, :variable
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define_entity :parameter, :create_parameter, :parameter
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define_entity :variable, :create_variable, :variable, -> { component.parent }
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define_entity :parameter, :create_parameter, :parameter, -> { component.parent }
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end
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end
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end
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RgGen.define_list_feature(:register, :type) do
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sv_ral do
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base_feature do
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include RgGen::SystemVerilog::RAL::RegisterCommon
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define_helpers do
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def model_name(&body)
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@model_name = body if block_given?
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@offset_address
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end
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def unmapped
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@unmapped = true
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end
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def unmapped?
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end
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def constructor(&body)
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@constructor = body if block_given?
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@constructor
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export :constructors
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build do
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variable :
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name: register.name,
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array_size: register.array_size,
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random: true
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variable :ral_model, {
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name: register.name, data_type: model_name,
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+
array_size: register.array_size, random: true
|
39
31
|
}
|
40
32
|
end
|
41
33
|
|
42
34
|
def constructors
|
43
|
-
|
44
|
-
constructor_code(array_index, i)
|
45
|
-
end
|
35
|
+
array_indices.map.with_index(&method(:constructor_code))
|
46
36
|
end
|
47
37
|
|
48
38
|
private
|
@@ -51,45 +41,25 @@ RgGen.define_list_feature(:register, :type) do
|
|
51
41
|
if helper.model_name
|
52
42
|
instance_eval(&helper.model_name)
|
53
43
|
else
|
54
|
-
"#{register.
|
44
|
+
"#{register.full_name('_')}_reg_model"
|
55
45
|
end
|
56
46
|
end
|
57
47
|
|
58
|
-
def array_index_list
|
59
|
-
(register.array? || nil) &&
|
60
|
-
begin
|
61
|
-
index_table = register.array_size.map { |size| (0...size).to_a }
|
62
|
-
index_table[0].product(*index_table[1..-1])
|
63
|
-
end
|
64
|
-
end
|
65
|
-
|
66
48
|
def constructor_code(array_index, index)
|
67
49
|
if helper.constructor
|
68
50
|
instance_exec(array_index, index, &helper.constructor)
|
69
51
|
else
|
70
|
-
macro_call(
|
71
|
-
:rggen_ral_create_reg_model, arguments(array_index, index)
|
72
|
-
)
|
52
|
+
macro_call(:rggen_ral_create_reg, arguments(array_index, index))
|
73
53
|
end
|
74
54
|
end
|
75
55
|
|
76
56
|
def arguments(array_index, index)
|
77
57
|
[
|
78
58
|
ral_model[array_index], array(array_index), offset_address(index),
|
79
|
-
access_rights,
|
59
|
+
string(access_rights), string(hdl_path(array_index))
|
80
60
|
]
|
81
61
|
end
|
82
62
|
|
83
|
-
def offset_address(index = 0)
|
84
|
-
address =
|
85
|
-
if helper.offset_address
|
86
|
-
instance_exec(index, &helper.offset_address)
|
87
|
-
else
|
88
|
-
register.offset_address + register.byte_width * index
|
89
|
-
end
|
90
|
-
hex(address, register_block.local_address_width)
|
91
|
-
end
|
92
|
-
|
93
63
|
def access_rights
|
94
64
|
if read_only?
|
95
65
|
'RO'
|
@@ -108,20 +78,8 @@ RgGen.define_list_feature(:register, :type) do
|
|
108
78
|
register.writable? && !register.readable?
|
109
79
|
end
|
110
80
|
|
111
|
-
def unmapped
|
112
|
-
helper.unmapped? && 1 || 0
|
113
|
-
end
|
114
|
-
|
115
|
-
def hdl_path(array_index)
|
116
|
-
[
|
117
|
-
"g_#{register.name}",
|
118
|
-
*Array(array_index).map { |i| "g[#{i}]" },
|
119
|
-
'u_register'
|
120
|
-
].join('.')
|
121
|
-
end
|
122
|
-
|
123
81
|
def variables
|
124
|
-
register.declarations
|
82
|
+
register.declarations[:variable]
|
125
83
|
end
|
126
84
|
|
127
85
|
def field_model_constructors
|
@@ -3,15 +3,11 @@
|
|
3
3
|
RgGen.define_list_item_feature(:register, :type, :external) do
|
4
4
|
sv_ral do
|
5
5
|
build do
|
6
|
-
parameter :
|
7
|
-
name: model_name,
|
8
|
-
data_type: 'type',
|
9
|
-
default: 'rggen_ral_block'
|
6
|
+
parameter :model_type, {
|
7
|
+
name: model_name, data_type: 'type', default: 'rggen_ral_block'
|
10
8
|
}
|
11
|
-
parameter :
|
12
|
-
name: "INTEGRATE_#{model_name}",
|
13
|
-
data_type: 'bit',
|
14
|
-
default: 1
|
9
|
+
parameter :integrate_model, {
|
10
|
+
name: "INTEGRATE_#{model_name}", data_type: 'bit', default: 1
|
15
11
|
}
|
16
12
|
end
|
17
13
|
|
@@ -19,8 +15,8 @@ RgGen.define_list_item_feature(:register, :type, :external) do
|
|
19
15
|
|
20
16
|
constructor do
|
21
17
|
macro_call(
|
22
|
-
'
|
23
|
-
[ral_model, offset_address, 'this', integrate_model]
|
18
|
+
'rggen_ral_create_block',
|
19
|
+
[ral_model, offset_address(0), 'this', integrate_model]
|
24
20
|
)
|
25
21
|
end
|
26
22
|
end
|