rggen-systemverilog 0.17.0 → 0.21.1

data/lib/rggen/systemverilog/rtl/setup.rb

@@ -8,6 +8,7 @@ RgGen.setup :'rggen-sv-rtl', RgGen::SystemVerilog::RTL do |builder|
   ]
   builder.enable :register_block, [:sv_rtl_top, :protocol]
   builder.enable :register_block, :protocol, [:apb, :axi4lite]
+  builder.enable :register_file, [:sv_rtl_top]
   builder.enable :register, [:sv_rtl_top]
   builder.enable :bit_field, [:sv_rtl_top]
 end

data/lib/rggen/systemverilog/version.rb

@@ -2,6 +2,6 @@
 
 module RgGen
   module SystemVerilog
-    VERSION = '0.17.0'
+    VERSION = '0.21.1'
   end
 end

metadata

@@ -1,14 +1,14 @@
 --- !ruby/object:Gem::Specification
 name: rggen-systemverilog
 version: !ruby/object:Gem::Version
-  version: 0.17.0
+  version: 0.21.1
 platform: ruby
 authors:
 - Taichi Ishitani
 autorequire: 
 bindir: bin
 cert_chain: []
-date: 2019-11-13 00:00:00.000000000 Z
+date: 2020-07-24 00:00:00.000000000 Z
 dependencies:
 - !ruby/object:Gem::Dependency
   name: docile
@@ -54,7 +54,7 @@ dependencies:
         version: '0'
 description: 'SystemVerilog RTL and UVM RAL model generators for RgGen.
 
-'
+  '
 email:
 - rggen@googlegroups.com
 executables: []
@@ -93,8 +93,12 @@ files:
 - lib/rggen/systemverilog/ral/register/type/external.rb
 - lib/rggen/systemverilog/ral/register/type/indirect.erb
 - lib/rggen/systemverilog/ral/register/type/indirect.rb
-- lib/rggen/systemverilog/ral/register_block/sv_ral_block_model.erb
+- lib/rggen/systemverilog/ral/register_block/sv_ral_model.erb
+- lib/rggen/systemverilog/ral/register_block/sv_ral_model.rb
 - lib/rggen/systemverilog/ral/register_block/sv_ral_package.rb
+- lib/rggen/systemverilog/ral/register_common.rb
+- lib/rggen/systemverilog/ral/register_file/sv_ral_model.erb
+- lib/rggen/systemverilog/ral/register_file/sv_ral_model.rb
 - lib/rggen/systemverilog/ral/setup.rb
 - lib/rggen/systemverilog/rtl.rb
 - lib/rggen/systemverilog/rtl/bit_field/sv_rtl_top.rb
@@ -109,8 +113,8 @@ files:
 - lib/rggen/systemverilog/rtl/bit_field/type/rof.rb
 - lib/rggen/systemverilog/rtl/bit_field/type/rs_w0s_w1s.erb
 - lib/rggen/systemverilog/rtl/bit_field/type/rs_w0s_w1s.rb
-- lib/rggen/systemverilog/rtl/bit_field/type/rw_wo.erb
-- lib/rggen/systemverilog/rtl/bit_field/type/rw_wo.rb
+- lib/rggen/systemverilog/rtl/bit_field/type/rw_w1_wo_wo1.erb
+- lib/rggen/systemverilog/rtl/bit_field/type/rw_w1_wo_wo1.rb
 - lib/rggen/systemverilog/rtl/bit_field/type/rwc.erb
 - lib/rggen/systemverilog/rtl/bit_field/type/rwc.rb
 - lib/rggen/systemverilog/rtl/bit_field/type/rwe.erb
@@ -128,6 +132,7 @@ files:
 - lib/rggen/systemverilog/rtl/feature.rb
 - lib/rggen/systemverilog/rtl/global/array_port_format.rb
 - lib/rggen/systemverilog/rtl/global/fold_sv_interface_port.rb
+- lib/rggen/systemverilog/rtl/partial_sum.rb
 - lib/rggen/systemverilog/rtl/register/sv_rtl_top.rb
 - lib/rggen/systemverilog/rtl/register/type.rb
 - lib/rggen/systemverilog/rtl/register/type/default.erb
@@ -142,6 +147,8 @@ files:
 - lib/rggen/systemverilog/rtl/register_block/protocol/axi4lite.rb
 - lib/rggen/systemverilog/rtl/register_block/sv_rtl_macros.erb
 - lib/rggen/systemverilog/rtl/register_block/sv_rtl_top.rb
+- lib/rggen/systemverilog/rtl/register_file/sv_rtl_top.rb
+- lib/rggen/systemverilog/rtl/register_index.rb
 - lib/rggen/systemverilog/rtl/setup.rb
 - lib/rggen/systemverilog/version.rb
 homepage: https://github.com/rggen/rggen-systemverilog
@@ -160,15 +167,15 @@ required_ruby_version: !ruby/object:Gem::Requirement
   requirements:
   - - ">="
     - !ruby/object:Gem::Version
-      version: '2.3'
+      version: '2.4'
 required_rubygems_version: !ruby/object:Gem::Requirement
   requirements:
   - - ">="
     - !ruby/object:Gem::Version
       version: '0'
 requirements: []
-rubygems_version: 3.0.3
+rubygems_version: 3.1.2
 signing_key: 
 specification_version: 4
-summary: rggen-systemverilog-0.17.0
+summary: rggen-systemverilog-0.21.1
 test_files: []

data/lib/rggen/systemverilog/ral/register_block/sv_ral_block_model.erb

@@ -1,11 +0,0 @@
-function new(string name);
-  super.new(name);
-endfunction
-function void build();
-<% reg_model_constructors.each do |constructor| %>
-  <%= constructor %>
-<% end %>
-endfunction
-function uvm_reg_map create_default_map();
-  return create_map("default_map", 0, <%= byte_width %>, UVM_LITTLE_ENDIAN, 1);
-endfunction

data/lib/rggen/systemverilog/rtl/bit_field/type/rw_wo.rb

@@ -1,14 +0,0 @@
-# frozen_string_literal: true
-
-RgGen.define_list_item_feature(:bit_field, :type, [:rw, :wo]) do
-  sv_rtl do
-    build do
-      output :register_block, :value_out, {
-        name: "o_#{full_name}", data_type: :logic, width: width,
-        array_size: array_size, array_format: array_port_format
-      }
-    end
-
-    main_code :bit_field, from_template: true
-  end
-end