rggen-systemverilog 0.17.0 → 0.21.1

checksums.yaml

@@ -1,7 +1,7 @@
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data/LICENSE

@@ -1,6 +1,6 @@
 The MIT License (MIT)
 
-Copyright (c) 2019 Taichi Ishitani
+Copyright (c) 2019-2020 Taichi Ishitani
 
 Permission is hereby granted, free of charge, to any person obtaining a copy
 of this software and associated documentation files (the "Software"), to deal

data/README.md

@@ -1,5 +1,5 @@
 [![Gem Version](https://badge.fury.io/rb/rggen-systemverilog.svg)](https://badge.fury.io/rb/rggen-systemverilog)
-[![Build Status](https://travis-ci.com/rggen/rggen-systemverilog.svg?branch=master)](https://travis-ci.com/rggen/rggen-systemverilog)
+[![CI](https://github.com/rggen/rggen-systemverilog/workflows/CI/badge.svg)](https://github.com/rggen/rggen-systemverilog/actions?query=workflow%3ACI)
 [![Maintainability](https://api.codeclimate.com/v1/badges/88086c5be538a1564a35/maintainability)](https://codeclimate.com/github/rggen/rggen-systemverilog/maintainability)
 [![codecov](https://codecov.io/gh/rggen/rggen-systemverilog/branch/master/graph/badge.svg)](https://codecov.io/gh/rggen/rggen-systemverilog)
 [![Quality Gate Status](https://sonarcloud.io/api/project_badges/measure?project=rggen_rggen-systemverilog&metric=alert_status)](https://sonarcloud.io/dashboard?id=rggen_rggen-systemverilog)
@@ -34,7 +34,7 @@ Feedbacks, bug reports, questions and etc. are wellcome! You can post them by us
 
 ## Copyright & License
 
-Copyright © 2019 Taichi Ishitani. RgGen::SystemVerilog is licensed under the [MIT License](https://opensource.org/licenses/MIT), see [LICENSE](LICENSE) for futher details.
+Copyright © 2019-2020 Taichi Ishitani. RgGen::SystemVerilog is licensed under the [MIT License](https://opensource.org/licenses/MIT), see [LICENSE](LICENSE) for futher details.
 
 ## Code of Conduct
 

data/lib/rggen/systemverilog/common.rb

@@ -28,10 +28,10 @@ module RgGen
       def self.register_component(builder, name, feature_class)
         builder.output_component_registry(name) do
           register_component [
-            :register_map, :register_block, :register, :bit_field
+            :root, :register_block, :register_file, :register, :bit_field
           ] do |category|
             component Component, ComponentFactory
-            feature feature_class, FeatureFactory if category != :register_map
+            feature feature_class, FeatureFactory if category != :root
           end
         end
       end

data/lib/rggen/systemverilog/common/component.rb

@@ -4,12 +4,8 @@ module RgGen
   module SystemVerilog
     module Common
       class Component < Core::OutputBase::Component
-        def declarations(domain, type)
-          body = ->(r) { r.declarations(domain, type) }
-          [
-            @features.each_value.map(&body),
-            @children.map(&body)
-          ].flatten
+        def declarations
+          @declarations ||= Hash.new { |h, k| h[k] = [] }
         end
 
         def package_imports(domain)

data/lib/rggen/systemverilog/common/feature.rb

@@ -8,26 +8,25 @@ module RgGen
         template_engine Core::OutputBase::ERBEngine
 
         EntityContext =
-          Struct.new(:entity_type, :creation_method, :declaration_type)
+          Struct.new(:entity_type, :method, :declaration_type, :default_layer)
 
         class << self
           private
 
-          def define_entity(entity_type, creation_method, declaration_type)
+          def define_entity(entity_type, method, declaration_type, default_layer)
             context =
-              EntityContext.new(entity_type, creation_method, declaration_type)
-            define_method(entity_type) do |domain, name, **attributes, &block|
-              entity =
-                create_entity(context, { name: name }.merge(attributes), block)
-              add_entity(entity, context, domain, name)
+              EntityContext.new(entity_type, method, declaration_type, default_layer)
+            define_method(entity_type) do |name, *args, &block|
+              if args.size >= 3
+                message = 'wrong number of arguments ' \
+                          "(given #{args.size + 1}, expected 1..3)"
+                raise ArgumentError.new(message)
+              end
+              define_entity(context, name, args, &block)
             end
           end
         end
 
-        def declarations(domain, type)
-          @declarations[domain][type]
-        end
-
         def package_imports(domain)
           @package_imports[domain]
         end
@@ -36,30 +35,44 @@ module RgGen
 
         def post_initialize
           super
-          @declarations = Hash.new do |h0, k0|
-            h0[k0] = Hash.new { |h1, k1| h1[k1] = [] }
-          end
           @package_imports = Hash.new { |h, k| h[k] = [] }
         end
 
-        def create_entity(context, attributes, block)
-          creation_method = context.creation_method
-          entity_type = context.entity_type
-          __send__(creation_method, entity_type, attributes, block)
+        def define_entity(context, name, args, &block)
+          layer, attributes = parse_entity_arguments(args)
+          entity = create_entity(context, name, attributes, &block)
+          add_entity(context, entity, name, layer)
+        end
+
+        def parse_entity_arguments(args)
+          if args.empty?
+            [nil, nil]
+          elsif args.size == 1 && args.first.is_a?(Hash)
+            [nil, args.first]
+          elsif args.size == 1
+            [args.first, nil]
+          else
+            args[0..1]
+          end
+        end
+
+        def create_entity(context, name, attributes, &block)
+          merged_attributes = { name: name }.merge(Hash(attributes))
+          __send__(context.method, context.entity_type, merged_attributes, &block)
         end
 
-        def add_entity(entity, context, domain, name)
-          add_declaration(context, domain, entity.declaration)
-          add_identifier(name, entity.identifier)
+        def add_entity(context, entity, name, layer)
+          add_declaration(context, entity, layer)
+          add_identifier(entity, name)
         end
 
-        def add_declaration(context, domain, declaration)
-          declaration_type = context.declaration_type
-          @declarations[domain][declaration_type] << declaration
+        def add_declaration(context, entity, layer)
+          (layer || instance_exec(&context.default_layer))
+            .declarations[context.declaration_type] << entity.declaration
         end
 
-        def add_identifier(name, identifier)
-          instance_variable_set("@#{name}", identifier)
+        def add_identifier(entity, name)
+          instance_variable_set("@#{name}", entity.identifier)
           attr_singleton_reader(name)
           export(name)
         end

data/lib/rggen/systemverilog/common/utility.rb

@@ -45,6 +45,10 @@ module RgGen
           end
         end
 
+        def all_bits_0
+          "'0"
+        end
+
         def bin(value, width = nil)
           if width
             width = bit_width(value, width)
@@ -79,7 +83,7 @@ module RgGen
           [width, bit_length].max
         end
 
-        def argument(name, **attribute)
+        def argument(name, attribute = {})
           DataObject.new(:argument, attribute.merge(name: name)).declaration
         end
 
@@ -90,7 +94,7 @@ module RgGen
           module_definition: ModuleDefinition,
           package_definition: PackageDefinition
         }.each do |method_name, definition|
-          define_method(method_name) do |name, **attributes, &block|
+          define_method(method_name) do |name, attributes = {}, &block|
             definition.new(attributes.merge(name: name), &block).to_code
           end
         end

data/lib/rggen/systemverilog/common/utility/data_object.rb

@@ -7,9 +7,9 @@ module RgGen
         class DataObject
           include Core::Utility::AttributeSetter
 
-          def initialize(object_type, **default_attributes)
+          def initialize(object_type, default_attributes = {})
             @object_type = object_type
-            apply_attributes(default_attributes)
+            apply_attributes(**default_attributes)
             block_given? && yield(self)
           end
 

data/lib/rggen/systemverilog/common/utility/interface_instance.rb

@@ -7,8 +7,8 @@ module RgGen
         class InterfaceInstance
           include Core::Utility::AttributeSetter
 
-          def initialize(**default_attributes)
-            apply_attributes(default_attributes)
+          def initialize(default_attributes = {})
+            apply_attributes(**default_attributes)
             block_given? && yield(self)
           end
 

data/lib/rggen/systemverilog/common/utility/interface_port.rb

@@ -7,8 +7,8 @@ module RgGen
         class InterfacePort
           include Core::Utility::AttributeSetter
 
-          def initialize(**default_attributes)
-            apply_attributes(default_attributes)
+          def initialize(default_attributes = {})
+            apply_attributes(**default_attributes)
             block_given? && yield(self)
           end
 
@@ -17,9 +17,13 @@ module RgGen
           define_attribute :modport
           define_attribute :array_size
 
-          def modport(name, ports = nil)
-            @modport_name = name
-            @modport_ports = ports
+          def modport(name_and_ports, ports = nil)
+            @modport_name, @modport_ports =
+              if ports
+                [name_and_ports, ports]
+              else
+                Array(name_and_ports)[0..1]
+              end
           end
 
           def declaration

data/lib/rggen/systemverilog/common/utility/local_scope.rb

@@ -10,8 +10,8 @@ module RgGen
           define_attribute :variables
           define_attribute :loop_size
 
-          def top_scope
-            @top_scope = true
+          def top_scope(value = true)
+            @top_scope = value
           end
 
           private

data/lib/rggen/systemverilog/common/utility/structure_definition.rb

@@ -4,13 +4,11 @@ module RgGen
   module SystemVerilog
     module Common
       module Utility
-        class StructureDefinition <
-          Core::Utility::CodeUtility::StructureDefinition
-
+        class StructureDefinition < Core::Utility::CodeUtility::StructureDefinition
           include Core::Utility::AttributeSetter
 
-          def initialize(**default_attributes, &block)
-            apply_attributes(default_attributes)
+          def initialize(default_attributes = {}, &block)
+            apply_attributes(**default_attributes)
             super(&block)
           end
 

data/lib/rggen/systemverilog/ral.rb

@@ -2,6 +2,7 @@
 
 require_relative 'common'
 require_relative 'ral/feature'
+require_relative 'ral/register_common'
 
 module RgGen
   module SystemVerilog
@@ -15,7 +16,9 @@ module RgGen
         'ral/register/type',
         'ral/register/type/external',
         'ral/register/type/indirect',
-        'ral/register_block/sv_ral_package'
+        'ral/register_block/sv_ral_model',
+        'ral/register_block/sv_ral_package',
+        'ral/register_file/sv_ral_model'
       ].freeze
 
       def self.version

data/lib/rggen/systemverilog/ral/bit_field/type.rb

@@ -17,11 +17,9 @@ RgGen.define_list_feature(:bit_field, :type) do
       export :constructors
 
       build do
-        variable :register, :ral_model, {
-          name: bit_field.name,
-          data_type: model_name,
-          array_size: array_size,
-          random: true
+        variable :ral_model, {
+          name: bit_field.name, data_type: model_name,
+          array_size: array_size, random: true
         }
       end
 
@@ -36,9 +34,7 @@ RgGen.define_list_feature(:bit_field, :type) do
 
       def constructors
         (bit_field.sequence_size&.times || [nil]).map do |index|
-          macro_call(
-            :rggen_ral_create_field_model, arguments(index)
-          )
+          macro_call(:rggen_ral_create_field, arguments(index))
         end
       end
 
@@ -50,8 +46,8 @@ RgGen.define_list_feature(:bit_field, :type) do
 
       def arguments(index)
         [
-          ral_model[index], bit_field.lsb(index), bit_field.width,
-          access, volatile, reset_value(index), valid_reset
+          ral_model[index], bit_field.lsb(index), bit_field.width, string(access),
+          volatile, reset_value(index), valid_reset, index || -1, string(reference)
         ]
       end
 
@@ -68,6 +64,15 @@ RgGen.define_list_feature(:bit_field, :type) do
       def valid_reset
         bit_field.initial_value? && 1 || 0
       end
+
+      def reference
+        if bit_field.reference?
+          reference_field = bit_field.reference
+          [reference_field.register.full_name('.'), reference_field.name].join('.')
+        else
+          ''
+        end
+      end
     end
 
     default_feature do

data/lib/rggen/systemverilog/ral/bit_field/type/rwe_rwl.rb

@@ -3,17 +3,7 @@
 RgGen.define_list_item_feature(:bit_field, :type, [:rwe, :rwl]) do
   sv_ral do
     model_name do
-      "rggen_ral_#{bit_field.type}_field #(#{reference_names})"
-    end
-
-    private
-
-    def reference_names
-      reference = bit_field.reference
-      register = reference&.register
-      [register&.name, reference&.name]
-        .map { |name| string(name) }
-        .join(', ')
+      "rggen_ral_#{bit_field.type}_field"
     end
   end
 end

data/lib/rggen/systemverilog/ral/feature.rb

@@ -6,20 +6,18 @@ module RgGen
       class Feature < Common::Feature
         private
 
-        def create_variable(_, attributes, block)
+        def create_variable(_, attributes, &block)
           DataObject.new(
             :variable, attributes.merge(array_format: :unpacked), &block
           )
         end
 
-        def create_parameter(_, attributes, block)
-          DataObject.new(
-            :parameter, attributes, &block
-          )
+        def create_parameter(_, attributes, &block)
+          DataObject.new(:parameter, attributes, &block)
         end
 
-        define_entity :variable, :create_variable, :variable
-        define_entity :parameter, :create_parameter, :parameter
+        define_entity :variable, :create_variable, :variable, -> { component.parent }
+        define_entity :parameter, :create_parameter, :parameter, -> { component.parent }
       end
     end
   end

data/lib/rggen/systemverilog/ral/register/type.rb

@@ -3,6 +3,8 @@
 RgGen.define_list_feature(:register, :type) do
   sv_ral do
     base_feature do
+      include RgGen::SystemVerilog::RAL::RegisterCommon
+
       define_helpers do
         def model_name(&body)
           @model_name = body if block_given?
@@ -14,14 +16,6 @@ RgGen.define_list_feature(:register, :type) do
           @offset_address
         end
 
-        def unmapped
-          @unmapped = true
-        end
-
-        def unmapped?
-          !@unmapped.nil?
-        end
-
         def constructor(&body)
           @constructor = body if block_given?
           @constructor
@@ -31,18 +25,14 @@ RgGen.define_list_feature(:register, :type) do
       export :constructors
 
       build do
-        variable :register_block, :ral_model, {
-          name: register.name,
-          data_type: model_name,
-          array_size: register.array_size,
-          random: true
+        variable :ral_model, {
+          name: register.name, data_type: model_name,
+          array_size: register.array_size, random: true
         }
       end
 
       def constructors
-        (array_index_list || [nil]).map.with_index do |array_index, i|
-          constructor_code(array_index, i)
-        end
+        array_indices.map.with_index(&method(:constructor_code))
       end
 
       private
@@ -51,45 +41,25 @@ RgGen.define_list_feature(:register, :type) do
         if helper.model_name
           instance_eval(&helper.model_name)
         else
-          "#{register.name}_reg_model"
+          "#{register.full_name('_')}_reg_model"
         end
       end
 
-      def array_index_list
-        (register.array? || nil) &&
-          begin
-            index_table = register.array_size.map { |size| (0...size).to_a }
-            index_table[0].product(*index_table[1..-1])
-          end
-      end
-
       def constructor_code(array_index, index)
         if helper.constructor
           instance_exec(array_index, index, &helper.constructor)
         else
-          macro_call(
-            :rggen_ral_create_reg_model, arguments(array_index, index)
-          )
+          macro_call(:rggen_ral_create_reg, arguments(array_index, index))
         end
       end
 
       def arguments(array_index, index)
         [
           ral_model[array_index], array(array_index), offset_address(index),
-          access_rights, unmapped, hdl_path(array_index)
+          string(access_rights), string(hdl_path(array_index))
         ]
       end
 
-      def offset_address(index = 0)
-        address =
-          if helper.offset_address
-            instance_exec(index, &helper.offset_address)
-          else
-            register.offset_address + register.byte_width * index
-          end
-        hex(address, register_block.local_address_width)
-      end
-
       def access_rights
         if read_only?
           'RO'
@@ -108,20 +78,8 @@ RgGen.define_list_feature(:register, :type) do
         register.writable? && !register.readable?
       end
 
-      def unmapped
-        helper.unmapped? && 1 || 0
-      end
-
-      def hdl_path(array_index)
-        [
-          "g_#{register.name}",
-          *Array(array_index).map { |i| "g[#{i}]" },
-          'u_register'
-        ].join('.')
-      end
-
       def variables
-        register.declarations(:register, :variable)
+        register.declarations[:variable]
       end
 
       def field_model_constructors