rggen-systemverilog 0.17.0 → 0.21.1

data/lib/rggen/systemverilog/rtl/register/type/indirect.rb

@@ -3,7 +3,7 @@
 RgGen.define_list_item_feature(:register, :type, :indirect) do
   sv_rtl do
     build do
-      logic :register, :indirect_index, { width: index_width }
+      logic :indirect_index, { width: index_width }
     end
 
     main_code :register do |code|
@@ -19,11 +19,11 @@ RgGen.define_list_item_feature(:register, :type, :indirect) do
     end
 
     def index_width
-      @index_width ||= index_fields.map(&:width).inject(:+)
+      @index_width ||= index_fields.map(&:width).sum
     end
 
     def index_values
-      loop_variables = register.loop_variables
+      loop_variables = register.local_loop_variables
       register.index_entries.zip(index_fields).map do |entry, field|
         if entry.array_index?
           loop_variables.shift[0, field.width]

data/lib/rggen/systemverilog/rtl/register_block/protocol.rb

@@ -65,21 +65,27 @@ RgGen.define_list_feature(:register_block, :protocol) do
 
     base_feature do
       build do
-        parameter :register_block, :error_status, {
+        parameter :address_width, {
+          name: 'ADDRESS_WIDTH', data_type: :int, default: local_address_width
+        }
+        parameter :pre_decode, {
+          name: 'PRE_DECODE', data_type: :bit, width: 1, default: 0
+        }
+        parameter :base_address, {
+          name: 'BASE_ADDRESS', data_type: :bit, width: address_width,
+          default: all_bits_0
+        }
+        parameter :error_status, {
           name: 'ERROR_STATUS', data_type: :bit, width: 1, default: 0
         }
-        parameter :register_block, :default_read_data, {
+        parameter :default_read_data, {
           name: 'DEFAULT_READ_DATA', data_type: :bit, width: bus_width,
-          default: hex(0, bus_width)
+          default: all_bits_0
         }
       end
 
       private
 
-      def address_width
-        configuration.address_width
-      end
-
       def bus_width
         configuration.bus_width
       end
@@ -96,6 +102,10 @@ RgGen.define_list_feature(:register_block, :protocol) do
         register_block.total_registers
       end
 
+      def byte_size
+        register_block.byte_size
+      end
+
       def clock
         register_block.clock
       end

data/lib/rggen/systemverilog/rtl/register_block/protocol/apb.erb

@@ -1,9 +1,13 @@
 rggen_apb_adapter #(
-  .ADDRESS_WIDTH      (<%= local_address_width %>),
-  .BUS_WIDTH          (<%= bus_width %>),
-  .REGISTERS          (<%= total_registers %>),
-  .ERROR_STATUS       (<%= error_status %>),
-  .DEFAULT_READ_DATA  (<%= default_read_data %>)
+  .ADDRESS_WIDTH        (<%= address_width %>),
+  .LOCAL_ADDRESS_WIDTH  (<%= local_address_width %>),
+  .BUS_WIDTH            (<%= bus_width %>),
+  .REGISTERS            (<%= total_registers %>),
+  .PRE_DECODE           (<%= pre_decode %>),
+  .BASE_ADDRESS         (<%= base_address %>),
+  .BYTE_SIZE            (<%= byte_size %>),
+  .ERROR_STATUS         (<%= error_status %>),
+  .DEFAULT_READ_DATA    (<%= default_read_data %>)
 ) u_adapter (
   .i_clk        (<%= clock %>),
   .i_rst_n      (<%= reset %>),

data/lib/rggen/systemverilog/rtl/register_block/protocol/apb.rb

@@ -22,42 +22,41 @@ RgGen.define_list_item_feature(:register_block, :protocol, :apb) do
   sv_rtl do
     build do
       if configuration.fold_sv_interface_port?
-        interface_port :register_block, :apb_if, {
+        interface_port :apb_if, {
           name: 'apb_if', interface_type: 'rggen_apb_if', modport: 'slave'
         }
       else
-        input :register_block, :psel, {
+        input :psel, {
           name: 'i_psel', data_type: :logic, width: 1
         }
-        input :register_block, :penable, {
+        input :penable, {
           name: 'i_penable', data_type: :logic, width: 1
         }
-        input :register_block, :paddr, {
+        input :paddr, {
           name: 'i_paddr', data_type: :logic, width: address_width
         }
-        input :register_block, :pprot, {
+        input :pprot, {
           name: 'i_pprot', data_type: :logic, width: 3
         }
-        input :register_block, :pwrite, {
+        input :pwrite, {
           name: 'i_pwrite', data_type: :logic, width: 1
         }
-        input :register_block, :pstrb, {
-          name: 'i_pstrb', data_type: :logic,
-          width: byte_width
+        input :pstrb, {
+          name: 'i_pstrb', data_type: :logic, width: byte_width
         }
-        input :register_block, :pwdata, {
+        input :pwdata, {
           name: 'i_pwdata', data_type: :logic, width: bus_width
         }
-        output :register_block, :pready, {
+        output :pready, {
           name: 'o_pready', data_type: :logic, width: 1
         }
-        output :register_block, :prdata, {
+        output :prdata, {
           name: 'o_prdata', data_type: :logic, width: bus_width
         }
-        output :register_block, :pslverr, {
+        output :pslverr, {
           name: 'o_pslverr', data_type: :logic, width: 1
         }
-        interface :register_block, :apb_if, {
+        interface :apb_if, {
           name: 'apb_if', interface_type: 'rggen_apb_if',
           parameter_values: [address_width, bus_width],
           variables: [
@@ -82,7 +81,7 @@ RgGen.define_list_item_feature(:register_block, :protocol, :apb) do
           [pready, apb_if.pready],
           [prdata, apb_if.prdata],
           [pslverr, apb_if.pslverr]
-        ].map { |lhs, rhs| code << assign(lhs, rhs) << nl }
+        ].each { |lhs, rhs| code << assign(lhs, rhs) << nl }
       end
     end
   end

data/lib/rggen/systemverilog/rtl/register_block/protocol/axi4lite.erb

@@ -1,10 +1,15 @@
 rggen_axi4lite_adapter #(
-  .ADDRESS_WIDTH      (<%= local_address_width %>),
-  .BUS_WIDTH          (<%= bus_width %>),
-  .REGISTERS          (<%= total_registers %>),
-  .ERROR_STATUS       (<%= error_status %>),
-  .DEFAULT_READ_DATA  (<%= default_read_data %>),
-  .WRITE_FIRST        (<%= write_first %>)
+  .ID_WIDTH             (<%= id_width %>),
+  .ADDRESS_WIDTH        (<%= address_width %>),
+  .LOCAL_ADDRESS_WIDTH  (<%= local_address_width %>),
+  .BUS_WIDTH            (<%= bus_width %>),
+  .REGISTERS            (<%= total_registers %>),
+  .PRE_DECODE           (<%= pre_decode %>),
+  .BASE_ADDRESS         (<%= base_address %>),
+  .BYTE_SIZE            (<%= byte_size %>),
+  .ERROR_STATUS         (<%= error_status %>),
+  .DEFAULT_READ_DATA    (<%= default_read_data %>),
+  .WRITE_FIRST          (<%= write_first %>)
 ) u_adapter (
   .i_clk        (<%= clock %>),
   .i_rst_n      (<%= reset %>),

data/lib/rggen/systemverilog/rtl/register_block/protocol/axi4lite.rb

@@ -13,83 +13,96 @@ RgGen.define_list_item_feature(:register_block, :protocol, :axi4lite) do
 
   sv_rtl do
     build do
-      parameter :register_block, :write_first, {
-        name: 'WRITE_FIRST',
-        data_type: :bit,
-        default: 1
+      parameter :id_width, {
+        name: 'ID_WIDTH', data_type: :int, default: 0
+      }
+      parameter :write_first, {
+        name: 'WRITE_FIRST', data_type: :bit, default: 1
       }
       if configuration.fold_sv_interface_port?
-        interface_port :register_block, :axi4lite_if, {
+        interface_port :axi4lite_if, {
           name: 'axi4lite_if',
           interface_type: 'rggen_axi4lite_if', modport: 'slave'
         }
       else
-        input :register_block, :awvalid, {
+        input :awvalid, {
           name: 'i_awvalid', data_type: :logic, width: 1
         }
-        output :register_block, :awready, {
+        output :awready, {
           name: 'o_awready', data_type: :logic, width: 1
         }
-        input :register_block, :awaddr, {
+        input :awid, {
+          name: 'i_awid', data_type: :logic, width: id_port_width
+        }
+        input :awaddr, {
           name: 'i_awaddr', data_type: :logic, width: address_width
         }
-        input :register_block, :awprot, {
+        input :awprot, {
           name: 'i_awprot', data_type: :logic, width: 3
         }
-        input :register_block, :wvalid, {
+        input :wvalid, {
           name: 'i_wvalid', data_type: :logic, width: 1
         }
-        output :register_block, :wready, {
+        output :wready, {
           name: 'o_wready', data_type: :logic, width: 1
         }
-        input :register_block, :wdata, {
+        input :wdata, {
           name: 'i_wdata', data_type: :logic, width: bus_width
         }
-        input :register_block, :wstrb, {
+        input :wstrb, {
           name: 'i_wstrb', data_type: :logic, width: byte_width
         }
-        output :register_block, :bvalid, {
+        output :bvalid, {
           name: 'o_bvalid', data_type: :logic, width: 1
         }
-        input :register_block, :bready, {
+        output :bid, {
+          name: 'o_bid', data_type: :logic, width: id_port_width
+        }
+        input :bready, {
           name: 'i_bready', data_type: :logic, width: 1
         }
-        output :register_block, :bresp, {
+        output :bresp, {
           name: 'o_bresp', data_type: :logic, width: 2
         }
-        input :register_block, :arvalid, {
+        input :arvalid, {
           name: 'i_arvalid', data_type: :logic, width: 1
         }
-        output :register_block, :arready, {
+        output :arready, {
           name: 'o_arready', data_type: :logic, width: 1
         }
-        input :register_block, :araddr, {
+        input :arid, {
+          name: 'i_arid', data_type: :logic, width: id_port_width
+        }
+        input :araddr, {
           name: 'i_araddr', data_type: :logic, width: address_width
         }
-        input :register_block, :arprot, {
+        input :arprot, {
           name: 'i_arprot', data_type: :logic, width: 3
         }
-        output :register_block, :rvalid, {
+        output :rvalid, {
           name: 'o_rvalid', data_type: :logic, width: 1
         }
-        input :register_block, :rready, {
+        input :rready, {
           name: 'i_rready', data_type: :logic, width: 1
         }
-        output :register_block, :rdata, {
+        output :rid, {
+          name: 'o_rid', data_type: :logic, width: id_port_width
+        }
+        output :rdata, {
           name: 'o_rdata', data_type: :logic, width: bus_width
         }
-        output :register_block, :rresp, {
+        output :rresp, {
           name: 'o_rresp', data_type: :logic, width: 2
         }
-        interface :register_block, :axi4lite_if, {
+        interface :axi4lite_if, {
           name: 'axi4lite_if', interface_type: 'rggen_axi4lite_if',
-          parameter_values: [address_width, bus_width],
+          parameter_values: [id_width, address_width, bus_width],
           variables: [
-            'awvalid', 'awready', 'awaddr', 'awprot',
+            'awvalid', 'awready', 'awid', 'awaddr', 'awprot',
             'wvalid', 'wready', 'wdata', 'wstrb',
-            'bvalid', 'bready', 'bresp',
-            'arvalid', 'arready', 'araddr', 'arprot',
-            'rvalid', 'rready', 'rdata', 'rresp'
+            'bvalid', 'bready', 'bid', 'bresp',
+            'arvalid', 'arready', 'arid', 'araddr', 'arprot',
+            'rvalid', 'rready', 'rid', 'rdata', 'rresp'
           ]
         }
       end
@@ -101,6 +114,7 @@ RgGen.define_list_item_feature(:register_block, :protocol, :axi4lite) do
         [
           [axi4lite_if.awvalid, awvalid],
           [awready, axi4lite_if.awready],
+          [axi4lite_if.awid, awid],
           [axi4lite_if.awaddr, awaddr],
           [axi4lite_if.awprot, awprot],
           [axi4lite_if.wvalid, wvalid],
@@ -109,17 +123,26 @@ RgGen.define_list_item_feature(:register_block, :protocol, :axi4lite) do
           [axi4lite_if.wstrb, wstrb],
           [bvalid, axi4lite_if.bvalid],
           [axi4lite_if.bready, bready],
+          [bid, axi4lite_if.bid],
           [bresp, axi4lite_if.bresp],
           [axi4lite_if.arvalid, arvalid],
           [arready, axi4lite_if.arready],
+          [axi4lite_if.arid, arid],
           [axi4lite_if.araddr, araddr],
           [axi4lite_if.arprot, arprot],
           [rvalid, axi4lite_if.rvalid],
           [axi4lite_if.rready, rready],
+          [rid, axi4lite_if.rid],
           [rdata, axi4lite_if.rdata],
           [rresp, axi4lite_if.rresp]
         ].each { |lhs, rhs| code << assign(lhs, rhs) << nl }
       end
     end
+
+    private
+
+    def id_port_width
+      "((#{id_width}>0)?#{id_width}:1)"
+    end
   end
 end

data/lib/rggen/systemverilog/rtl/register_block/sv_rtl_top.rb

@@ -5,17 +5,16 @@ RgGen.define_simple_feature(:register_block, :sv_rtl_top) do
     export :total_registers
 
     build do
-      input :register_block, :clock, {
+      input :clock, {
         name: 'i_clk', data_type: :logic, width: 1
       }
-      input :register_block, :reset, {
+      input :reset, {
         name: 'i_rst_n', data_type: :logic, width: 1
       }
-      interface :register_block, :register_if, {
+      interface :register_if, {
         name: 'register_if', interface_type: 'rggen_register_if',
         parameter_values: [address_width, bus_width, value_width],
-        array_size: [total_registers],
-        variables: ['value']
+        array_size: [total_registers], variables: ['value']
       }
     end
 
@@ -24,10 +23,7 @@ RgGen.define_simple_feature(:register_block, :sv_rtl_top) do
     end
 
     def total_registers
-      register_block
-        .registers
-        .map(&:count)
-        .inject(:+)
+      register_block.files_and_registers.map(&:count).sum
     end
 
     private
@@ -68,19 +64,21 @@ RgGen.define_simple_feature(:register_block, :sv_rtl_top) do
     end
 
     def parameters
-      register_block.declarations(:register_block, :parameter)
+      register_block.declarations[:parameter]
     end
 
     def ports
-      register_block.declarations(:register_block, :port)
+      register_block.declarations[:port]
     end
 
     def variables
-      register_block.declarations(:register_block, :variable)
+      register_block.declarations[:variable]
     end
 
     def sv_module_body(code)
-      register_block.generate_code(:register_block, :top_down, code)
+      { register_block: nil, register_file: 1 }.each do |kind, depth|
+        register_block.generate_code(code, kind, :top_down, depth)
+      end
     end
   end
 end

data/lib/rggen/systemverilog/rtl/register_file/sv_rtl_top.rb

@@ -0,0 +1,30 @@
+# frozen_string_literal: true
+
+RgGen.define_simple_feature(:register_file, :sv_rtl_top) do
+  sv_rtl do
+    include RgGen::SystemVerilog::RTL::RegisterIndex
+
+    main_code :register_file do
+      local_scope("g_#{register_file.name}") do |scope|
+        scope.top_scope top_scope?
+        scope.loop_size loop_size
+        scope.body(&method(:body_code))
+      end
+    end
+
+    private
+
+    def top_scope?
+      register_file(:upper).nil?
+    end
+
+    def loop_size
+      (register_file.array? || nil) &&
+        local_loop_variables.zip(register_file.array_size).to_h
+    end
+
+    def body_code(code)
+      register_file.generate_code(code, :register_file, :top_down, 1)
+    end
+  end
+end

data/lib/rggen/systemverilog/rtl/register_index.rb

@@ -0,0 +1,112 @@
+# frozen_string_literal: true
+
+module RgGen
+  module SystemVerilog
+    module RTL
+      module RegisterIndex
+        include PartialSum
+
+        EXPORTED_METHODS = [
+          :loop_variables, :local_loop_variables,
+          :local_index, :local_indices,
+          :index, :inside_roop?
+        ].freeze
+
+        def self.included(feature)
+          feature.module_eval do
+            EXPORTED_METHODS.each { |m| export m }
+
+            pre_build do
+              @base_index = files_and_registers.sum(&:count)
+            end
+          end
+        end
+
+        def loop_variables
+          (inside_roop? || nil) &&
+            [*upper_register_file&.loop_variables, *local_loop_variables]
+        end
+
+        def local_loop_variables
+          (component.array? || nil) &&
+            begin
+              start_depth = (upper_register_file&.loop_variables&.size || 0) + 1
+              Array.new(component.array_size.size) do |i|
+                create_identifier(loop_index(i + start_depth))
+              end
+            end
+        end
+
+        def local_index
+          (component.array? || nil) &&
+            local_index_coefficients
+              .zip(local_loop_variables)
+              .map { |operands| product(operands, false) }
+              .join('+')
+        end
+
+        def local_indices
+          [*upper_register_file&.local_indices, local_index]
+        end
+
+        def index(offset_or_offsets = nil)
+          operands = index_operands(offset_or_offsets)
+          partial_indices = partial_sums(operands)
+          if partial_indices.empty? || partial_indices.all?(&method(:integer?))
+            partial_indices.sum
+          else
+            partial_indices.join('+')
+          end
+        end
+
+        def inside_roop?
+          component.array? || upper_register_file&.inside_roop? || false
+        end
+
+        private
+
+        def upper_register_file
+          component.register_file
+        end
+
+        def local_index_coefficients
+          coefficients = []
+          component.array_size.reverse.inject(1) do |total, size|
+            coefficients.unshift(total)
+            total * size
+          end
+          coefficients
+        end
+
+        def index_operands(offset_or_offsets)
+          offsets = offset_or_offsets && Array(offset_or_offsets)
+          [
+            *upper_register_file&.index(offsets&.slice(0..-2)),
+            @base_index,
+            *local_register_index(offsets&.slice(-1))
+          ]
+        end
+
+        def local_register_index(offset)
+          (component.array? || nil) &&
+            begin
+              operands = [component.count(false), offset || local_index]
+              product(operands, true)
+            end
+        end
+
+        def product(operands, need_bracket)
+          if operands.all?(&method(:integer?))
+            operands.reduce(:*)
+          elsif operands.first == 1
+            operands.last
+          elsif need_bracket
+            "#{operands.first}*(#{operands.last})"
+          else
+            operands.join('*')
+          end
+        end
+      end
+    end
+  end
+end