rggen-systemverilog 0.17.0 → 0.21.1
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- checksums.yaml +4 -4
- data/LICENSE +1 -1
- data/README.md +2 -2
- data/lib/rggen/systemverilog/common.rb +2 -2
- data/lib/rggen/systemverilog/common/component.rb +2 -6
- data/lib/rggen/systemverilog/common/feature.rb +39 -26
- data/lib/rggen/systemverilog/common/utility.rb +6 -2
- data/lib/rggen/systemverilog/common/utility/data_object.rb +2 -2
- data/lib/rggen/systemverilog/common/utility/interface_instance.rb +2 -2
- data/lib/rggen/systemverilog/common/utility/interface_port.rb +9 -5
- data/lib/rggen/systemverilog/common/utility/local_scope.rb +2 -2
- data/lib/rggen/systemverilog/common/utility/structure_definition.rb +3 -5
- data/lib/rggen/systemverilog/ral.rb +4 -1
- data/lib/rggen/systemverilog/ral/bit_field/type.rb +15 -10
- data/lib/rggen/systemverilog/ral/bit_field/type/rwe_rwl.rb +1 -11
- data/lib/rggen/systemverilog/ral/feature.rb +5 -7
- data/lib/rggen/systemverilog/ral/register/type.rb +10 -52
- data/lib/rggen/systemverilog/ral/register/type/default.erb +1 -1
- data/lib/rggen/systemverilog/ral/register/type/external.rb +6 -10
- data/lib/rggen/systemverilog/ral/register/type/indirect.erb +3 -3
- data/lib/rggen/systemverilog/ral/register/type/indirect.rb +5 -2
- data/lib/rggen/systemverilog/ral/register_block/sv_ral_model.erb +8 -0
- data/lib/rggen/systemverilog/ral/register_block/sv_ral_model.rb +36 -0
- data/lib/rggen/systemverilog/ral/register_block/sv_ral_package.rb +1 -32
- data/lib/rggen/systemverilog/ral/register_common.rb +46 -0
- data/lib/rggen/systemverilog/ral/register_file/sv_ral_model.erb +8 -0
- data/lib/rggen/systemverilog/ral/register_file/sv_ral_model.rb +57 -0
- data/lib/rggen/systemverilog/ral/setup.rb +2 -1
- data/lib/rggen/systemverilog/rtl.rb +5 -2
- data/lib/rggen/systemverilog/rtl/bit_field/sv_rtl_top.rb +34 -19
- data/lib/rggen/systemverilog/rtl/bit_field/type.rb +1 -5
- data/lib/rggen/systemverilog/rtl/bit_field/type/rc_w0c_w1c.rb +3 -3
- data/lib/rggen/systemverilog/rtl/bit_field/type/ro.rb +1 -1
- data/lib/rggen/systemverilog/rtl/bit_field/type/rs_w0s_w1s.rb +2 -2
- data/lib/rggen/systemverilog/rtl/bit_field/type/{rw_wo.erb → rw_w1_wo_wo1.erb} +4 -2
- data/lib/rggen/systemverilog/rtl/bit_field/type/rw_w1_wo_wo1.rb +24 -0
- data/lib/rggen/systemverilog/rtl/bit_field/type/rwc.rb +2 -2
- data/lib/rggen/systemverilog/rtl/bit_field/type/rwe.rb +2 -2
- data/lib/rggen/systemverilog/rtl/bit_field/type/rwl.rb +2 -2
- data/lib/rggen/systemverilog/rtl/bit_field/type/rws.rb +3 -3
- data/lib/rggen/systemverilog/rtl/bit_field/type/w0crs_w1crs.rb +1 -1
- data/lib/rggen/systemverilog/rtl/bit_field/type/w0src_w1src.rb +1 -1
- data/lib/rggen/systemverilog/rtl/bit_field/type/w0trg_w1trg.rb +1 -1
- data/lib/rggen/systemverilog/rtl/feature.rb +12 -16
- data/lib/rggen/systemverilog/rtl/partial_sum.rb +29 -0
- data/lib/rggen/systemverilog/rtl/register/sv_rtl_top.rb +10 -47
- data/lib/rggen/systemverilog/rtl/register/type.rb +25 -1
- data/lib/rggen/systemverilog/rtl/register/type/external.rb +15 -15
- data/lib/rggen/systemverilog/rtl/register/type/indirect.rb +3 -3
- data/lib/rggen/systemverilog/rtl/register_block/protocol.rb +17 -7
- data/lib/rggen/systemverilog/rtl/register_block/protocol/apb.erb +9 -5
- data/lib/rggen/systemverilog/rtl/register_block/protocol/apb.rb +14 -15
- data/lib/rggen/systemverilog/rtl/register_block/protocol/axi4lite.erb +11 -6
- data/lib/rggen/systemverilog/rtl/register_block/protocol/axi4lite.rb +53 -30
- data/lib/rggen/systemverilog/rtl/register_block/sv_rtl_top.rb +11 -13
- data/lib/rggen/systemverilog/rtl/register_file/sv_rtl_top.rb +30 -0
- data/lib/rggen/systemverilog/rtl/register_index.rb +112 -0
- data/lib/rggen/systemverilog/rtl/setup.rb +1 -0
- data/lib/rggen/systemverilog/version.rb +1 -1
- metadata +16 -9
- data/lib/rggen/systemverilog/ral/register_block/sv_ral_block_model.erb +0 -11
- data/lib/rggen/systemverilog/rtl/bit_field/type/rw_wo.rb +0 -14
@@ -3,16 +3,16 @@
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RgGen.define_list_item_feature(:bit_field, :type, [:rc, :w0c, :w1c]) do
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sv_rtl do
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build do
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-
input :
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+
input :set, {
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name: "i_#{full_name}_set", data_type: :logic, width: width,
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array_size: array_size, array_format: array_port_format
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}
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-
output :
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+
output :value_out, {
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name: "o_#{full_name}", data_type: :logic, width: width,
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array_size: array_size, array_format: array_port_format
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}
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if bit_field.reference?
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-
output :
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+
output :value_unmasked, {
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name: "o_#{full_name}_unmasked", data_type: :logic, width: width,
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array_size: array_size, array_format: array_port_format
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}
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@@ -4,7 +4,7 @@ RgGen.define_list_item_feature(:bit_field, :type, :ro) do
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sv_rtl do
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build do
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unless bit_field.reference?
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-
input :
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+
input :value_in, {
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name: "i_#{full_name}", data_type: :logic, width: width,
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array_size: array_size, array_format: array_port_format
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}
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@@ -3,11 +3,11 @@
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RgGen.define_list_item_feature(:bit_field, :type, [:rs, :w0s, :w1s]) do
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sv_rtl do
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build do
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-
input :
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+
input :clear, {
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name: "i_#{full_name}_clear", data_type: :logic, width: width,
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array_size: array_size, array_format: array_port_format
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}
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-
output :
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+
output :value_out, {
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name: "o_#{full_name}", data_type: :logic, width: width,
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array_size: array_size, array_format: array_port_format
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}
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@@ -1,6 +1,8 @@
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-
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+
rggen_bit_field_rw_wo #(
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.WIDTH (<%= width %>),
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-
.INITIAL_VALUE (<%= initial_value %>)
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+
.INITIAL_VALUE (<%= initial_value %>),
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.WRITE_ONLY (<%= write_only %>),
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.WRITE_ONCE (<%= write_once %>)
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) u_bit_field (
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.i_clk (<%= clock %>),
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.i_rst_n (<%= reset %>),
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@@ -0,0 +1,24 @@
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# frozen_string_literal: true
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RgGen.define_list_item_feature(:bit_field, :type, [:rw, :w1, :wo, :wo1]) do
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sv_rtl do
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build do
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output :value_out, {
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name: "o_#{full_name}", data_type: :logic, width: width,
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array_size: array_size, array_format: array_port_format
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}
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end
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+
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main_code :bit_field, from_template: true
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private
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def write_only
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bit_field.write_only? && 1 || 0
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end
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def write_once
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[:w1, :wo1].include?(bit_field.type) && 1 || 0
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end
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end
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end
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@@ -4,12 +4,12 @@ RgGen.define_list_item_feature(:bit_field, :type, :rwc) do
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sv_rtl do
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build do
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unless bit_field.reference?
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-
input :
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+
input :clear, {
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name: "i_#{full_name}_clear", data_type: :logic, width: 1,
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array_size: array_size, array_format: array_port_format
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}
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end
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-
output :
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+
output :value_out, {
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name: "o_#{full_name}", data_type: :logic, width: width,
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array_size: array_size, array_format: array_port_format
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}
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@@ -4,12 +4,12 @@ RgGen.define_list_item_feature(:bit_field, :type, :rwe) do
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sv_rtl do
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build do
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unless bit_field.reference?
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-
input :
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+
input :enable, {
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name: "i_#{full_name}_enable", data_type: :logic, width: 1,
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array_size: array_size, array_format: array_port_format
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}
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end
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-
output :
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+
output :value_out, {
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name: "o_#{full_name}", data_type: :logic, width: width,
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array_size: array_size, array_format: array_port_format
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}
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@@ -4,12 +4,12 @@ RgGen.define_list_item_feature(:bit_field, :type, :rwl) do
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sv_rtl do
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build do
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unless bit_field.reference?
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-
input :
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+
input :lock, {
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name: "i_#{full_name}_lock", data_type: :logic, width: 1,
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array_size: array_size, array_format: array_port_format
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}
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end
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-
output :
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+
output :value_out, {
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name: "o_#{full_name}", data_type: :logic, width: width,
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array_size: array_size, array_format: array_port_format
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}
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@@ -4,16 +4,16 @@ RgGen.define_list_item_feature(:bit_field, :type, :rws) do
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sv_rtl do
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build do
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unless bit_field.reference?
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-
input :
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+
input :set, {
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name: "i_#{full_name}_set", data_type: :logic, width: 1,
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array_size: array_size, array_format: array_port_format
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}
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end
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-
input :
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+
input :value_in, {
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name: "i_#{full_name}", data_type: :logic, width: width,
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array_size: array_size, array_format: array_port_format
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}
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-
output :
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+
output :value_out, {
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name: "o_#{full_name}", data_type: :logic, width: width,
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array_size: array_size, array_format: array_port_format
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}
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@@ -3,7 +3,7 @@
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RgGen.define_list_item_feature(:bit_field, :type, [:w0crs, :w1crs]) do
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sv_rtl do
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build do
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-
output :
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+
output :value_out, {
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name: "o_#{full_name}", data_type: :logic, width: width,
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array_size: array_size, array_format: array_port_format
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}
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@@ -3,7 +3,7 @@
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RgGen.define_list_item_feature(:bit_field, :type, [:w0src, :w1src]) do
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sv_rtl do
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build do
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-
output :
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+
output :value_out, {
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name: "o_#{full_name}", data_type: :logic, width: width,
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array_size: array_size, array_format: array_port_format
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}
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@@ -3,7 +3,7 @@
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RgGen.define_list_item_feature(:bit_field, :type, [:w0trg, :w1trg]) do
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sv_rtl do
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build do
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-
output :
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+
output :trigger, {
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name: "o_#{full_name}_trigger", data_type: :logic, width: width,
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array_size: array_size, array_format: array_port_format
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}
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@@ -6,43 +6,39 @@ module RgGen
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class Feature < Common::Feature
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private
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8
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9
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-
def create_variable(data_type, attributes, block)
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+
def create_variable(data_type, attributes, &block)
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DataObject.new(
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:variable, attributes.merge(data_type: data_type), &block
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)
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end
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-
def
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+
def create_if_instance(_, attributes, &block)
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InterfaceInstance.new(attributes, &block)
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end
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-
def create_argument(direction, attributes, block)
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+
def create_argument(direction, attributes, &block)
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DataObject.new(
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:argument, attributes.merge(direction: direction), &block
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)
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end
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24
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-
def
|
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+
def create_if_port(_, attributes, &block)
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26
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InterfacePort.new(attributes, &block)
|
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end
|
28
28
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29
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-
def create_parameter(parameter_type, attributes, block)
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+
def create_parameter(parameter_type, attributes, &block)
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DataObject.new(
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:parameter, attributes.merge(parameter_type: parameter_type), &block
|
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)
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end
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35
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-
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-
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-
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-
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-
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-
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-
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42
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-
[:localparam, :create_parameter, :parameter]
|
43
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-
].each do |entity, creation_method, declaration_type|
|
44
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-
define_entity(entity, creation_method, declaration_type)
|
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-
end
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35
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+
define_entity :logic, :create_variable, :variable, -> { component }
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+
define_entity :interface, :create_if_instance, :variable, -> { component }
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37
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+
define_entity :input, :create_argument, :port, -> { register_block }
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+
define_entity :output, :create_argument, :port, -> { register_block }
|
39
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+
define_entity :interface_port, :create_if_port, :port, -> { register_block }
|
40
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+
define_entity :parameter, :create_parameter, :parameter, -> { register_block }
|
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+
define_entity :localparam, :create_parameter, :parameter, -> { component }
|
46
42
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end
|
47
43
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end
|
48
44
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end
|
@@ -0,0 +1,29 @@
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1
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+
# frozen_string_literal: true
|
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+
|
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+
module RgGen
|
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+
module SystemVerilog
|
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+
module RTL
|
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+
module PartialSum
|
7
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+
private
|
8
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+
|
9
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+
def partial_sums(operands)
|
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+
sums =
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+
operands
|
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+
.chunk(&method(:integer?))
|
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+
.flat_map(&method(:calc_partial_sum))
|
14
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+
.reject { |value| integer?(value) && value.zero? }
|
15
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+
sums.empty? && [0] || sums
|
16
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+
end
|
17
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+
|
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+
def calc_partial_sum(kind_ans_values)
|
19
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+
kind, values = kind_ans_values
|
20
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+
kind && values.sum || values
|
21
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+
end
|
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+
|
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+
def integer?(value)
|
24
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+
value.is_a?(Integer)
|
25
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+
end
|
26
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+
end
|
27
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+
end
|
28
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+
end
|
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+
end
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@@ -2,18 +2,11 @@
|
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2
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3
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RgGen.define_simple_feature(:register, :sv_rtl_top) do
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4
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sv_rtl do
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-
|
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-
export :local_index
|
7
|
-
export :loop_variables
|
8
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-
|
9
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-
pre_build do
|
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-
@base_index =
|
11
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-
register_block.registers.map(&:count).inject(0, :+)
|
12
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-
end
|
5
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+
include RgGen::SystemVerilog::RTL::RegisterIndex
|
13
6
|
|
14
7
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build do
|
15
|
-
|
16
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-
interface :
|
8
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+
unless register.bit_fields.empty?
|
9
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+
interface :bit_field_if, {
|
17
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name: 'bit_field_if',
|
18
11
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interface_type: 'rggen_bit_field_if',
|
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parameter_values: [register.width]
|
@@ -21,62 +14,32 @@ RgGen.define_simple_feature(:register, :sv_rtl_top) do
|
|
21
14
|
end
|
22
15
|
end
|
23
16
|
|
24
|
-
main_code :
|
17
|
+
main_code :register_file do
|
25
18
|
local_scope("g_#{register.name}") do |scope|
|
26
|
-
scope.top_scope
|
19
|
+
scope.top_scope top_scope?
|
27
20
|
scope.loop_size loop_size
|
28
21
|
scope.variables variables
|
29
22
|
scope.body(&method(:body_code))
|
30
23
|
end
|
31
24
|
end
|
32
25
|
|
33
|
-
def index(offset = nil)
|
34
|
-
operands =
|
35
|
-
register.array? ? [@base_index, offset || local_index] : [@base_index]
|
36
|
-
if operands.all? { |operand| operand.is_a?(Integer) }
|
37
|
-
operands.inject(:+)
|
38
|
-
else
|
39
|
-
operands.join('+')
|
40
|
-
end
|
41
|
-
end
|
42
|
-
|
43
|
-
def local_index
|
44
|
-
(register.array? || nil) &&
|
45
|
-
loop_variables
|
46
|
-
.zip(local_index_coefficients)
|
47
|
-
.map { |v, c| [c, v].compact.join('*') }
|
48
|
-
.join('+')
|
49
|
-
end
|
50
|
-
|
51
|
-
def loop_variables
|
52
|
-
(register.array? || nil) &&
|
53
|
-
register.array_size.map.with_index(1) do |_size, i|
|
54
|
-
create_identifier(loop_index(i))
|
55
|
-
end
|
56
|
-
end
|
57
|
-
|
58
26
|
private
|
59
27
|
|
60
|
-
def
|
61
|
-
|
62
|
-
register.array_size.reverse.inject(1) do |total, size|
|
63
|
-
coefficients.unshift(coefficients.size.zero? ? nil : total)
|
64
|
-
total * size
|
65
|
-
end
|
66
|
-
coefficients
|
28
|
+
def top_scope?
|
29
|
+
register_file.nil?
|
67
30
|
end
|
68
31
|
|
69
32
|
def loop_size
|
70
33
|
(register.array? || nil) &&
|
71
|
-
|
34
|
+
local_loop_variables.zip(register.array_size).to_h
|
72
35
|
end
|
73
36
|
|
74
37
|
def variables
|
75
|
-
register.declarations
|
38
|
+
register.declarations[:variable]
|
76
39
|
end
|
77
40
|
|
78
41
|
def body_code(code)
|
79
|
-
register.generate_code(:register, :top_down
|
42
|
+
register.generate_code(code, :register, :top_down)
|
80
43
|
end
|
81
44
|
end
|
82
45
|
end
|
@@ -3,6 +3,8 @@
|
|
3
3
|
RgGen.define_list_feature(:register, :type) do
|
4
4
|
sv_rtl do
|
5
5
|
base_feature do
|
6
|
+
include RgGen::SystemVerilog::RTL::PartialSum
|
7
|
+
|
6
8
|
private
|
7
9
|
|
8
10
|
def readable
|
@@ -22,7 +24,29 @@ RgGen.define_list_feature(:register, :type) do
|
|
22
24
|
end
|
23
25
|
|
24
26
|
def offset_address
|
25
|
-
|
27
|
+
offsets = [*register_files, register].flat_map(&method(:collect_offsets))
|
28
|
+
offsets = partial_sums(offsets)
|
29
|
+
format_offsets(offsets)
|
30
|
+
end
|
31
|
+
|
32
|
+
def collect_offsets(component)
|
33
|
+
if component.register_file? && component.array?
|
34
|
+
[component.offset_address, byte_offset(component)]
|
35
|
+
else
|
36
|
+
component.offset_address
|
37
|
+
end
|
38
|
+
end
|
39
|
+
|
40
|
+
def byte_offset(component)
|
41
|
+
"#{component.byte_size(false)}*(#{component.local_index})"
|
42
|
+
end
|
43
|
+
|
44
|
+
def format_offsets(offsets)
|
45
|
+
offsets.map(&method(:format_offset)).join('+')
|
46
|
+
end
|
47
|
+
|
48
|
+
def format_offset(offset)
|
49
|
+
offset.is_a?(Integer) ? hex(offset, address_width) : offset
|
26
50
|
end
|
27
51
|
|
28
52
|
def width
|
@@ -4,49 +4,49 @@ RgGen.define_list_item_feature(:register, :type, :external) do
|
|
4
4
|
sv_rtl do
|
5
5
|
build do
|
6
6
|
if configuration.fold_sv_interface_port?
|
7
|
-
interface_port :
|
7
|
+
interface_port :bus_if, {
|
8
8
|
name: "#{register.name}_bus_if",
|
9
9
|
interface_type: 'rggen_bus_if',
|
10
10
|
modport: 'master'
|
11
11
|
}
|
12
12
|
else
|
13
|
-
output :
|
13
|
+
output :valid, {
|
14
14
|
name: "o_#{register.name}_valid",
|
15
15
|
data_type: :logic, width: 1
|
16
16
|
}
|
17
|
-
output :
|
17
|
+
output :access, {
|
18
|
+
name: "o_#{register.name}_access",
|
19
|
+
data_type: :logic, width: '$bits(rggen_access)'
|
20
|
+
}
|
21
|
+
output :address, {
|
18
22
|
name: "o_#{register.name}_address",
|
19
23
|
data_type: :logic, width: address_width
|
20
24
|
}
|
21
|
-
output :
|
22
|
-
name: "o_#{register.name}_write",
|
23
|
-
data_type: :logic, width: 1
|
24
|
-
}
|
25
|
-
output :register_block, :write_data, {
|
25
|
+
output :write_data, {
|
26
26
|
name: "o_#{register.name}_data",
|
27
27
|
data_type: :logic, width: bus_width
|
28
28
|
}
|
29
|
-
output :
|
29
|
+
output :strobe, {
|
30
30
|
name: "o_#{register.name}_strobe",
|
31
31
|
data_type: :logic, width: byte_width
|
32
32
|
}
|
33
|
-
input :
|
33
|
+
input :ready, {
|
34
34
|
name: "i_#{register.name}_ready",
|
35
35
|
data_type: :logic, width: 1
|
36
36
|
}
|
37
|
-
input :
|
37
|
+
input :status, {
|
38
38
|
name: "i_#{register.name}_status",
|
39
39
|
data_type: :logic, width: 2
|
40
40
|
}
|
41
|
-
input :
|
41
|
+
input :read_data, {
|
42
42
|
name: "i_#{register.name}_data",
|
43
43
|
data_type: :logic, width: bus_width
|
44
44
|
}
|
45
|
-
interface :
|
45
|
+
interface :bus_if, {
|
46
46
|
name: 'bus_if', interface_type: 'rggen_bus_if',
|
47
47
|
parameter_values: [address_width, bus_width],
|
48
48
|
variables: [
|
49
|
-
'valid', '
|
49
|
+
'valid', 'access', 'address', 'write_data', 'strobe',
|
50
50
|
'ready', 'status', 'read_data'
|
51
51
|
]
|
52
52
|
}
|
@@ -58,8 +58,8 @@ RgGen.define_list_item_feature(:register, :type, :external) do
|
|
58
58
|
unless configuration.fold_sv_interface_port?
|
59
59
|
[
|
60
60
|
[valid, bus_if.valid],
|
61
|
+
[access, bus_if.access],
|
61
62
|
[address, bus_if.address],
|
62
|
-
[write, bus_if.write],
|
63
63
|
[write_data, bus_if.write_data],
|
64
64
|
[strobe, bus_if.strobe],
|
65
65
|
[bus_if.ready, ready],
|