passenger 5.3.3 → 5.3.4

data/src/cxx_supportlib/vendor-modified/boost/atomic/detail/ops_gcc_arm_common.hpp

@@ -0,0 +1,134 @@
+/*
+ * Distributed under the Boost Software License, Version 1.0.
+ * (See accompanying file LICENSE_1_0.txt or copy at
+ * http://www.boost.org/LICENSE_1_0.txt)
+ *
+ * Copyright (c) 2009 Helge Bahmann
+ * Copyright (c) 2013 Tim Blechmann
+ * Copyright (c) 2014 Andrey Semashev
+ */
+/*!
+ * \file   atomic/detail/ops_gcc_arm_common.hpp
+ *
+ * This header contains basic utilities for gcc ARM backend.
+ */
+
+#ifndef BOOST_ATOMIC_DETAIL_OPS_GCC_ARM_COMMON_HPP_INCLUDED_
+#define BOOST_ATOMIC_DETAIL_OPS_GCC_ARM_COMMON_HPP_INCLUDED_
+
+#include <boost/cstdint.hpp>
+#include <boost/memory_order.hpp>
+#include <boost/atomic/detail/config.hpp>
+
+#ifdef BOOST_HAS_PRAGMA_ONCE
+#pragma once
+#endif
+
+namespace boost {
+namespace atomics {
+namespace detail {
+
+// A memory barrier is effected using a "co-processor 15" instruction,
+// though a separate assembler mnemonic is available for it in v7.
+//
+// "Thumb 1" is a subset of the ARM instruction set that uses a 16-bit encoding.  It
+// doesn't include all instructions and in particular it doesn't include the co-processor
+// instruction used for the memory barrier or the load-locked/store-conditional
+// instructions.  So, if we're compiling in "Thumb 1" mode, we need to wrap all of our
+// asm blocks with code to temporarily change to ARM mode.
+//
+// You can only change between ARM and Thumb modes when branching using the bx instruction.
+// bx takes an address specified in a register.  The least significant bit of the address
+// indicates the mode, so 1 is added to indicate that the destination code is Thumb.
+// A temporary register is needed for the address and is passed as an argument to these
+// macros.  It must be one of the "low" registers accessible to Thumb code, specified
+// using the "l" attribute in the asm statement.
+//
+// Architecture v7 introduces "Thumb 2", which does include (almost?) all of the ARM
+// instruction set.  (Actually, there was an extension of v6 called v6T2 which supported
+// "Thumb 2" mode, but its architecture manual is no longer available, referring to v7.)
+// So in v7 we don't need to change to ARM mode; we can write "universal
+// assembler" which will assemble to Thumb 2 or ARM code as appropriate.  The only thing
+// we need to do to make this "universal" assembler mode work is to insert "IT" instructions
+// to annotate the conditional instructions.  These are ignored in other modes (e.g. v6),
+// so they can always be present.
+
+// A note about memory_order_consume. Technically, this architecture allows to avoid
+// unnecessary memory barrier after consume load since it supports data dependency ordering.
+// However, some compiler optimizations may break a seemingly valid code relying on data
+// dependency tracking by injecting bogus branches to aid out of order execution.
+// This may happen not only in Boost.Atomic code but also in user's code, which we have no
+// control of. See this thread: http://lists.boost.org/Archives/boost/2014/06/213890.php.
+// For this reason we promote memory_order_consume to memory_order_acquire.
+
+#if defined(__thumb__) && !defined(__thumb2__)
+#define BOOST_ATOMIC_DETAIL_ARM_ASM_START(TMPREG) "adr " #TMPREG ", 8f\n" "bx " #TMPREG "\n" ".arm\n" ".align 4\n" "8:\n"
+#define BOOST_ATOMIC_DETAIL_ARM_ASM_END(TMPREG)   "adr " #TMPREG ", 9f + 1\n" "bx " #TMPREG "\n" ".thumb\n" ".align 2\n" "9:\n"
+#define BOOST_ATOMIC_DETAIL_ARM_ASM_TMPREG_CONSTRAINT(var) "=&l" (var)
+#else
+// The tmpreg may be wasted in this case, which is non-optimal.
+#define BOOST_ATOMIC_DETAIL_ARM_ASM_START(TMPREG)
+#define BOOST_ATOMIC_DETAIL_ARM_ASM_END(TMPREG)
+#define BOOST_ATOMIC_DETAIL_ARM_ASM_TMPREG_CONSTRAINT(var) "=&r" (var)
+#endif
+
+struct gcc_arm_operations_base
+{
+    static BOOST_CONSTEXPR_OR_CONST bool full_cas_based = false;
+    static BOOST_CONSTEXPR_OR_CONST bool is_always_lock_free = true;
+
+    static BOOST_FORCEINLINE void fence_before(memory_order order) BOOST_NOEXCEPT
+    {
+        if ((static_cast< unsigned int >(order) & static_cast< unsigned int >(memory_order_release)) != 0u)
+            hardware_full_fence();
+    }
+
+    static BOOST_FORCEINLINE void fence_after(memory_order order) BOOST_NOEXCEPT
+    {
+        if ((static_cast< unsigned int >(order) & (static_cast< unsigned int >(memory_order_consume) | static_cast< unsigned int >(memory_order_acquire))) != 0u)
+            hardware_full_fence();
+    }
+
+    static BOOST_FORCEINLINE void fence_after_store(memory_order order) BOOST_NOEXCEPT
+    {
+        if (order == memory_order_seq_cst)
+            hardware_full_fence();
+    }
+
+    static BOOST_FORCEINLINE void hardware_full_fence() BOOST_NOEXCEPT
+    {
+#if defined(BOOST_ATOMIC_DETAIL_ARM_HAS_DMB)
+        // Older binutils (supposedly, older than 2.21.1) didn't support symbolic or numeric arguments of the "dmb" instruction such as "ish" or "#11".
+        // As a workaround we have to inject encoded bytes of the instruction. There are two encodings for the instruction: ARM and Thumb. See ARM Architecture Reference Manual, A8.8.43.
+        // Since we cannot detect binutils version at compile time, we'll have to always use this hack.
+        __asm__ __volatile__
+        (
+#if defined(__thumb2__)
+            ".short 0xF3BF, 0x8F5B\n" // dmb ish
+#else
+            ".word 0xF57FF05B\n" // dmb ish
+#endif
+            :
+            :
+            : "memory"
+        );
+#else
+        uint32_t tmp;
+        __asm__ __volatile__
+        (
+            BOOST_ATOMIC_DETAIL_ARM_ASM_START(%0)
+            "mcr\tp15, 0, r0, c7, c10, 5\n"
+            BOOST_ATOMIC_DETAIL_ARM_ASM_END(%0)
+            : "=&l" (tmp)
+            :
+            : "memory"
+        );
+#endif
+    }
+};
+
+} // namespace detail
+} // namespace atomics
+} // namespace boost
+
+#endif // BOOST_ATOMIC_DETAIL_OPS_GCC_ARM_COMMON_HPP_INCLUDED_

data/src/cxx_supportlib/vendor-modified/boost/atomic/detail/ops_gcc_atomic.hpp

@@ -14,12 +14,13 @@
 #ifndef BOOST_ATOMIC_DETAIL_OPS_GCC_ATOMIC_HPP_INCLUDED_
 #define BOOST_ATOMIC_DETAIL_OPS_GCC_ATOMIC_HPP_INCLUDED_
 
+#include <cstddef>
 #include <boost/memory_order.hpp>
 #include <boost/atomic/detail/config.hpp>
 #include <boost/atomic/detail/storage_type.hpp>
 #include <boost/atomic/detail/operations_fwd.hpp>
 #include <boost/atomic/capabilities.hpp>
-#if defined(__clang__) && (defined(BOOST_ATOMIC_DETAIL_X86_HAS_CMPXCHG8B) || defined(BOOST_ATOMIC_DETAIL_X86_HAS_CMPXCHG16B))
+#if (defined(__clang__) || (defined(BOOST_GCC) && (BOOST_GCC+0) >= 70000)) && (defined(BOOST_ATOMIC_DETAIL_X86_HAS_CMPXCHG8B) || defined(BOOST_ATOMIC_DETAIL_X86_HAS_CMPXCHG16B))
 #include <boost/atomic/detail/ops_gcc_x86_dcas.hpp>
 #include <boost/atomic/detail/ops_cas_based.hpp>
 #endif
@@ -53,10 +54,10 @@ namespace detail {
  * The function converts \c boost::memory_order values to the compiler-specific constants.
  *
  * NOTE: The intention is that the function is optimized away by the compiler, and the
- *       compiler-specific constants are passed to the intrinsics. I know constexpr doesn't
+ *       compiler-specific constants are passed to the intrinsics. Unfortunately, constexpr doesn't
  *       work in this case because the standard atomics interface require memory ordering
  *       constants to be passed as function arguments, at which point they stop being constexpr.
- *       However it is crucial that the compiler sees constants and not runtime values,
+ *       However, it is crucial that the compiler sees constants and not runtime values,
  *       because otherwise it just ignores the ordering value and always uses seq_cst.
  *       This is the case with Intel C++ Compiler 14.0.3 (Composer XE 2013 SP1, update 3) and
  *       gcc 4.8.2. Intel Compiler issues a warning in this case:
@@ -70,8 +71,8 @@ namespace detail {
  *       all functions are called with constant orderings and call intrinstcts properly.
  *
  *       Unfortunately, this still doesn't work in debug mode as the compiler doesn't
- *       inline functions even when marked with BOOST_FORCEINLINE. In this case all atomic
- *       operaions will be executed with seq_cst semantics.
+ *       propagate constants even when functions are marked with BOOST_FORCEINLINE. In this case
+ *       all atomic operaions will be executed with seq_cst semantics.
  */
 BOOST_FORCEINLINE BOOST_CONSTEXPR int convert_memory_order_to_gcc(memory_order order) BOOST_NOEXCEPT
 {
@@ -80,12 +81,17 @@ BOOST_FORCEINLINE BOOST_CONSTEXPR int convert_memory_order_to_gcc(memory_order o
         (order == memory_order_acq_rel ? __ATOMIC_ACQ_REL : __ATOMIC_SEQ_CST)))));
 }
 
-template< typename T >
+template< std::size_t Size, bool Signed >
 struct gcc_atomic_operations
 {
-    typedef T storage_type;
+    typedef typename make_storage_type< Size >::type storage_type;
+    typedef typename make_storage_type< Size >::aligned aligned_storage_type;
 
-    // Note: In the current implementation, gcc_atomic_operations are used onlu when the particularly sized __atomic
+    static BOOST_CONSTEXPR_OR_CONST std::size_t storage_size = Size;
+    static BOOST_CONSTEXPR_OR_CONST bool is_signed = Signed;
+    static BOOST_CONSTEXPR_OR_CONST bool full_cas_based = false;
+
+    // Note: In the current implementation, gcc_atomic_operations are used only when the particularly sized __atomic
     // intrinsics are always lock-free (i.e. the corresponding LOCK_FREE macro is 2). Therefore it is safe to
     // always set is_always_lock_free to true here.
     static BOOST_CONSTEXPR_OR_CONST bool is_always_lock_free = true;
@@ -161,31 +167,29 @@ struct gcc_atomic_operations
     {
         __atomic_clear(const_cast< storage_type* >(&storage), atomics::detail::convert_memory_order_to_gcc(order));
     }
-
-    static BOOST_FORCEINLINE bool is_lock_free(storage_type const volatile& storage) BOOST_NOEXCEPT
-    {
-        return __atomic_is_lock_free(sizeof(storage_type), &storage);
-    }
 };
 
 #if BOOST_ATOMIC_INT128_LOCK_FREE > 0
-#if defined(__clang__) && defined(BOOST_ATOMIC_DETAIL_X86_HAS_CMPXCHG16B)
+#if (defined(__clang__) || (defined(BOOST_GCC) && (BOOST_GCC+0) >= 70000)) && defined(BOOST_ATOMIC_DETAIL_X86_HAS_CMPXCHG16B)
 
 // Workaround for clang bug: http://llvm.org/bugs/show_bug.cgi?id=19149
 // Clang 3.4 does not implement 128-bit __atomic* intrinsics even though it defines __GCC_HAVE_SYNC_COMPARE_AND_SWAP_16
+// A similar problem exists with gcc 7 as well, as it requires to link with libatomic to use 16-byte intrinsics:
+// https://gcc.gnu.org/bugzilla/show_bug.cgi?id=80878
 template< bool Signed >
 struct operations< 16u, Signed > :
     public cas_based_operations< gcc_dcas_x86_64< Signed > >
 {
+    static BOOST_CONSTEXPR_OR_CONST std::size_t storage_size = 16u;
+    static BOOST_CONSTEXPR_OR_CONST bool is_signed = Signed;
 };
 
 #else
 
 template< bool Signed >
 struct operations< 16u, Signed > :
-    public gcc_atomic_operations< typename make_storage_type< 16u, Signed >::type >
+    public gcc_atomic_operations< 16u, Signed >
 {
-    typedef typename make_storage_type< 16u, Signed >::aligned aligned_storage_type;
 };
 
 #endif
@@ -200,6 +204,8 @@ template< bool Signed >
 struct operations< 8u, Signed > :
     public cas_based_operations< gcc_dcas_x86< Signed > >
 {
+    static BOOST_CONSTEXPR_OR_CONST std::size_t storage_size = 8u;
+    static BOOST_CONSTEXPR_OR_CONST bool is_signed = Signed;
 };
 
 #elif (BOOST_ATOMIC_DETAIL_SIZEOF_LLONG == 8 && __GCC_ATOMIC_LLONG_LOCK_FREE != BOOST_ATOMIC_LLONG_LOCK_FREE) ||\
@@ -212,18 +218,16 @@ struct operations< 8u, Signed > :
 
 template< bool Signed >
 struct operations< 8u, Signed > :
-    public extending_cas_based_operations< gcc_atomic_operations< typename make_storage_type< 16u, Signed >::type >, 8u, Signed >
+    public extending_cas_based_operations< gcc_atomic_operations< 16u, Signed >, 8u, Signed >
 {
-    typedef typename make_storage_type< 16u, Signed >::aligned aligned_storage_type;
 };
 
 #else
 
 template< bool Signed >
 struct operations< 8u, Signed > :
-    public gcc_atomic_operations< typename make_storage_type< 8u, Signed >::type >
+    public gcc_atomic_operations< 8u, Signed >
 {
-    typedef typename make_storage_type< 8u, Signed >::aligned aligned_storage_type;
 };
 
 #endif
@@ -242,18 +246,16 @@ struct operations< 8u, Signed > :
 
 template< bool Signed >
 struct operations< 4u, Signed > :
-    public extending_cas_based_operations< gcc_atomic_operations< typename make_storage_type< 8u, Signed >::type >, 4u, Signed >
+    public extending_cas_based_operations< gcc_atomic_operations< 8u, Signed >, 4u, Signed >
 {
-    typedef typename make_storage_type< 8u, Signed >::aligned aligned_storage_type;
 };
 
 #else // !defined(BOOST_ATOMIC_DETAIL_INT64_EXTENDED)
 
 template< bool Signed >
 struct operations< 4u, Signed > :
-    public extending_cas_based_operations< gcc_atomic_operations< typename make_storage_type< 16u, Signed >::type >, 4u, Signed >
+    public extending_cas_based_operations< gcc_atomic_operations< 16u, Signed >, 4u, Signed >
 {
-    typedef typename make_storage_type< 16u, Signed >::aligned aligned_storage_type;
 };
 
 #endif // !defined(BOOST_ATOMIC_DETAIL_INT64_EXTENDED)
@@ -262,9 +264,8 @@ struct operations< 4u, Signed > :
 
 template< bool Signed >
 struct operations< 4u, Signed > :
-    public gcc_atomic_operations< typename make_storage_type< 4u, Signed >::type >
+    public gcc_atomic_operations< 4u, Signed >
 {
-    typedef typename make_storage_type< 4u, Signed >::aligned aligned_storage_type;
 };
 
 #endif
@@ -283,27 +284,24 @@ struct operations< 4u, Signed > :
 
 template< bool Signed >
 struct operations< 2u, Signed > :
-    public extending_cas_based_operations< gcc_atomic_operations< typename make_storage_type< 4u, Signed >::type >, 2u, Signed >
+    public extending_cas_based_operations< gcc_atomic_operations< 4u, Signed >, 2u, Signed >
 {
-    typedef typename make_storage_type< 4u, Signed >::aligned aligned_storage_type;
 };
 
 #elif !defined(BOOST_ATOMIC_DETAIL_INT64_EXTENDED)
 
 template< bool Signed >
 struct operations< 2u, Signed > :
-    public extending_cas_based_operations< gcc_atomic_operations< typename make_storage_type< 8u, Signed >::type >, 2u, Signed >
+    public extending_cas_based_operations< gcc_atomic_operations< 8u, Signed >, 2u, Signed >
 {
-    typedef typename make_storage_type< 8u, Signed >::aligned aligned_storage_type;
 };
 
 #else
 
 template< bool Signed >
 struct operations< 2u, Signed > :
-    public extending_cas_based_operations< gcc_atomic_operations< typename make_storage_type< 16u, Signed >::type >, 2u, Signed >
+    public extending_cas_based_operations< gcc_atomic_operations< 16u, Signed >, 2u, Signed >
 {
-    typedef typename make_storage_type< 16u, Signed >::aligned aligned_storage_type;
 };
 
 #endif
@@ -312,9 +310,8 @@ struct operations< 2u, Signed > :
 
 template< bool Signed >
 struct operations< 2u, Signed > :
-    public gcc_atomic_operations< typename make_storage_type< 2u, Signed >::type >
+    public gcc_atomic_operations< 2u, Signed >
 {
-    typedef typename make_storage_type< 2u, Signed >::aligned aligned_storage_type;
 };
 
 #endif
@@ -333,36 +330,32 @@ struct operations< 2u, Signed > :
 
 template< bool Signed >
 struct operations< 1u, Signed > :
-    public extending_cas_based_operations< gcc_atomic_operations< typename make_storage_type< 2u, Signed >::type >, 1u, Signed >
+    public extending_cas_based_operations< gcc_atomic_operations< 2u, Signed >, 1u, Signed >
 {
-    typedef typename make_storage_type< 2u, Signed >::aligned aligned_storage_type;
 };
 
 #elif !defined(BOOST_ATOMIC_DETAIL_INT32_EXTENDED)
 
 template< bool Signed >
 struct operations< 1u, Signed > :
-    public extending_cas_based_operations< gcc_atomic_operations< typename make_storage_type< 4u, Signed >::type >, 1u, Signed >
+    public extending_cas_based_operations< gcc_atomic_operations< 4u, Signed >, 1u, Signed >
 {
-    typedef typename make_storage_type< 4u, Signed >::aligned aligned_storage_type;
 };
 
 #elif !defined(BOOST_ATOMIC_DETAIL_INT64_EXTENDED)
 
 template< bool Signed >
 struct operations< 1u, Signed > :
-    public extending_cas_based_operations< gcc_atomic_operations< typename make_storage_type< 8u, Signed >::type >, 1u, Signed >
+    public extending_cas_based_operations< gcc_atomic_operations< 8u, Signed >, 1u, Signed >
 {
-    typedef typename make_storage_type< 8u, Signed >::aligned aligned_storage_type;
 };
 
 #else
 
 template< bool Signed >
 struct operations< 1u, Signed > :
-    public extending_cas_based_operations< gcc_atomic_operations< typename make_storage_type< 16u, Signed >::type >, 1u, Signed >
+    public extending_cas_based_operations< gcc_atomic_operations< 16u, Signed >, 1u, Signed >
 {
-    typedef typename make_storage_type< 16u, Signed >::aligned aligned_storage_type;
 };
 
 #endif
@@ -371,9 +364,8 @@ struct operations< 1u, Signed > :
 
 template< bool Signed >
 struct operations< 1u, Signed > :
-    public gcc_atomic_operations< typename make_storage_type< 1u, Signed >::type >
+    public gcc_atomic_operations< 1u, Signed >
 {
-    typedef typename make_storage_type< 1u, Signed >::aligned aligned_storage_type;
 };
 
 #endif

data/src/cxx_supportlib/vendor-modified/boost/atomic/detail/ops_gcc_ppc.hpp

@@ -16,10 +16,12 @@
 #ifndef BOOST_ATOMIC_DETAIL_OPS_GCC_PPC_HPP_INCLUDED_
 #define BOOST_ATOMIC_DETAIL_OPS_GCC_PPC_HPP_INCLUDED_
 
+#include <cstddef>
 #include <boost/memory_order.hpp>
 #include <boost/atomic/detail/config.hpp>
 #include <boost/atomic/detail/storage_type.hpp>
 #include <boost/atomic/detail/operations_fwd.hpp>
+#include <boost/atomic/detail/ops_gcc_ppc_common.hpp>
 #include <boost/atomic/capabilities.hpp>
 
 #ifdef BOOST_HAS_PRAGMA_ONCE
@@ -57,7 +59,9 @@ namespace detail {
     cycles, while "sync" hast a cost of about 50 clock cycles, the small
     penalty to atomic loads more than compensates for this.
 
-    Byte- and halfword-sized atomic values are realized by encoding the
+    Byte- and halfword-sized atomic values are implemented in two ways.
+    When 8 and 16-bit instructions are available (in Power8 and later),
+    they are used. Otherwise operations are realized by encoding the
     value to be represented into a word, performing sign/zero extension
     as appropriate. This means that after add/sub operations the value
     needs fixing up to accurately preserve the wrap-around semantic of
@@ -75,45 +79,15 @@ namespace detail {
     to pose a problem.
 */
 
-// A note about memory_order_consume. Technically, this architecture allows to avoid
-// unnecessary memory barrier after consume load since it supports data dependency ordering.
-// However, some compiler optimizations may break a seemingly valid code relying on data
-// dependency tracking by injecting bogus branches to aid out of order execution.
-// This may happen not only in Boost.Atomic code but also in user's code, which we have no
-// control of. See this thread: http://lists.boost.org/Archives/boost/2014/06/213890.php.
-// For this reason we promote memory_order_consume to memory_order_acquire.
-
-struct gcc_ppc_operations_base
-{
-    static BOOST_CONSTEXPR_OR_CONST bool is_always_lock_free = true;
-
-    static BOOST_FORCEINLINE void fence_before(memory_order order) BOOST_NOEXCEPT
-    {
-#if defined(__powerpc64__) || defined(__PPC64__)
-        if (order == memory_order_seq_cst)
-            __asm__ __volatile__ ("sync" ::: "memory");
-        else if ((order & memory_order_release) != 0)
-            __asm__ __volatile__ ("lwsync" ::: "memory");
-#else
-        if ((order & memory_order_release) != 0)
-            __asm__ __volatile__ ("sync" ::: "memory");
-#endif
-    }
-
-    static BOOST_FORCEINLINE void fence_after(memory_order order) BOOST_NOEXCEPT
-    {
-        if ((order & (memory_order_consume | memory_order_acquire)) != 0)
-            __asm__ __volatile__ ("isync" ::: "memory");
-    }
-};
-
-
 template< bool Signed >
 struct operations< 4u, Signed > :
     public gcc_ppc_operations_base
 {
-    typedef typename make_storage_type< 4u, Signed >::type storage_type;
-    typedef typename make_storage_type< 4u, Signed >::aligned aligned_storage_type;
+    typedef typename make_storage_type< 4u >::type storage_type;
+    typedef typename make_storage_type< 4u >::aligned aligned_storage_type;
+
+    static BOOST_CONSTEXPR_OR_CONST std::size_t storage_size = 4u;
+    static BOOST_CONSTEXPR_OR_CONST bool is_signed = Signed;
 
     static BOOST_FORCEINLINE void store(storage_type volatile& storage, storage_type v, memory_order order) BOOST_NOEXCEPT
     {
@@ -131,7 +105,7 @@ struct operations< 4u, Signed > :
         storage_type v;
         if (order == memory_order_seq_cst)
             __asm__ __volatile__ ("sync" ::: "memory");
-        if ((order & (memory_order_consume | memory_order_acquire)) != 0)
+        if ((static_cast< unsigned int >(order) & (static_cast< unsigned int >(memory_order_consume) | static_cast< unsigned int >(memory_order_acquire))) != 0u)
         {
             __asm__ __volatile__
             (
@@ -229,7 +203,7 @@ struct operations< 4u, Signed > :
 
     static BOOST_FORCEINLINE storage_type fetch_add(storage_type volatile& storage, storage_type v, memory_order order) BOOST_NOEXCEPT
     {
-        storage_type original, tmp;
+        storage_type original, result;
         fence_before(order);
         __asm__ __volatile__
         (
@@ -238,7 +212,7 @@ struct operations< 4u, Signed > :
             "add %1,%0,%3\n\t"
             "stwcx. %1,%y2\n\t"
             "bne- 1b\n\t"
-            : "=&b" (original), "=&b" (tmp), "+Z" (storage)
+            : "=&b" (original), "=&b" (result), "+Z" (storage)
             : "b" (v)
             : BOOST_ATOMIC_DETAIL_ASM_CLOBBER_CC
         );
@@ -248,7 +222,7 @@ struct operations< 4u, Signed > :
 
     static BOOST_FORCEINLINE storage_type fetch_sub(storage_type volatile& storage, storage_type v, memory_order order) BOOST_NOEXCEPT
     {
-        storage_type original, tmp;
+        storage_type original, result;
         fence_before(order);
         __asm__ __volatile__
         (
@@ -257,7 +231,7 @@ struct operations< 4u, Signed > :
             "sub %1,%0,%3\n\t"
             "stwcx. %1,%y2\n\t"
             "bne- 1b\n\t"
-            : "=&b" (original), "=&b" (tmp), "+Z" (storage)
+            : "=&b" (original), "=&b" (result), "+Z" (storage)
             : "b" (v)
             : BOOST_ATOMIC_DETAIL_ASM_CLOBBER_CC
         );
@@ -267,7 +241,7 @@ struct operations< 4u, Signed > :
 
     static BOOST_FORCEINLINE storage_type fetch_and(storage_type volatile& storage, storage_type v, memory_order order) BOOST_NOEXCEPT
     {
-        storage_type original, tmp;
+        storage_type original, result;
         fence_before(order);
         __asm__ __volatile__
         (
@@ -276,7 +250,7 @@ struct operations< 4u, Signed > :
             "and %1,%0,%3\n\t"
             "stwcx. %1,%y2\n\t"
             "bne- 1b\n\t"
-            : "=&b" (original), "=&b" (tmp), "+Z" (storage)
+            : "=&b" (original), "=&b" (result), "+Z" (storage)
             : "b" (v)
             : BOOST_ATOMIC_DETAIL_ASM_CLOBBER_CC
         );
@@ -286,7 +260,7 @@ struct operations< 4u, Signed > :
 
     static BOOST_FORCEINLINE storage_type fetch_or(storage_type volatile& storage, storage_type v, memory_order order) BOOST_NOEXCEPT
     {
-        storage_type original, tmp;
+        storage_type original, result;
         fence_before(order);
         __asm__ __volatile__
         (
@@ -295,7 +269,7 @@ struct operations< 4u, Signed > :
             "or %1,%0,%3\n\t"
             "stwcx. %1,%y2\n\t"
             "bne- 1b\n\t"
-            : "=&b" (original), "=&b" (tmp), "+Z" (storage)
+            : "=&b" (original), "=&b" (result), "+Z" (storage)
             : "b" (v)
             : BOOST_ATOMIC_DETAIL_ASM_CLOBBER_CC
         );
@@ -305,7 +279,7 @@ struct operations< 4u, Signed > :
 
     static BOOST_FORCEINLINE storage_type fetch_xor(storage_type volatile& storage, storage_type v, memory_order order) BOOST_NOEXCEPT
     {
-        storage_type original, tmp;
+        storage_type original, result;
         fence_before(order);
         __asm__ __volatile__
         (
@@ -314,7 +288,7 @@ struct operations< 4u, Signed > :
             "xor %1,%0,%3\n\t"
             "stwcx. %1,%y2\n\t"
             "bne- 1b\n\t"
-            : "=&b" (original), "=&b" (tmp), "+Z" (storage)
+            : "=&b" (original), "=&b" (result), "+Z" (storage)
             : "b" (v)
             : BOOST_ATOMIC_DETAIL_ASM_CLOBBER_CC
         );
@@ -331,13 +305,239 @@ struct operations< 4u, Signed > :
     {
         store(storage, 0, order);
     }
+};
+
+#if defined(BOOST_ATOMIC_DETAIL_PPC_HAS_LBARX_STBCX)
 
-    static BOOST_FORCEINLINE bool is_lock_free(storage_type const volatile&) BOOST_NOEXCEPT
+template< bool Signed >
+struct operations< 1u, Signed > :
+    public gcc_ppc_operations_base
+{
+    typedef typename make_storage_type< 1u >::type storage_type;
+    typedef typename make_storage_type< 1u >::aligned aligned_storage_type;
+
+    static BOOST_CONSTEXPR_OR_CONST std::size_t storage_size = 1u;
+    static BOOST_CONSTEXPR_OR_CONST bool is_signed = Signed;
+
+    static BOOST_FORCEINLINE void store(storage_type volatile& storage, storage_type v, memory_order order) BOOST_NOEXCEPT
     {
-        return true;
+        fence_before(order);
+        __asm__ __volatile__
+        (
+            "stb %1, %0\n\t"
+            : "+m" (storage)
+            : "r" (v)
+        );
+    }
+
+    static BOOST_FORCEINLINE storage_type load(storage_type const volatile& storage, memory_order order) BOOST_NOEXCEPT
+    {
+        storage_type v;
+        if (order == memory_order_seq_cst)
+            __asm__ __volatile__ ("sync" ::: "memory");
+        if ((static_cast< unsigned int >(order) & (static_cast< unsigned int >(memory_order_consume) | static_cast< unsigned int >(memory_order_acquire))) != 0u)
+        {
+            __asm__ __volatile__
+            (
+                "lbz %0, %1\n\t"
+                "cmpw %0, %0\n\t"
+                "bne- 1f\n\t"
+                "1:\n\t"
+                "isync\n\t"
+                : "=&r" (v)
+                : "m" (storage)
+                : "cr0", "memory"
+            );
+        }
+        else
+        {
+            __asm__ __volatile__
+            (
+                "lbz %0, %1\n\t"
+                : "=&r" (v)
+                : "m" (storage)
+            );
+        }
+        return v;
+    }
+
+    static BOOST_FORCEINLINE storage_type exchange(storage_type volatile& storage, storage_type v, memory_order order) BOOST_NOEXCEPT
+    {
+        storage_type original;
+        fence_before(order);
+        __asm__ __volatile__
+        (
+            "1:\n\t"
+            "lbarx %0,%y1\n\t"
+            "stbcx. %2,%y1\n\t"
+            "bne- 1b\n\t"
+            : "=&b" (original), "+Z" (storage)
+            : "b" (v)
+            : "cr0"
+        );
+        fence_after(order);
+        return original;
+    }
+
+    static BOOST_FORCEINLINE bool compare_exchange_weak(
+        storage_type volatile& storage, storage_type& expected, storage_type desired, memory_order success_order, memory_order failure_order) BOOST_NOEXCEPT
+    {
+        int success;
+        fence_before(success_order);
+        __asm__ __volatile__
+        (
+            "li %1, 0\n\t"
+            "lbarx %0,%y2\n\t"
+            "cmpw %0, %3\n\t"
+            "bne- 1f\n\t"
+            "stbcx. %4,%y2\n\t"
+            "bne- 1f\n\t"
+            "li %1, 1\n\t"
+            "1:\n\t"
+            : "=&b" (expected), "=&b" (success), "+Z" (storage)
+            : "b" (expected), "b" (desired)
+            : "cr0"
+        );
+        if (success)
+            fence_after(success_order);
+        else
+            fence_after(failure_order);
+        return !!success;
+    }
+
+    static BOOST_FORCEINLINE bool compare_exchange_strong(
+        storage_type volatile& storage, storage_type& expected, storage_type desired, memory_order success_order, memory_order failure_order) BOOST_NOEXCEPT
+    {
+        int success;
+        fence_before(success_order);
+        __asm__ __volatile__
+        (
+            "li %1, 0\n\t"
+            "0: lbarx %0,%y2\n\t"
+            "cmpw %0, %3\n\t"
+            "bne- 1f\n\t"
+            "stbcx. %4,%y2\n\t"
+            "bne- 0b\n\t"
+            "li %1, 1\n\t"
+            "1:\n\t"
+            : "=&b" (expected), "=&b" (success), "+Z" (storage)
+            : "b" (expected), "b" (desired)
+            : "cr0"
+        );
+        if (success)
+            fence_after(success_order);
+        else
+            fence_after(failure_order);
+        return !!success;
+    }
+
+    static BOOST_FORCEINLINE storage_type fetch_add(storage_type volatile& storage, storage_type v, memory_order order) BOOST_NOEXCEPT
+    {
+        storage_type original, result;
+        fence_before(order);
+        __asm__ __volatile__
+        (
+            "1:\n\t"
+            "lbarx %0,%y2\n\t"
+            "add %1,%0,%3\n\t"
+            "stbcx. %1,%y2\n\t"
+            "bne- 1b\n\t"
+            : "=&b" (original), "=&b" (result), "+Z" (storage)
+            : "b" (v)
+            : BOOST_ATOMIC_DETAIL_ASM_CLOBBER_CC
+        );
+        fence_after(order);
+        return original;
+    }
+
+    static BOOST_FORCEINLINE storage_type fetch_sub(storage_type volatile& storage, storage_type v, memory_order order) BOOST_NOEXCEPT
+    {
+        storage_type original, result;
+        fence_before(order);
+        __asm__ __volatile__
+        (
+            "1:\n\t"
+            "lbarx %0,%y2\n\t"
+            "sub %1,%0,%3\n\t"
+            "stbcx. %1,%y2\n\t"
+            "bne- 1b\n\t"
+            : "=&b" (original), "=&b" (result), "+Z" (storage)
+            : "b" (v)
+            : BOOST_ATOMIC_DETAIL_ASM_CLOBBER_CC
+        );
+        fence_after(order);
+        return original;
+    }
+
+    static BOOST_FORCEINLINE storage_type fetch_and(storage_type volatile& storage, storage_type v, memory_order order) BOOST_NOEXCEPT
+    {
+        storage_type original, result;
+        fence_before(order);
+        __asm__ __volatile__
+        (
+            "1:\n\t"
+            "lbarx %0,%y2\n\t"
+            "and %1,%0,%3\n\t"
+            "stbcx. %1,%y2\n\t"
+            "bne- 1b\n\t"
+            : "=&b" (original), "=&b" (result), "+Z" (storage)
+            : "b" (v)
+            : BOOST_ATOMIC_DETAIL_ASM_CLOBBER_CC
+        );
+        fence_after(order);
+        return original;
+    }
+
+    static BOOST_FORCEINLINE storage_type fetch_or(storage_type volatile& storage, storage_type v, memory_order order) BOOST_NOEXCEPT
+    {
+        storage_type original, result;
+        fence_before(order);
+        __asm__ __volatile__
+        (
+            "1:\n\t"
+            "lbarx %0,%y2\n\t"
+            "or %1,%0,%3\n\t"
+            "stbcx. %1,%y2\n\t"
+            "bne- 1b\n\t"
+            : "=&b" (original), "=&b" (result), "+Z" (storage)
+            : "b" (v)
+            : BOOST_ATOMIC_DETAIL_ASM_CLOBBER_CC
+        );
+        fence_after(order);
+        return original;
+    }
+
+    static BOOST_FORCEINLINE storage_type fetch_xor(storage_type volatile& storage, storage_type v, memory_order order) BOOST_NOEXCEPT
+    {
+        storage_type original, result;
+        fence_before(order);
+        __asm__ __volatile__
+        (
+            "1:\n\t"
+            "lbarx %0,%y2\n\t"
+            "xor %1,%0,%3\n\t"
+            "stbcx. %1,%y2\n\t"
+            "bne- 1b\n\t"
+            : "=&b" (original), "=&b" (result), "+Z" (storage)
+            : "b" (v)
+            : BOOST_ATOMIC_DETAIL_ASM_CLOBBER_CC
+        );
+        fence_after(order);
+        return original;
+    }
+
+    static BOOST_FORCEINLINE bool test_and_set(storage_type volatile& storage, memory_order order) BOOST_NOEXCEPT
+    {
+        return !!exchange(storage, (storage_type)1, order);
+    }
+
+    static BOOST_FORCEINLINE void clear(storage_type volatile& storage, memory_order order) BOOST_NOEXCEPT
+    {
+        store(storage, 0, order);
     }
 };
 
+#else // defined(BOOST_ATOMIC_DETAIL_PPC_HAS_LBARX_STBCX)
 
 template< >
 struct operations< 1u, false > :
@@ -348,7 +548,7 @@ struct operations< 1u, false > :
 
     static BOOST_FORCEINLINE storage_type fetch_add(storage_type volatile& storage, storage_type v, memory_order order) BOOST_NOEXCEPT
     {
-        storage_type original, tmp;
+        storage_type original, result;
         fence_before(order);
         __asm__ __volatile__
         (
@@ -358,7 +558,7 @@ struct operations< 1u, false > :
             "rlwinm %1, %1, 0, 0xff\n\t"
             "stwcx. %1,%y2\n\t"
             "bne- 1b\n\t"
-            : "=&b" (original), "=&b" (tmp), "+Z" (storage)
+            : "=&b" (original), "=&b" (result), "+Z" (storage)
             : "b" (v)
             : BOOST_ATOMIC_DETAIL_ASM_CLOBBER_CC
         );
@@ -368,7 +568,7 @@ struct operations< 1u, false > :
 
     static BOOST_FORCEINLINE storage_type fetch_sub(storage_type volatile& storage, storage_type v, memory_order order) BOOST_NOEXCEPT
     {
-        storage_type original, tmp;
+        storage_type original, result;
         fence_before(order);
         __asm__ __volatile__
         (
@@ -378,7 +578,7 @@ struct operations< 1u, false > :
             "rlwinm %1, %1, 0, 0xff\n\t"
             "stwcx. %1,%y2\n\t"
             "bne- 1b\n\t"
-            : "=&b" (original), "=&b" (tmp), "+Z" (storage)
+            : "=&b" (original), "=&b" (result), "+Z" (storage)
             : "b" (v)
             : BOOST_ATOMIC_DETAIL_ASM_CLOBBER_CC
         );
@@ -396,7 +596,7 @@ struct operations< 1u, true > :
 
     static BOOST_FORCEINLINE storage_type fetch_add(storage_type volatile& storage, storage_type v, memory_order order) BOOST_NOEXCEPT
     {
-        storage_type original, tmp;
+        storage_type original, result;
         fence_before(order);
         __asm__ __volatile__
         (
@@ -406,7 +606,7 @@ struct operations< 1u, true > :
             "extsb %1, %1\n\t"
             "stwcx. %1,%y2\n\t"
             "bne- 1b\n\t"
-            : "=&b" (original), "=&b" (tmp), "+Z" (storage)
+            : "=&b" (original), "=&b" (result), "+Z" (storage)
             : "b" (v)
             : BOOST_ATOMIC_DETAIL_ASM_CLOBBER_CC
         );
@@ -416,7 +616,7 @@ struct operations< 1u, true > :
 
     static BOOST_FORCEINLINE storage_type fetch_sub(storage_type volatile& storage, storage_type v, memory_order order) BOOST_NOEXCEPT
     {
-        storage_type original, tmp;
+        storage_type original, result;
         fence_before(order);
         __asm__ __volatile__
         (
@@ -426,15 +626,248 @@ struct operations< 1u, true > :
             "extsb %1, %1\n\t"
             "stwcx. %1,%y2\n\t"
             "bne- 1b\n\t"
-            : "=&b" (original), "=&b" (tmp), "+Z" (storage)
+            : "=&b" (original), "=&b" (result), "+Z" (storage)
+            : "b" (v)
+            : BOOST_ATOMIC_DETAIL_ASM_CLOBBER_CC
+        );
+        fence_after(order);
+        return original;
+    }
+};
+
+#endif // defined(BOOST_ATOMIC_DETAIL_PPC_HAS_LBARX_STBCX)
+
+#if defined(BOOST_ATOMIC_DETAIL_PPC_HAS_LHARX_STHCX)
+
+template< bool Signed >
+struct operations< 2u, Signed > :
+    public gcc_ppc_operations_base
+{
+    typedef typename make_storage_type< 2u >::type storage_type;
+    typedef typename make_storage_type< 2u >::aligned aligned_storage_type;
+
+    static BOOST_CONSTEXPR_OR_CONST std::size_t storage_size = 2u;
+    static BOOST_CONSTEXPR_OR_CONST bool is_signed = Signed;
+
+    static BOOST_FORCEINLINE void store(storage_type volatile& storage, storage_type v, memory_order order) BOOST_NOEXCEPT
+    {
+        fence_before(order);
+        __asm__ __volatile__
+        (
+            "sth %1, %0\n\t"
+            : "+m" (storage)
+            : "r" (v)
+        );
+    }
+
+    static BOOST_FORCEINLINE storage_type load(storage_type const volatile& storage, memory_order order) BOOST_NOEXCEPT
+    {
+        storage_type v;
+        if (order == memory_order_seq_cst)
+            __asm__ __volatile__ ("sync" ::: "memory");
+        if ((static_cast< unsigned int >(order) & (static_cast< unsigned int >(memory_order_consume) | static_cast< unsigned int >(memory_order_acquire))) != 0u)
+        {
+            __asm__ __volatile__
+            (
+                "lhz %0, %1\n\t"
+                "cmpw %0, %0\n\t"
+                "bne- 1f\n\t"
+                "1:\n\t"
+                "isync\n\t"
+                : "=&r" (v)
+                : "m" (storage)
+                : "cr0", "memory"
+            );
+        }
+        else
+        {
+            __asm__ __volatile__
+            (
+                "lhz %0, %1\n\t"
+                : "=&r" (v)
+                : "m" (storage)
+            );
+        }
+        return v;
+    }
+
+    static BOOST_FORCEINLINE storage_type exchange(storage_type volatile& storage, storage_type v, memory_order order) BOOST_NOEXCEPT
+    {
+        storage_type original;
+        fence_before(order);
+        __asm__ __volatile__
+        (
+            "1:\n\t"
+            "lharx %0,%y1\n\t"
+            "sthcx. %2,%y1\n\t"
+            "bne- 1b\n\t"
+            : "=&b" (original), "+Z" (storage)
+            : "b" (v)
+            : "cr0"
+        );
+        fence_after(order);
+        return original;
+    }
+
+    static BOOST_FORCEINLINE bool compare_exchange_weak(
+        storage_type volatile& storage, storage_type& expected, storage_type desired, memory_order success_order, memory_order failure_order) BOOST_NOEXCEPT
+    {
+        int success;
+        fence_before(success_order);
+        __asm__ __volatile__
+        (
+            "li %1, 0\n\t"
+            "lharx %0,%y2\n\t"
+            "cmpw %0, %3\n\t"
+            "bne- 1f\n\t"
+            "sthcx. %4,%y2\n\t"
+            "bne- 1f\n\t"
+            "li %1, 1\n\t"
+            "1:\n\t"
+            : "=&b" (expected), "=&b" (success), "+Z" (storage)
+            : "b" (expected), "b" (desired)
+            : "cr0"
+        );
+        if (success)
+            fence_after(success_order);
+        else
+            fence_after(failure_order);
+        return !!success;
+    }
+
+    static BOOST_FORCEINLINE bool compare_exchange_strong(
+        storage_type volatile& storage, storage_type& expected, storage_type desired, memory_order success_order, memory_order failure_order) BOOST_NOEXCEPT
+    {
+        int success;
+        fence_before(success_order);
+        __asm__ __volatile__
+        (
+            "li %1, 0\n\t"
+            "0: lharx %0,%y2\n\t"
+            "cmpw %0, %3\n\t"
+            "bne- 1f\n\t"
+            "sthcx. %4,%y2\n\t"
+            "bne- 0b\n\t"
+            "li %1, 1\n\t"
+            "1:\n\t"
+            : "=&b" (expected), "=&b" (success), "+Z" (storage)
+            : "b" (expected), "b" (desired)
+            : "cr0"
+        );
+        if (success)
+            fence_after(success_order);
+        else
+            fence_after(failure_order);
+        return !!success;
+    }
+
+    static BOOST_FORCEINLINE storage_type fetch_add(storage_type volatile& storage, storage_type v, memory_order order) BOOST_NOEXCEPT
+    {
+        storage_type original, result;
+        fence_before(order);
+        __asm__ __volatile__
+        (
+            "1:\n\t"
+            "lharx %0,%y2\n\t"
+            "add %1,%0,%3\n\t"
+            "sthcx. %1,%y2\n\t"
+            "bne- 1b\n\t"
+            : "=&b" (original), "=&b" (result), "+Z" (storage)
+            : "b" (v)
+            : BOOST_ATOMIC_DETAIL_ASM_CLOBBER_CC
+        );
+        fence_after(order);
+        return original;
+    }
+
+    static BOOST_FORCEINLINE storage_type fetch_sub(storage_type volatile& storage, storage_type v, memory_order order) BOOST_NOEXCEPT
+    {
+        storage_type original, result;
+        fence_before(order);
+        __asm__ __volatile__
+        (
+            "1:\n\t"
+            "lharx %0,%y2\n\t"
+            "sub %1,%0,%3\n\t"
+            "sthcx. %1,%y2\n\t"
+            "bne- 1b\n\t"
+            : "=&b" (original), "=&b" (result), "+Z" (storage)
+            : "b" (v)
+            : BOOST_ATOMIC_DETAIL_ASM_CLOBBER_CC
+        );
+        fence_after(order);
+        return original;
+    }
+
+    static BOOST_FORCEINLINE storage_type fetch_and(storage_type volatile& storage, storage_type v, memory_order order) BOOST_NOEXCEPT
+    {
+        storage_type original, result;
+        fence_before(order);
+        __asm__ __volatile__
+        (
+            "1:\n\t"
+            "lharx %0,%y2\n\t"
+            "and %1,%0,%3\n\t"
+            "sthcx. %1,%y2\n\t"
+            "bne- 1b\n\t"
+            : "=&b" (original), "=&b" (result), "+Z" (storage)
             : "b" (v)
             : BOOST_ATOMIC_DETAIL_ASM_CLOBBER_CC
         );
         fence_after(order);
         return original;
     }
+
+    static BOOST_FORCEINLINE storage_type fetch_or(storage_type volatile& storage, storage_type v, memory_order order) BOOST_NOEXCEPT
+    {
+        storage_type original, result;
+        fence_before(order);
+        __asm__ __volatile__
+        (
+            "1:\n\t"
+            "lharx %0,%y2\n\t"
+            "or %1,%0,%3\n\t"
+            "sthcx. %1,%y2\n\t"
+            "bne- 1b\n\t"
+            : "=&b" (original), "=&b" (result), "+Z" (storage)
+            : "b" (v)
+            : BOOST_ATOMIC_DETAIL_ASM_CLOBBER_CC
+        );
+        fence_after(order);
+        return original;
+    }
+
+    static BOOST_FORCEINLINE storage_type fetch_xor(storage_type volatile& storage, storage_type v, memory_order order) BOOST_NOEXCEPT
+    {
+        storage_type original, result;
+        fence_before(order);
+        __asm__ __volatile__
+        (
+            "1:\n\t"
+            "lharx %0,%y2\n\t"
+            "xor %1,%0,%3\n\t"
+            "sthcx. %1,%y2\n\t"
+            "bne- 1b\n\t"
+            : "=&b" (original), "=&b" (result), "+Z" (storage)
+            : "b" (v)
+            : BOOST_ATOMIC_DETAIL_ASM_CLOBBER_CC
+        );
+        fence_after(order);
+        return original;
+    }
+
+    static BOOST_FORCEINLINE bool test_and_set(storage_type volatile& storage, memory_order order) BOOST_NOEXCEPT
+    {
+        return !!exchange(storage, (storage_type)1, order);
+    }
+
+    static BOOST_FORCEINLINE void clear(storage_type volatile& storage, memory_order order) BOOST_NOEXCEPT
+    {
+        store(storage, 0, order);
+    }
 };
 
+#else // defined(BOOST_ATOMIC_DETAIL_PPC_HAS_LHARX_STHCX)
 
 template< >
 struct operations< 2u, false > :
@@ -445,7 +878,7 @@ struct operations< 2u, false > :
 
     static BOOST_FORCEINLINE storage_type fetch_add(storage_type volatile& storage, storage_type v, memory_order order) BOOST_NOEXCEPT
     {
-        storage_type original, tmp;
+        storage_type original, result;
         fence_before(order);
         __asm__ __volatile__
         (
@@ -455,7 +888,7 @@ struct operations< 2u, false > :
             "rlwinm %1, %1, 0, 0xffff\n\t"
             "stwcx. %1,%y2\n\t"
             "bne- 1b\n\t"
-            : "=&b" (original), "=&b" (tmp), "+Z" (storage)
+            : "=&b" (original), "=&b" (result), "+Z" (storage)
             : "b" (v)
             : BOOST_ATOMIC_DETAIL_ASM_CLOBBER_CC
         );
@@ -465,7 +898,7 @@ struct operations< 2u, false > :
 
     static BOOST_FORCEINLINE storage_type fetch_sub(storage_type volatile& storage, storage_type v, memory_order order) BOOST_NOEXCEPT
     {
-        storage_type original, tmp;
+        storage_type original, result;
         fence_before(order);
         __asm__ __volatile__
         (
@@ -475,7 +908,7 @@ struct operations< 2u, false > :
             "rlwinm %1, %1, 0, 0xffff\n\t"
             "stwcx. %1,%y2\n\t"
             "bne- 1b\n\t"
-            : "=&b" (original), "=&b" (tmp), "+Z" (storage)
+            : "=&b" (original), "=&b" (result), "+Z" (storage)
             : "b" (v)
             : BOOST_ATOMIC_DETAIL_ASM_CLOBBER_CC
         );
@@ -493,7 +926,7 @@ struct operations< 2u, true > :
 
     static BOOST_FORCEINLINE storage_type fetch_add(storage_type volatile& storage, storage_type v, memory_order order) BOOST_NOEXCEPT
     {
-        storage_type original, tmp;
+        storage_type original, result;
         fence_before(order);
         __asm__ __volatile__
         (
@@ -503,7 +936,7 @@ struct operations< 2u, true > :
             "extsh %1, %1\n\t"
             "stwcx. %1,%y2\n\t"
             "bne- 1b\n\t"
-            : "=&b" (original), "=&b" (tmp), "+Z" (storage)
+            : "=&b" (original), "=&b" (result), "+Z" (storage)
             : "b" (v)
             : BOOST_ATOMIC_DETAIL_ASM_CLOBBER_CC
         );
@@ -513,7 +946,7 @@ struct operations< 2u, true > :
 
     static BOOST_FORCEINLINE storage_type fetch_sub(storage_type volatile& storage, storage_type v, memory_order order) BOOST_NOEXCEPT
     {
-        storage_type original, tmp;
+        storage_type original, result;
         fence_before(order);
         __asm__ __volatile__
         (
@@ -523,7 +956,7 @@ struct operations< 2u, true > :
             "extsh %1, %1\n\t"
             "stwcx. %1,%y2\n\t"
             "bne- 1b\n\t"
-            : "=&b" (original), "=&b" (tmp), "+Z" (storage)
+            : "=&b" (original), "=&b" (result), "+Z" (storage)
             : "b" (v)
             : BOOST_ATOMIC_DETAIL_ASM_CLOBBER_CC
         );
@@ -532,15 +965,19 @@ struct operations< 2u, true > :
     }
 };
 
+#endif // defined(BOOST_ATOMIC_DETAIL_PPC_HAS_LHARX_STHCX)
 
-#if defined(__powerpc64__) || defined(__PPC64__)
+#if defined(BOOST_ATOMIC_DETAIL_PPC_HAS_LDARX_STDCX)
 
 template< bool Signed >
 struct operations< 8u, Signed > :
     public gcc_ppc_operations_base
 {
-    typedef typename make_storage_type< 8u, Signed >::type storage_type;
-    typedef typename make_storage_type< 8u, Signed >::aligned aligned_storage_type;
+    typedef typename make_storage_type< 8u >::type storage_type;
+    typedef typename make_storage_type< 8u >::aligned aligned_storage_type;
+
+    static BOOST_CONSTEXPR_OR_CONST std::size_t storage_size = 8u;
+    static BOOST_CONSTEXPR_OR_CONST bool is_signed = Signed;
 
     static BOOST_FORCEINLINE void store(storage_type volatile& storage, storage_type v, memory_order order) BOOST_NOEXCEPT
     {
@@ -558,7 +995,7 @@ struct operations< 8u, Signed > :
         storage_type v;
         if (order == memory_order_seq_cst)
             __asm__ __volatile__ ("sync" ::: "memory");
-        if ((order & (memory_order_consume | memory_order_acquire)) != 0)
+        if ((static_cast< unsigned int >(order) & (static_cast< unsigned int >(memory_order_consume) | static_cast< unsigned int >(memory_order_acquire))) != 0u)
         {
             __asm__ __volatile__
             (
@@ -656,7 +1093,7 @@ struct operations< 8u, Signed > :
 
     static BOOST_FORCEINLINE storage_type fetch_add(storage_type volatile& storage, storage_type v, memory_order order) BOOST_NOEXCEPT
     {
-        storage_type original, tmp;
+        storage_type original, result;
         fence_before(order);
         __asm__ __volatile__
         (
@@ -665,7 +1102,7 @@ struct operations< 8u, Signed > :
             "add %1,%0,%3\n\t"
             "stdcx. %1,%y2\n\t"
             "bne- 1b\n\t"
-            : "=&b" (original), "=&b" (tmp), "+Z" (storage)
+            : "=&b" (original), "=&b" (result), "+Z" (storage)
             : "b" (v)
             : BOOST_ATOMIC_DETAIL_ASM_CLOBBER_CC
         );
@@ -675,7 +1112,7 @@ struct operations< 8u, Signed > :
 
     static BOOST_FORCEINLINE storage_type fetch_sub(storage_type volatile& storage, storage_type v, memory_order order) BOOST_NOEXCEPT
     {
-        storage_type original, tmp;
+        storage_type original, result;
         fence_before(order);
         __asm__ __volatile__
         (
@@ -684,7 +1121,7 @@ struct operations< 8u, Signed > :
             "sub %1,%0,%3\n\t"
             "stdcx. %1,%y2\n\t"
             "bne- 1b\n\t"
-            : "=&b" (original), "=&b" (tmp), "+Z" (storage)
+            : "=&b" (original), "=&b" (result), "+Z" (storage)
             : "b" (v)
             : BOOST_ATOMIC_DETAIL_ASM_CLOBBER_CC
         );
@@ -694,7 +1131,7 @@ struct operations< 8u, Signed > :
 
     static BOOST_FORCEINLINE storage_type fetch_and(storage_type volatile& storage, storage_type v, memory_order order) BOOST_NOEXCEPT
     {
-        storage_type original, tmp;
+        storage_type original, result;
         fence_before(order);
         __asm__ __volatile__
         (
@@ -703,7 +1140,7 @@ struct operations< 8u, Signed > :
             "and %1,%0,%3\n\t"
             "stdcx. %1,%y2\n\t"
             "bne- 1b\n\t"
-            : "=&b" (original), "=&b" (tmp), "+Z" (storage)
+            : "=&b" (original), "=&b" (result), "+Z" (storage)
             : "b" (v)
             : BOOST_ATOMIC_DETAIL_ASM_CLOBBER_CC
         );
@@ -713,7 +1150,7 @@ struct operations< 8u, Signed > :
 
     static BOOST_FORCEINLINE storage_type fetch_or(storage_type volatile& storage, storage_type v, memory_order order) BOOST_NOEXCEPT
     {
-        storage_type original, tmp;
+        storage_type original, result;
         fence_before(order);
         __asm__ __volatile__
         (
@@ -722,7 +1159,7 @@ struct operations< 8u, Signed > :
             "or %1,%0,%3\n\t"
             "stdcx. %1,%y2\n\t"
             "bne- 1b\n\t"
-            : "=&b" (original), "=&b" (tmp), "+Z" (storage)
+            : "=&b" (original), "=&b" (result), "+Z" (storage)
             : "b" (v)
             : BOOST_ATOMIC_DETAIL_ASM_CLOBBER_CC
         );
@@ -732,7 +1169,7 @@ struct operations< 8u, Signed > :
 
     static BOOST_FORCEINLINE storage_type fetch_xor(storage_type volatile& storage, storage_type v, memory_order order) BOOST_NOEXCEPT
     {
-        storage_type original, tmp;
+        storage_type original, result;
         fence_before(order);
         __asm__ __volatile__
         (
@@ -741,7 +1178,7 @@ struct operations< 8u, Signed > :
             "xor %1,%0,%3\n\t"
             "stdcx. %1,%y2\n\t"
             "bne- 1b\n\t"
-            : "=&b" (original), "=&b" (tmp), "+Z" (storage)
+            : "=&b" (original), "=&b" (result), "+Z" (storage)
             : "b" (v)
             : BOOST_ATOMIC_DETAIL_ASM_CLOBBER_CC
         );
@@ -758,32 +1195,23 @@ struct operations< 8u, Signed > :
     {
         store(storage, 0, order);
     }
-
-    static BOOST_FORCEINLINE bool is_lock_free(storage_type const volatile&) BOOST_NOEXCEPT
-    {
-        return true;
-    }
 };
 
-#endif // defined(__powerpc64__) || defined(__PPC64__)
+#endif // defined(BOOST_ATOMIC_DETAIL_PPC_HAS_LDARX_STDCX)
 
 
 BOOST_FORCEINLINE void thread_fence(memory_order order) BOOST_NOEXCEPT
 {
-    switch (order)
+    if (order != memory_order_relaxed)
     {
-    case memory_order_consume:
-    case memory_order_acquire:
-    case memory_order_release:
-    case memory_order_acq_rel:
 #if defined(__powerpc64__) || defined(__PPC64__)
-        __asm__ __volatile__ ("lwsync" ::: "memory");
-        break;
-#endif
-    case memory_order_seq_cst:
+        if (order != memory_order_seq_cst)
+            __asm__ __volatile__ ("lwsync" ::: "memory");
+        else
+            __asm__ __volatile__ ("sync" ::: "memory");
+#else
         __asm__ __volatile__ ("sync" ::: "memory");
-        break;
-    default:;
+#endif
     }
 }