passenger 5.3.3 → 5.3.4

data/src/cxx_supportlib/vendor-modified/boost/atomic/detail/hwcaps_gcc_x86.hpp

@@ -0,0 +1,58 @@
+/*
+ * Distributed under the Boost Software License, Version 1.0.
+ * (See accompanying file LICENSE_1_0.txt or copy at
+ * http://www.boost.org/LICENSE_1_0.txt)
+ *
+ * Copyright (c) 2017 Andrey Semashev
+ */
+/*!
+ * \file   atomic/detail/hwcaps_gcc_x86.hpp
+ *
+ * This header defines hardware capabilities macros for x86
+ */
+
+#ifndef BOOST_ATOMIC_DETAIL_HWCAPS_GCC_X86_HPP_INCLUDED_
+#define BOOST_ATOMIC_DETAIL_HWCAPS_GCC_X86_HPP_INCLUDED_
+
+#include <boost/atomic/detail/config.hpp>
+
+#ifdef BOOST_HAS_PRAGMA_ONCE
+#pragma once
+#endif
+
+#if defined(__GNUC__)
+
+#if defined(__i386__) &&\
+    (\
+        defined(__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8) ||\
+        defined(__i586__) || defined(__i686__) || defined(__SSE__)\
+    )
+#define BOOST_ATOMIC_DETAIL_X86_HAS_CMPXCHG8B 1
+#endif
+
+#if defined(__x86_64__) && defined(__GCC_HAVE_SYNC_COMPARE_AND_SWAP_16)
+#define BOOST_ATOMIC_DETAIL_X86_HAS_CMPXCHG16B 1
+#endif
+
+#if defined(__x86_64__) || defined(__SSE2__)
+// Use mfence only if SSE2 is available
+#define BOOST_ATOMIC_DETAIL_X86_HAS_MFENCE 1
+#endif
+
+#else // defined(__GNUC__)
+
+#if defined(__i386__) && !defined(BOOST_ATOMIC_NO_CMPXCHG8B)
+#define BOOST_ATOMIC_DETAIL_X86_HAS_CMPXCHG8B 1
+#endif
+
+#if defined(__x86_64__) && !defined(BOOST_ATOMIC_NO_CMPXCHG16B)
+#define BOOST_ATOMIC_DETAIL_X86_HAS_CMPXCHG16B 1
+#endif
+
+#if !defined(BOOST_ATOMIC_NO_MFENCE)
+#define BOOST_ATOMIC_DETAIL_X86_HAS_MFENCE 1
+#endif
+
+#endif // defined(__GNUC__)
+
+#endif // BOOST_ATOMIC_DETAIL_HWCAPS_GCC_X86_HPP_INCLUDED_

data/src/cxx_supportlib/vendor-modified/boost/atomic/detail/int_sizes.hpp

@@ -39,7 +39,7 @@
 #if defined(__SIZEOF_POINTER__)
 #define BOOST_ATOMIC_DETAIL_SIZEOF_POINTER __SIZEOF_POINTER__
 #elif defined(_MSC_VER)
-#if defined(_M_AMD64) || defined(_M_IA64)
+#if defined(_M_AMD64) || defined(_M_ARM64) || defined(_M_IA64)
 #define BOOST_ATOMIC_DETAIL_SIZEOF_POINTER 8
 #else
 #define BOOST_ATOMIC_DETAIL_SIZEOF_POINTER 4
@@ -117,7 +117,7 @@
 #include <wchar.h>
 #include <boost/cstdint.hpp>
 
- #if defined(_MSC_VER) && ( _MSC_VER <= 1310 || defined(UNDER_CE) && _MSC_VER <= 1500 )
+#if defined(_MSC_VER) && (_MSC_VER <= 1310 || defined(UNDER_CE) && _MSC_VER <= 1500)
 // MSVC 7.1 and MSVC 8 (arm) define WCHAR_MAX to a value not suitable for constant expressions
 #define BOOST_ATOMIC_DETAIL_SIZEOF_WCHAR_T 2
 #elif (WCHAR_MAX + 0) == 0xff || (WCHAR_MAX + 0) == 0x7f
@@ -134,7 +134,7 @@
 #if !defined(BOOST_ATOMIC_DETAIL_SIZEOF_SHORT) || !defined(BOOST_ATOMIC_DETAIL_SIZEOF_INT) ||\
     !defined(BOOST_ATOMIC_DETAIL_SIZEOF_LONG) || !defined(BOOST_ATOMIC_DETAIL_SIZEOF_LLONG) ||\
     !defined(BOOST_ATOMIC_DETAIL_SIZEOF_WCHAR_T)
-#error Boost.Atomic: Failed to determine builtin integer sizes, the target platform is not supported. Please, report to the developers.
+#error Boost.Atomic: Failed to determine builtin integer sizes, the target platform is not supported. Please, report to the developers (patches are welcome).
 #endif
 
 #endif // BOOST_ATOMIC_DETAIL_INT_SIZES_HPP_INCLUDED_

data/src/cxx_supportlib/vendor-modified/boost/atomic/detail/integral_extend.hpp

@@ -0,0 +1,105 @@
+/*
+ * Distributed under the Boost Software License, Version 1.0.
+ * (See accompanying file LICENSE_1_0.txt or copy at
+ * http://www.boost.org/LICENSE_1_0.txt)
+ *
+ * Copyright (c) 2018 Andrey Semashev
+ */
+/*!
+ * \file   atomic/detail/integral_extend.hpp
+ *
+ * This header defines sign/zero extension utilities for Boost.Atomic. The tools assume two's complement signed integer representation.
+ */
+
+#ifndef BOOST_ATOMIC_DETAIL_INTEGRAL_EXTEND_HPP_INCLUDED_
+#define BOOST_ATOMIC_DETAIL_INTEGRAL_EXTEND_HPP_INCLUDED_
+
+#include <boost/atomic/detail/config.hpp>
+#include <boost/atomic/detail/bitwise_cast.hpp>
+#include <boost/atomic/detail/type_traits/integral_constant.hpp>
+#include <boost/atomic/detail/type_traits/is_signed.hpp>
+#include <boost/atomic/detail/type_traits/make_signed.hpp>
+#include <boost/atomic/detail/type_traits/make_unsigned.hpp>
+
+#ifdef BOOST_HAS_PRAGMA_ONCE
+#pragma once
+#endif
+
+namespace boost {
+namespace atomics {
+namespace detail {
+
+template< typename Output, typename Input >
+BOOST_FORCEINLINE Output zero_extend_impl(Input input, atomics::detail::true_type) BOOST_NOEXCEPT
+{
+    // Note: If we are casting with truncation or to the same-sized output, don't cause signed integer overflow by this chain of conversions
+    return atomics::detail::bitwise_cast< Output >(static_cast< typename atomics::detail::make_unsigned< Output >::type >(
+        static_cast< typename atomics::detail::make_unsigned< Input >::type >(input)));
+}
+
+template< typename Output, typename Input >
+BOOST_FORCEINLINE Output zero_extend_impl(Input input, atomics::detail::false_type) BOOST_NOEXCEPT
+{
+    return static_cast< Output >(static_cast< typename atomics::detail::make_unsigned< Input >::type >(input));
+}
+
+//! Zero-extends or truncates (wraps) input operand to fit in the output type
+template< typename Output, typename Input >
+BOOST_FORCEINLINE Output zero_extend(Input input) BOOST_NOEXCEPT
+{
+    return atomics::detail::zero_extend_impl< Output >(input, atomics::detail::integral_constant< bool, atomics::detail::is_signed< Output >::value >());
+}
+
+//! Truncates (wraps) input operand to fit in the output type
+template< typename Output, typename Input >
+BOOST_FORCEINLINE Output integral_truncate(Input input) BOOST_NOEXCEPT
+{
+    // zero_extend does the truncation
+    return atomics::detail::zero_extend< Output >(input);
+}
+
+template< typename Output, typename Input >
+BOOST_FORCEINLINE Output sign_extend_impl(Input input, atomics::detail::true_type) BOOST_NOEXCEPT
+{
+    return atomics::detail::integral_truncate< Output >(input);
+}
+
+template< typename Output, typename Input >
+BOOST_FORCEINLINE Output sign_extend_impl(Input input, atomics::detail::false_type) BOOST_NOEXCEPT
+{
+    return static_cast< Output >(atomics::detail::bitwise_cast< typename atomics::detail::make_signed< Input >::type >(input));
+}
+
+//! Sign-extends or truncates (wraps) input operand to fit in the output type
+template< typename Output, typename Input >
+BOOST_FORCEINLINE Output sign_extend(Input input) BOOST_NOEXCEPT
+{
+    return atomics::detail::sign_extend_impl< Output >(input, atomics::detail::integral_constant< bool, sizeof(Output) <= sizeof(Input) >());
+}
+
+//! Sign-extends or truncates (wraps) input operand to fit in the output type
+template< typename Output, typename Input >
+BOOST_FORCEINLINE Output integral_extend(Input input, atomics::detail::true_type) BOOST_NOEXCEPT
+{
+    return atomics::detail::sign_extend< Output >(input);
+}
+
+//! Zero-extends or truncates (wraps) input operand to fit in the output type
+template< typename Output, typename Input >
+BOOST_FORCEINLINE Output integral_extend(Input input, atomics::detail::false_type) BOOST_NOEXCEPT
+{
+    return atomics::detail::zero_extend< Output >(input);
+}
+
+//! Sign- or zero-extends or truncates (wraps) input operand to fit in the output type
+template< bool Signed, typename Output, typename Input >
+BOOST_FORCEINLINE Output integral_extend(Input input) BOOST_NOEXCEPT
+{
+    return atomics::detail::integral_extend< Output >(input, atomics::detail::integral_constant< bool, Signed >());
+}
+
+} // namespace detail
+} // namespace atomics
+} // namespace boost
+
+#endif // BOOST_ATOMIC_DETAIL_INTEGRAL_EXTEND_HPP_INCLUDED_

data/src/cxx_supportlib/vendor-modified/boost/atomic/detail/interlocked.hpp

@@ -2,7 +2,7 @@
 #define BOOST_ATOMIC_DETAIL_INTERLOCKED_HPP
 
 //  Copyright (c) 2009 Helge Bahmann
-//  Copyright (c) 2012 - 2014 Andrey Semashev
+//  Copyright (c) 2012 - 2014, 2017 Andrey Semashev
 //
 //  Distributed under the Boost Software License, Version 1.0.
 //  See accompanying file LICENSE_1_0.txt or copy at
@@ -73,6 +73,8 @@ extern "C" long __cdecl _InterlockedExchange( long volatile *, long );
 #pragma intrinsic(_InterlockedAnd)
 #pragma intrinsic(_InterlockedOr)
 #pragma intrinsic(_InterlockedXor)
+#pragma intrinsic(_interlockedbittestandset)
+#pragma intrinsic(_interlockedbittestandreset)
 #endif
 
 #define BOOST_ATOMIC_INTERLOCKED_COMPARE_EXCHANGE(dest, exchange, compare) _InterlockedCompareExchange((long*)(dest), (long)(exchange), (long)(compare))
@@ -81,6 +83,18 @@ extern "C" long __cdecl _InterlockedExchange( long volatile *, long );
 #define BOOST_ATOMIC_INTERLOCKED_AND(dest, arg) _InterlockedAnd((long*)(dest), (long)(arg))
 #define BOOST_ATOMIC_INTERLOCKED_OR(dest, arg) _InterlockedOr((long*)(dest), (long)(arg))
 #define BOOST_ATOMIC_INTERLOCKED_XOR(dest, arg) _InterlockedXor((long*)(dest), (long)(arg))
+#define BOOST_ATOMIC_INTERLOCKED_BTS(dest, arg) _interlockedbittestandset((long*)(dest), (long)(arg))
+#define BOOST_ATOMIC_INTERLOCKED_BTR(dest, arg) _interlockedbittestandreset((long*)(dest), (long)(arg))
+
+#if defined(_M_AMD64)
+#if defined(BOOST_MSVC)
+#pragma intrinsic(_interlockedbittestandset64)
+#pragma intrinsic(_interlockedbittestandreset64)
+#endif
+
+#define BOOST_ATOMIC_INTERLOCKED_BTS64(dest, arg) _interlockedbittestandset64((__int64*)(dest), (__int64)(arg))
+#define BOOST_ATOMIC_INTERLOCKED_BTR64(dest, arg) _interlockedbittestandreset64((__int64*)(dest), (__int64)(arg))
+#endif // defined(_M_AMD64)
 
 #if (defined(_M_IX86) && _M_IX86 >= 500) || defined(_M_AMD64) || defined(_M_IA64)
 #if defined(BOOST_MSVC)
@@ -394,6 +408,26 @@ extern "C" long __cdecl _InterlockedExchange( long volatile *, long );
 #define BOOST_ATOMIC_INTERLOCKED_XOR64_ACQUIRE(dest, arg) _InterlockedXor64_acq((__int64*)(dest), (__int64)(arg))
 #define BOOST_ATOMIC_INTERLOCKED_XOR64_RELEASE(dest, arg) _InterlockedXor64_rel((__int64*)(dest), (__int64)(arg))
 
+#if defined(BOOST_MSVC)
+#pragma intrinsic(_interlockedbittestandset_nf)
+#pragma intrinsic(_interlockedbittestandset_acq)
+#pragma intrinsic(_interlockedbittestandset_rel)
+#endif
+
+#define BOOST_ATOMIC_INTERLOCKED_BTS_RELAXED(dest, arg) _interlockedbittestandset_nf((long*)(dest), (long)(arg))
+#define BOOST_ATOMIC_INTERLOCKED_BTS_ACQUIRE(dest, arg) _interlockedbittestandset_acq((long*)(dest), (long)(arg))
+#define BOOST_ATOMIC_INTERLOCKED_BTS_RELEASE(dest, arg) _interlockedbittestandset_rel((long*)(dest), (long)(arg))
+
+#if defined(BOOST_MSVC)
+#pragma intrinsic(_interlockedbittestandreset_nf)
+#pragma intrinsic(_interlockedbittestandreset_acq)
+#pragma intrinsic(_interlockedbittestandreset_rel)
+#endif
+
+#define BOOST_ATOMIC_INTERLOCKED_BTR_RELAXED(dest, arg) _interlockedbittestandreset_nf((long*)(dest), (long)(arg))
+#define BOOST_ATOMIC_INTERLOCKED_BTR_ACQUIRE(dest, arg) _interlockedbittestandreset_acq((long*)(dest), (long)(arg))
+#define BOOST_ATOMIC_INTERLOCKED_BTR_RELEASE(dest, arg) _interlockedbittestandreset_rel((long*)(dest), (long)(arg))
+
 #endif // _MSC_VER >= 1700 && defined(_M_ARM)
 
 #endif // _MSC_VER < 1400

data/src/cxx_supportlib/vendor-modified/boost/atomic/detail/operations_lockfree.hpp

@@ -18,7 +18,7 @@
 #include <boost/atomic/detail/platform.hpp>
 
 #if !defined(BOOST_ATOMIC_EMULATED)
-#include BOOST_ATOMIC_DETAIL_HEADER(boost/atomic/detail/ops_)
+#include BOOST_ATOMIC_DETAIL_BACKEND_HEADER(boost/atomic/detail/ops_)
 #else
 #include <boost/atomic/detail/operations_fwd.hpp>
 #endif

data/src/cxx_supportlib/vendor-modified/boost/atomic/detail/ops_cas_based.hpp

@@ -47,6 +47,8 @@ struct cas_based_operations :
 {
     typedef typename Base::storage_type storage_type;
 
+    static BOOST_CONSTEXPR_OR_CONST bool full_cas_based = true;
+
     static BOOST_FORCEINLINE storage_type fetch_add(storage_type volatile& storage, storage_type v, memory_order order) BOOST_NOEXCEPT
     {
         storage_type old_val;

data/src/cxx_supportlib/vendor-modified/boost/atomic/detail/ops_emulated.hpp

@@ -30,10 +30,15 @@ namespace boost {
 namespace atomics {
 namespace detail {
 
-template< typename T >
+template< std::size_t Size, bool Signed >
 struct emulated_operations
 {
-    typedef T storage_type;
+    typedef typename make_storage_type< Size >::type storage_type;
+    typedef typename make_storage_type< Size >::aligned aligned_storage_type;
+
+    static BOOST_CONSTEXPR_OR_CONST std::size_t storage_size = Size;
+    static BOOST_CONSTEXPR_OR_CONST bool is_signed = Signed;
+    static BOOST_CONSTEXPR_OR_CONST bool full_cas_based = false;
 
     static BOOST_CONSTEXPR_OR_CONST bool is_always_lock_free = false;
 
@@ -142,18 +147,12 @@ struct emulated_operations
     {
         store(storage, (storage_type)0, order);
     }
-
-    static BOOST_FORCEINLINE bool is_lock_free(storage_type const volatile&) BOOST_NOEXCEPT
-    {
-        return false;
-    }
 };
 
 template< std::size_t Size, bool Signed >
 struct operations :
-    public emulated_operations< typename make_storage_type< Size, Signed >::type >
+    public emulated_operations< Size, Signed >
 {
-    typedef typename make_storage_type< Size, Signed >::aligned aligned_storage_type;
 };
 
 } // namespace detail

data/src/cxx_supportlib/vendor-modified/boost/atomic/detail/ops_extending_cas_based.hpp

@@ -18,6 +18,7 @@
 #include <boost/memory_order.hpp>
 #include <boost/atomic/detail/config.hpp>
 #include <boost/atomic/detail/storage_type.hpp>
+#include <boost/atomic/detail/integral_extend.hpp>
 
 #ifdef BOOST_HAS_PRAGMA_ONCE
 #pragma once
@@ -32,18 +33,18 @@ struct extending_cas_based_operations :
     public Base
 {
     typedef typename Base::storage_type storage_type;
-    typedef typename make_storage_type< Size, Signed >::type emulated_storage_type;
+    typedef typename make_storage_type< Size >::type emulated_storage_type;
 
     static BOOST_FORCEINLINE storage_type fetch_add(storage_type volatile& storage, storage_type v, memory_order order) BOOST_NOEXCEPT
     {
         storage_type old_val;
         atomics::detail::non_atomic_load(storage, old_val);
-        emulated_storage_type new_val;
+        storage_type new_val;
         do
         {
-            new_val = static_cast< emulated_storage_type >(old_val) + static_cast< emulated_storage_type >(v);
+            new_val = atomics::detail::integral_extend< Signed, storage_type >(static_cast< emulated_storage_type >(old_val + v));
         }
-        while (!Base::compare_exchange_weak(storage, old_val, static_cast< storage_type >(new_val), order, memory_order_relaxed));
+        while (!Base::compare_exchange_weak(storage, old_val, new_val, order, memory_order_relaxed));
         return old_val;
     }
 
@@ -51,12 +52,12 @@ struct extending_cas_based_operations :
     {
         storage_type old_val;
         atomics::detail::non_atomic_load(storage, old_val);
-        emulated_storage_type new_val;
+        storage_type new_val;
         do
         {
-            new_val = static_cast< emulated_storage_type >(old_val) - static_cast< emulated_storage_type >(v);
+            new_val = atomics::detail::integral_extend< Signed, storage_type >(static_cast< emulated_storage_type >(old_val - v));
         }
-        while (!Base::compare_exchange_weak(storage, old_val, static_cast< storage_type >(new_val), order, memory_order_relaxed));
+        while (!Base::compare_exchange_weak(storage, old_val, new_val, order, memory_order_relaxed));
         return old_val;
     }
 };

data/src/cxx_supportlib/vendor-modified/boost/atomic/detail/ops_gcc_alpha.hpp

@@ -16,6 +16,7 @@
 #ifndef BOOST_ATOMIC_DETAIL_OPS_GCC_ALPHA_HPP_INCLUDED_
 #define BOOST_ATOMIC_DETAIL_OPS_GCC_ALPHA_HPP_INCLUDED_
 
+#include <cstddef>
 #include <boost/memory_order.hpp>
 #include <boost/atomic/detail/config.hpp>
 #include <boost/atomic/detail/storage_type.hpp>
@@ -63,17 +64,18 @@ namespace detail {
 
 struct gcc_alpha_operations_base
 {
+    static BOOST_CONSTEXPR_OR_CONST bool full_cas_based = false;
     static BOOST_CONSTEXPR_OR_CONST bool is_always_lock_free = true;
 
     static BOOST_FORCEINLINE void fence_before(memory_order order) BOOST_NOEXCEPT
     {
-        if ((order & memory_order_release) != 0)
+        if ((static_cast< unsigned int >(order) & static_cast< unsigned int >(memory_order_release)) != 0u)
             __asm__ __volatile__ ("mb" ::: "memory");
     }
 
     static BOOST_FORCEINLINE void fence_after(memory_order order) BOOST_NOEXCEPT
     {
-        if ((order & (memory_order_consume | memory_order_acquire)) != 0)
+        if ((static_cast< unsigned int >(order) & (static_cast< unsigned int >(memory_order_consume) | static_cast< unsigned int >(memory_order_acquire))) != 0u)
             __asm__ __volatile__ ("mb" ::: "memory");
     }
 
@@ -89,8 +91,11 @@ template< bool Signed >
 struct operations< 4u, Signed > :
     public gcc_alpha_operations_base
 {
-    typedef typename make_storage_type< 4u, Signed >::type storage_type;
-    typedef typename make_storage_type< 4u, Signed >::aligned aligned_storage_type;
+    typedef typename make_storage_type< 4u >::type storage_type;
+    typedef typename make_storage_type< 4u >::aligned aligned_storage_type;
+
+    static BOOST_CONSTEXPR_OR_CONST std::size_t storage_size = 4u;
+    static BOOST_CONSTEXPR_OR_CONST bool is_signed = Signed;
 
     static BOOST_FORCEINLINE void store(storage_type volatile& storage, storage_type v, memory_order order) BOOST_NOEXCEPT
     {
@@ -339,11 +344,6 @@ struct operations< 4u, Signed > :
     {
         store(storage, 0, order);
     }
-
-    static BOOST_FORCEINLINE bool is_lock_free(storage_type const volatile&) BOOST_NOEXCEPT
-    {
-        return true;
-    }
 };
 
 
@@ -601,8 +601,11 @@ template< bool Signed >
 struct operations< 8u, Signed > :
     public gcc_alpha_operations_base
 {
-    typedef typename make_storage_type< 8u, Signed >::type storage_type;
-    typedef typename make_storage_type< 8u, Signed >::aligned aligned_storage_type;
+    typedef typename make_storage_type< 8u >::type storage_type;
+    typedef typename make_storage_type< 8u >::aligned aligned_storage_type;
+
+    static BOOST_CONSTEXPR_OR_CONST std::size_t storage_size = 8u;
+    static BOOST_CONSTEXPR_OR_CONST bool is_signed = Signed;
 
     static BOOST_FORCEINLINE void store(storage_type volatile& storage, storage_type v, memory_order order) BOOST_NOEXCEPT
     {
@@ -851,11 +854,6 @@ struct operations< 8u, Signed > :
     {
         store(storage, 0, order);
     }
-
-    static BOOST_FORCEINLINE bool is_lock_free(storage_type const volatile&) BOOST_NOEXCEPT
-    {
-        return true;
-    }
 };
 
 

data/src/cxx_supportlib/vendor-modified/boost/atomic/detail/ops_gcc_arm.hpp

@@ -16,12 +16,14 @@
 #ifndef BOOST_ATOMIC_DETAIL_OPS_GCC_ARM_HPP_INCLUDED_
 #define BOOST_ATOMIC_DETAIL_OPS_GCC_ARM_HPP_INCLUDED_
 
+#include <cstddef>
 #include <boost/cstdint.hpp>
 #include <boost/memory_order.hpp>
 #include <boost/atomic/detail/config.hpp>
 #include <boost/atomic/detail/storage_type.hpp>
+#include <boost/atomic/detail/integral_extend.hpp>
 #include <boost/atomic/detail/operations_fwd.hpp>
-#include <boost/atomic/detail/ops_extending_cas_based.hpp>
+#include <boost/atomic/detail/ops_gcc_arm_common.hpp>
 #include <boost/atomic/capabilities.hpp>
 
 #ifdef BOOST_HAS_PRAGMA_ONCE
@@ -53,112 +55,16 @@ namespace detail {
 // (Actually it looks like these are available from version 6k onwards.)
 // FIXME these are not yet used; should be mostly a matter of copy-and-paste.
 // I think you can supply an immediate offset to the address.
-//
-// A memory barrier is effected using a "co-processor 15" instruction,
-// though a separate assembler mnemonic is available for it in v7.
-//
-// "Thumb 1" is a subset of the ARM instruction set that uses a 16-bit encoding.  It
-// doesn't include all instructions and in particular it doesn't include the co-processor
-// instruction used for the memory barrier or the load-locked/store-conditional
-// instructions.  So, if we're compiling in "Thumb 1" mode, we need to wrap all of our
-// asm blocks with code to temporarily change to ARM mode.
-//
-// You can only change between ARM and Thumb modes when branching using the bx instruction.
-// bx takes an address specified in a register.  The least significant bit of the address
-// indicates the mode, so 1 is added to indicate that the destination code is Thumb.
-// A temporary register is needed for the address and is passed as an argument to these
-// macros.  It must be one of the "low" registers accessible to Thumb code, specified
-// using the "l" attribute in the asm statement.
-//
-// Architecture v7 introduces "Thumb 2", which does include (almost?) all of the ARM
-// instruction set.  (Actually, there was an extension of v6 called v6T2 which supported
-// "Thumb 2" mode, but its architecture manual is no longer available, referring to v7.)
-// So in v7 we don't need to change to ARM mode; we can write "universal
-// assembler" which will assemble to Thumb 2 or ARM code as appropriate.  The only thing
-// we need to do to make this "universal" assembler mode work is to insert "IT" instructions
-// to annotate the conditional instructions.  These are ignored in other modes (e.g. v6),
-// so they can always be present.
-
-// A note about memory_order_consume. Technically, this architecture allows to avoid
-// unnecessary memory barrier after consume load since it supports data dependency ordering.
-// However, some compiler optimizations may break a seemingly valid code relying on data
-// dependency tracking by injecting bogus branches to aid out of order execution.
-// This may happen not only in Boost.Atomic code but also in user's code, which we have no
-// control of. See this thread: http://lists.boost.org/Archives/boost/2014/06/213890.php.
-// For this reason we promote memory_order_consume to memory_order_acquire.
-
-#if defined(__thumb__) && !defined(__thumb2__)
-#define BOOST_ATOMIC_DETAIL_ARM_ASM_START(TMPREG) "adr " #TMPREG ", 8f\n" "bx " #TMPREG "\n" ".arm\n" ".align 4\n" "8:\n"
-#define BOOST_ATOMIC_DETAIL_ARM_ASM_END(TMPREG)   "adr " #TMPREG ", 9f + 1\n" "bx " #TMPREG "\n" ".thumb\n" ".align 2\n" "9:\n"
-#define BOOST_ATOMIC_DETAIL_ARM_ASM_TMPREG_CONSTRAINT(var) "=&l" (var)
-#else
-// The tmpreg may be wasted in this case, which is non-optimal.
-#define BOOST_ATOMIC_DETAIL_ARM_ASM_START(TMPREG)
-#define BOOST_ATOMIC_DETAIL_ARM_ASM_END(TMPREG)
-#define BOOST_ATOMIC_DETAIL_ARM_ASM_TMPREG_CONSTRAINT(var) "=&r" (var)
-#endif
-
-struct gcc_arm_operations_base
-{
-    static BOOST_CONSTEXPR_OR_CONST bool is_always_lock_free = true;
-
-    static BOOST_FORCEINLINE void fence_before(memory_order order) BOOST_NOEXCEPT
-    {
-        if ((order & memory_order_release) != 0)
-            hardware_full_fence();
-    }
-
-    static BOOST_FORCEINLINE void fence_after(memory_order order) BOOST_NOEXCEPT
-    {
-        if ((order & (memory_order_consume | memory_order_acquire)) != 0)
-            hardware_full_fence();
-    }
-
-    static BOOST_FORCEINLINE void fence_after_store(memory_order order) BOOST_NOEXCEPT
-    {
-        if (order == memory_order_seq_cst)
-            hardware_full_fence();
-    }
-
-    static BOOST_FORCEINLINE void hardware_full_fence() BOOST_NOEXCEPT
-    {
-#if defined(BOOST_ATOMIC_DETAIL_ARM_HAS_DMB)
-        // Older binutils (supposedly, older than 2.21.1) didn't support symbolic or numeric arguments of the "dmb" instruction such as "ish" or "#11".
-        // As a workaround we have to inject encoded bytes of the instruction. There are two encodings for the instruction: ARM and Thumb. See ARM Architecture Reference Manual, A8.8.43.
-        // Since we cannot detect binutils version at compile time, we'll have to always use this hack.
-        __asm__ __volatile__
-        (
-#if defined(__thumb2__)
-            ".short 0xF3BF, 0x8F5B\n" // dmb ish
-#else
-            ".word 0xF57FF05B\n" // dmb ish
-#endif
-            :
-            :
-            : "memory"
-        );
-#else
-        int tmp;
-        __asm__ __volatile__
-        (
-            BOOST_ATOMIC_DETAIL_ARM_ASM_START(%0)
-            "mcr\tp15, 0, r0, c7, c10, 5\n"
-            BOOST_ATOMIC_DETAIL_ARM_ASM_END(%0)
-            : "=&l" (tmp)
-            :
-            : "memory"
-        );
-#endif
-    }
-};
-
 
 template< bool Signed >
 struct operations< 4u, Signed > :
     public gcc_arm_operations_base
 {
-    typedef typename make_storage_type< 4u, Signed >::type storage_type;
-    typedef typename make_storage_type< 4u, Signed >::aligned aligned_storage_type;
+    typedef typename make_storage_type< 4u >::type storage_type;
+    typedef typename make_storage_type< 4u >::aligned aligned_storage_type;
+
+    static BOOST_CONSTEXPR_OR_CONST std::size_t storage_size = 4u;
+    static BOOST_CONSTEXPR_OR_CONST bool is_signed = Signed;
 
     static BOOST_FORCEINLINE void store(storage_type volatile& storage, storage_type v, memory_order order) BOOST_NOEXCEPT
     {
@@ -217,7 +123,7 @@ struct operations< 4u, Signed > :
               [success] "=&r" (success),    // %1
               [tmp] "=&l" (tmp),            // %2
               [storage] "+Q" (storage)      // %3
-            : [expected] "r" (expected),    // %4
+            : [expected] "Ir" (expected),   // %4
               [desired] "r" (desired)       // %5
             : BOOST_ATOMIC_DETAIL_ASM_CLOBBER_CC
         );
@@ -253,7 +159,7 @@ struct operations< 4u, Signed > :
               [success] "=&r" (success),    // %1
               [tmp] "=&l" (tmp),            // %2
               [storage] "+Q" (storage)      // %3
-            : [expected] "r" (expected),    // %4
+            : [expected] "Ir" (expected),   // %4
               [desired] "r" (desired)       // %5
             : BOOST_ATOMIC_DETAIL_ASM_CLOBBER_CC
         );
@@ -284,7 +190,7 @@ struct operations< 4u, Signed > :
               [result] "=&r" (result),      // %1
               [tmp] "=&l" (tmp),            // %2
               [storage] "+Q" (storage)      // %3
-            : [value] "r" (v)               // %4
+            : [value] "Ir" (v)              // %4
             : BOOST_ATOMIC_DETAIL_ASM_CLOBBER_CC
         );
         fence_after(order);
@@ -310,7 +216,7 @@ struct operations< 4u, Signed > :
               [result] "=&r" (result),      // %1
               [tmp] "=&l" (tmp),            // %2
               [storage] "+Q" (storage)      // %3
-            : [value] "r" (v)               // %4
+            : [value] "Ir" (v)              // %4
             : BOOST_ATOMIC_DETAIL_ASM_CLOBBER_CC
         );
         fence_after(order);
@@ -336,7 +242,7 @@ struct operations< 4u, Signed > :
               [result] "=&r" (result),      // %1
               [tmp] "=&l" (tmp),            // %2
               [storage] "+Q" (storage)      // %3
-            : [value] "r" (v)               // %4
+            : [value] "Ir" (v)              // %4
             : BOOST_ATOMIC_DETAIL_ASM_CLOBBER_CC
         );
         fence_after(order);
@@ -362,7 +268,7 @@ struct operations< 4u, Signed > :
               [result] "=&r" (result),      // %1
               [tmp] "=&l" (tmp),            // %2
               [storage] "+Q" (storage)      // %3
-            : [value] "r" (v)               // %4
+            : [value] "Ir" (v)              // %4
             : BOOST_ATOMIC_DETAIL_ASM_CLOBBER_CC
         );
         fence_after(order);
@@ -388,7 +294,7 @@ struct operations< 4u, Signed > :
               [result] "=&r" (result),      // %1
               [tmp] "=&l" (tmp),            // %2
               [storage] "+Q" (storage)      // %3
-            : [value] "r" (v)               // %4
+            : [value] "Ir" (v)              // %4
             : BOOST_ATOMIC_DETAIL_ASM_CLOBBER_CC
         );
         fence_after(order);
@@ -404,13 +310,268 @@ struct operations< 4u, Signed > :
     {
         store(storage, 0, order);
     }
+};
+
+#if defined(BOOST_ATOMIC_DETAIL_ARM_HAS_LDREXB_STREXB)
+
+template< bool Signed >
+struct operations< 1u, Signed > :
+    public gcc_arm_operations_base
+{
+    typedef typename make_storage_type< 1u >::type storage_type;
+    typedef typename make_storage_type< 1u >::aligned aligned_storage_type;
+    typedef typename make_storage_type< 4u >::type extended_storage_type;
+
+    static BOOST_CONSTEXPR_OR_CONST std::size_t storage_size = 1u;
+    static BOOST_CONSTEXPR_OR_CONST bool is_signed = Signed;
+
+    static BOOST_FORCEINLINE void store(storage_type volatile& storage, storage_type v, memory_order order) BOOST_NOEXCEPT
+    {
+        fence_before(order);
+        storage = v;
+        fence_after_store(order);
+    }
+
+    static BOOST_FORCEINLINE storage_type load(storage_type const volatile& storage, memory_order order) BOOST_NOEXCEPT
+    {
+        storage_type v = storage;
+        fence_after(order);
+        return v;
+    }
+
+    static BOOST_FORCEINLINE storage_type exchange(storage_type volatile& storage, storage_type v, memory_order order) BOOST_NOEXCEPT
+    {
+        extended_storage_type original;
+        fence_before(order);
+        uint32_t tmp;
+        __asm__ __volatile__
+        (
+            BOOST_ATOMIC_DETAIL_ARM_ASM_START(%[tmp])
+            "1:\n"
+            "ldrexb %[original], %[storage]\n"          // load the original value and zero-extend to 32 bits
+            "strexb %[tmp], %[value], %[storage]\n"     // store the replacement, tmp = store failed
+            "teq    %[tmp], #0\n"                       // check if store succeeded
+            "bne    1b\n"
+            BOOST_ATOMIC_DETAIL_ARM_ASM_END(%[tmp])
+            : [tmp] "=&l" (tmp), [original] "=&r" (original), [storage] "+Q" (storage)
+            : [value] "r" (v)
+            : BOOST_ATOMIC_DETAIL_ASM_CLOBBER_CC
+        );
+        fence_after(order);
+        return static_cast< storage_type >(original);
+    }
+
+    static BOOST_FORCEINLINE bool compare_exchange_weak(
+        storage_type volatile& storage, storage_type& expected, storage_type desired, memory_order success_order, memory_order failure_order) BOOST_NOEXCEPT
+    {
+        fence_before(success_order);
+        uint32_t success;
+        uint32_t tmp;
+        extended_storage_type original;
+        __asm__ __volatile__
+        (
+            BOOST_ATOMIC_DETAIL_ARM_ASM_START(%[tmp])
+            "mov      %[success], #0\n"                      // success = 0
+            "ldrexb   %[original], %[storage]\n"             // original = zero_extend(*(&storage))
+            "cmp      %[original], %[expected]\n"            // flags = original==expected
+            "itt      eq\n"                                  // [hint that the following 2 instructions are conditional on flags.equal]
+            "strexbeq %[success], %[desired], %[storage]\n"  // if (flags.equal) *(&storage) = desired, success = store failed
+            "eoreq    %[success], %[success], #1\n"          // if (flags.equal) success ^= 1 (i.e. make it 1 if store succeeded)
+            BOOST_ATOMIC_DETAIL_ARM_ASM_END(%[tmp])
+            : [original] "=&r" (original),  // %0
+              [success] "=&r" (success),    // %1
+              [tmp] "=&l" (tmp),            // %2
+              [storage] "+Q" (storage)      // %3
+            : [expected] "Ir" (atomics::detail::zero_extend< extended_storage_type >(expected)),   // %4
+              [desired] "r" (desired)       // %5
+            : BOOST_ATOMIC_DETAIL_ASM_CLOBBER_CC
+        );
+        if (success)
+            fence_after(success_order);
+        else
+            fence_after(failure_order);
+        expected = static_cast< storage_type >(original);
+        return !!success;
+    }
+
+    static BOOST_FORCEINLINE bool compare_exchange_strong(
+        storage_type volatile& storage, storage_type& expected, storage_type desired, memory_order success_order, memory_order failure_order) BOOST_NOEXCEPT
+    {
+        fence_before(success_order);
+        uint32_t success;
+        uint32_t tmp;
+        extended_storage_type original;
+        __asm__ __volatile__
+        (
+            BOOST_ATOMIC_DETAIL_ARM_ASM_START(%[tmp])
+            "mov      %[success], #0\n"                      // success = 0
+            "1:\n"
+            "ldrexb   %[original], %[storage]\n"             // original = zero_extend(*(&storage))
+            "cmp      %[original], %[expected]\n"            // flags = original==expected
+            "bne      2f\n"                                  // if (!flags.equal) goto end
+            "strexb   %[success], %[desired], %[storage]\n"  // *(&storage) = desired, success = store failed
+            "eors     %[success], %[success], #1\n"          // success ^= 1 (i.e. make it 1 if store succeeded); flags.equal = success == 0
+            "beq      1b\n"                                  // if (flags.equal) goto retry
+            "2:\n"
+            BOOST_ATOMIC_DETAIL_ARM_ASM_END(%[tmp])
+            : [original] "=&r" (original),  // %0
+              [success] "=&r" (success),    // %1
+              [tmp] "=&l" (tmp),            // %2
+              [storage] "+Q" (storage)      // %3
+            : [expected] "Ir" (atomics::detail::zero_extend< extended_storage_type >(expected)),   // %4
+              [desired] "r" (desired)       // %5
+            : BOOST_ATOMIC_DETAIL_ASM_CLOBBER_CC
+        );
+        if (success)
+            fence_after(success_order);
+        else
+            fence_after(failure_order);
+        expected = static_cast< storage_type >(original);
+        return !!success;
+    }
+
+    static BOOST_FORCEINLINE storage_type fetch_add(storage_type volatile& storage, storage_type v, memory_order order) BOOST_NOEXCEPT
+    {
+        fence_before(order);
+        uint32_t tmp;
+        extended_storage_type original, result;
+        __asm__ __volatile__
+        (
+            BOOST_ATOMIC_DETAIL_ARM_ASM_START(%[tmp])
+            "1:\n"
+            "ldrexb   %[original], %[storage]\n"           // original = zero_extend(*(&storage))
+            "add      %[result], %[original], %[value]\n"  // result = original + value
+            "strexb   %[tmp], %[result], %[storage]\n"     // *(&storage) = result, tmp = store failed
+            "teq      %[tmp], #0\n"                        // flags = tmp==0
+            "bne      1b\n"                                // if (!flags.equal) goto retry
+            BOOST_ATOMIC_DETAIL_ARM_ASM_END(%[tmp])
+            : [original] "=&r" (original),  // %0
+              [result] "=&r" (result),      // %1
+              [tmp] "=&l" (tmp),            // %2
+              [storage] "+Q" (storage)      // %3
+            : [value] "Ir" (v)              // %4
+            : BOOST_ATOMIC_DETAIL_ASM_CLOBBER_CC
+        );
+        fence_after(order);
+        return static_cast< storage_type >(original);
+    }
+
+    static BOOST_FORCEINLINE storage_type fetch_sub(storage_type volatile& storage, storage_type v, memory_order order) BOOST_NOEXCEPT
+    {
+        fence_before(order);
+        uint32_t tmp;
+        extended_storage_type original, result;
+        __asm__ __volatile__
+        (
+            BOOST_ATOMIC_DETAIL_ARM_ASM_START(%[tmp])
+            "1:\n"
+            "ldrexb   %[original], %[storage]\n"           // original = zero_extend(*(&storage))
+            "sub      %[result], %[original], %[value]\n"  // result = original - value
+            "strexb   %[tmp], %[result], %[storage]\n"     // *(&storage) = result, tmp = store failed
+            "teq      %[tmp], #0\n"                        // flags = tmp==0
+            "bne      1b\n"                                // if (!flags.equal) goto retry
+            BOOST_ATOMIC_DETAIL_ARM_ASM_END(%[tmp])
+            : [original] "=&r" (original),  // %0
+              [result] "=&r" (result),      // %1
+              [tmp] "=&l" (tmp),            // %2
+              [storage] "+Q" (storage)      // %3
+            : [value] "Ir" (v)              // %4
+            : BOOST_ATOMIC_DETAIL_ASM_CLOBBER_CC
+        );
+        fence_after(order);
+        return static_cast< storage_type >(original);
+    }
+
+    static BOOST_FORCEINLINE storage_type fetch_and(storage_type volatile& storage, storage_type v, memory_order order) BOOST_NOEXCEPT
+    {
+        fence_before(order);
+        uint32_t tmp;
+        extended_storage_type original, result;
+        __asm__ __volatile__
+        (
+            BOOST_ATOMIC_DETAIL_ARM_ASM_START(%[tmp])
+            "1:\n"
+            "ldrexb   %[original], %[storage]\n"           // original = zero_extend(*(&storage))
+            "and      %[result], %[original], %[value]\n"  // result = original & value
+            "strexb   %[tmp], %[result], %[storage]\n"     // *(&storage) = result, tmp = store failed
+            "teq      %[tmp], #0\n"                        // flags = tmp==0
+            "bne      1b\n"                                // if (!flags.equal) goto retry
+            BOOST_ATOMIC_DETAIL_ARM_ASM_END(%[tmp])
+            : [original] "=&r" (original),  // %0
+              [result] "=&r" (result),      // %1
+              [tmp] "=&l" (tmp),            // %2
+              [storage] "+Q" (storage)      // %3
+            : [value] "Ir" (v)              // %4
+            : BOOST_ATOMIC_DETAIL_ASM_CLOBBER_CC
+        );
+        fence_after(order);
+        return static_cast< storage_type >(original);
+    }
+
+    static BOOST_FORCEINLINE storage_type fetch_or(storage_type volatile& storage, storage_type v, memory_order order) BOOST_NOEXCEPT
+    {
+        fence_before(order);
+        uint32_t tmp;
+        extended_storage_type original, result;
+        __asm__ __volatile__
+        (
+            BOOST_ATOMIC_DETAIL_ARM_ASM_START(%[tmp])
+            "1:\n"
+            "ldrexb   %[original], %[storage]\n"           // original = zero_extend(*(&storage))
+            "orr      %[result], %[original], %[value]\n"  // result = original | value
+            "strexb   %[tmp], %[result], %[storage]\n"     // *(&storage) = result, tmp = store failed
+            "teq      %[tmp], #0\n"                        // flags = tmp==0
+            "bne      1b\n"                                // if (!flags.equal) goto retry
+            BOOST_ATOMIC_DETAIL_ARM_ASM_END(%[tmp])
+            : [original] "=&r" (original),  // %0
+              [result] "=&r" (result),      // %1
+              [tmp] "=&l" (tmp),            // %2
+              [storage] "+Q" (storage)      // %3
+            : [value] "Ir" (v)              // %4
+            : BOOST_ATOMIC_DETAIL_ASM_CLOBBER_CC
+        );
+        fence_after(order);
+        return static_cast< storage_type >(original);
+    }
+
+    static BOOST_FORCEINLINE storage_type fetch_xor(storage_type volatile& storage, storage_type v, memory_order order) BOOST_NOEXCEPT
+    {
+        fence_before(order);
+        uint32_t tmp;
+        extended_storage_type original, result;
+        __asm__ __volatile__
+        (
+            BOOST_ATOMIC_DETAIL_ARM_ASM_START(%[tmp])
+            "1:\n"
+            "ldrexb   %[original], %[storage]\n"           // original = zero_extend(*(&storage))
+            "eor      %[result], %[original], %[value]\n"  // result = original ^ value
+            "strexb   %[tmp], %[result], %[storage]\n"     // *(&storage) = result, tmp = store failed
+            "teq      %[tmp], #0\n"                        // flags = tmp==0
+            "bne      1b\n"                                // if (!flags.equal) goto retry
+            BOOST_ATOMIC_DETAIL_ARM_ASM_END(%[tmp])
+            : [original] "=&r" (original),  // %0
+              [result] "=&r" (result),      // %1
+              [tmp] "=&l" (tmp),            // %2
+              [storage] "+Q" (storage)      // %3
+            : [value] "Ir" (v)              // %4
+            : BOOST_ATOMIC_DETAIL_ASM_CLOBBER_CC
+        );
+        fence_after(order);
+        return static_cast< storage_type >(original);
+    }
 
-    static BOOST_FORCEINLINE bool is_lock_free(storage_type const volatile&) BOOST_NOEXCEPT
+    static BOOST_FORCEINLINE bool test_and_set(storage_type volatile& storage, memory_order order) BOOST_NOEXCEPT
     {
-        return true;
+        return !!exchange(storage, (storage_type)1, order);
+    }
+
+    static BOOST_FORCEINLINE void clear(storage_type volatile& storage, memory_order order) BOOST_NOEXCEPT
+    {
+        store(storage, 0, order);
     }
 };
 
+#else // defined(BOOST_ATOMIC_DETAIL_ARM_HAS_LDREXB_STREXB)
 
 template< >
 struct operations< 1u, false > :
@@ -439,7 +600,7 @@ struct operations< 1u, false > :
               [result] "=&r" (result),      // %1
               [tmp] "=&l" (tmp),            // %2
               [storage] "+Q" (storage)      // %3
-            : [value] "r" (v)               // %4
+            : [value] "Ir" (v)              // %4
             : BOOST_ATOMIC_DETAIL_ASM_CLOBBER_CC
         );
         fence_after(order);
@@ -466,7 +627,7 @@ struct operations< 1u, false > :
               [result] "=&r" (result),      // %1
               [tmp] "=&l" (tmp),            // %2
               [storage] "+Q" (storage)      // %3
-            : [value] "r" (v)               // %4
+            : [value] "Ir" (v)              // %4
             : BOOST_ATOMIC_DETAIL_ASM_CLOBBER_CC
         );
         fence_after(order);
@@ -501,7 +662,7 @@ struct operations< 1u, true > :
               [result] "=&r" (result),      // %1
               [tmp] "=&l" (tmp),            // %2
               [storage] "+Q" (storage)      // %3
-            : [value] "r" (v)               // %4
+            : [value] "Ir" (v)              // %4
             : BOOST_ATOMIC_DETAIL_ASM_CLOBBER_CC
         );
         fence_after(order);
@@ -528,7 +689,7 @@ struct operations< 1u, true > :
               [result] "=&r" (result),      // %1
               [tmp] "=&l" (tmp),            // %2
               [storage] "+Q" (storage)      // %3
-            : [value] "r" (v)               // %4
+            : [value] "Ir" (v)              // %4
             : BOOST_ATOMIC_DETAIL_ASM_CLOBBER_CC
         );
         fence_after(order);
@@ -536,6 +697,268 @@ struct operations< 1u, true > :
     }
 };
 
+#endif // defined(BOOST_ATOMIC_DETAIL_ARM_HAS_LDREXB_STREXB)
+
+#if defined(BOOST_ATOMIC_DETAIL_ARM_HAS_LDREXH_STREXH)
+
+template< bool Signed >
+struct operations< 2u, Signed > :
+    public gcc_arm_operations_base
+{
+    typedef typename make_storage_type< 2u >::type storage_type;
+    typedef typename make_storage_type< 2u >::aligned aligned_storage_type;
+    typedef typename make_storage_type< 4u >::type extended_storage_type;
+
+    static BOOST_CONSTEXPR_OR_CONST std::size_t storage_size = 2u;
+    static BOOST_CONSTEXPR_OR_CONST bool is_signed = Signed;
+
+    static BOOST_FORCEINLINE void store(storage_type volatile& storage, storage_type v, memory_order order) BOOST_NOEXCEPT
+    {
+        fence_before(order);
+        storage = v;
+        fence_after_store(order);
+    }
+
+    static BOOST_FORCEINLINE storage_type load(storage_type const volatile& storage, memory_order order) BOOST_NOEXCEPT
+    {
+        storage_type v = storage;
+        fence_after(order);
+        return v;
+    }
+
+    static BOOST_FORCEINLINE storage_type exchange(storage_type volatile& storage, storage_type v, memory_order order) BOOST_NOEXCEPT
+    {
+        extended_storage_type original;
+        fence_before(order);
+        uint32_t tmp;
+        __asm__ __volatile__
+        (
+            BOOST_ATOMIC_DETAIL_ARM_ASM_START(%[tmp])
+            "1:\n"
+            "ldrexh %[original], %[storage]\n"          // load the original value and zero-extend to 32 bits
+            "strexh %[tmp], %[value], %[storage]\n"     // store the replacement, tmp = store failed
+            "teq    %[tmp], #0\n"                       // check if store succeeded
+            "bne    1b\n"
+            BOOST_ATOMIC_DETAIL_ARM_ASM_END(%[tmp])
+            : [tmp] "=&l" (tmp), [original] "=&r" (original), [storage] "+Q" (storage)
+            : [value] "r" (v)
+            : BOOST_ATOMIC_DETAIL_ASM_CLOBBER_CC
+        );
+        fence_after(order);
+        return static_cast< storage_type >(original);
+    }
+
+    static BOOST_FORCEINLINE bool compare_exchange_weak(
+        storage_type volatile& storage, storage_type& expected, storage_type desired, memory_order success_order, memory_order failure_order) BOOST_NOEXCEPT
+    {
+        fence_before(success_order);
+        uint32_t success;
+        uint32_t tmp;
+        extended_storage_type original;
+        __asm__ __volatile__
+        (
+            BOOST_ATOMIC_DETAIL_ARM_ASM_START(%[tmp])
+            "mov      %[success], #0\n"                      // success = 0
+            "ldrexh   %[original], %[storage]\n"             // original = zero_extend(*(&storage))
+            "cmp      %[original], %[expected]\n"            // flags = original==expected
+            "itt      eq\n"                                  // [hint that the following 2 instructions are conditional on flags.equal]
+            "strexheq %[success], %[desired], %[storage]\n"  // if (flags.equal) *(&storage) = desired, success = store failed
+            "eoreq    %[success], %[success], #1\n"          // if (flags.equal) success ^= 1 (i.e. make it 1 if store succeeded)
+            BOOST_ATOMIC_DETAIL_ARM_ASM_END(%[tmp])
+            : [original] "=&r" (original),  // %0
+              [success] "=&r" (success),    // %1
+              [tmp] "=&l" (tmp),            // %2
+              [storage] "+Q" (storage)      // %3
+            : [expected] "Ir" (atomics::detail::zero_extend< extended_storage_type >(expected)),   // %4
+              [desired] "r" (desired)       // %5
+            : BOOST_ATOMIC_DETAIL_ASM_CLOBBER_CC
+        );
+        if (success)
+            fence_after(success_order);
+        else
+            fence_after(failure_order);
+        expected = static_cast< storage_type >(original);
+        return !!success;
+    }
+
+    static BOOST_FORCEINLINE bool compare_exchange_strong(
+        storage_type volatile& storage, storage_type& expected, storage_type desired, memory_order success_order, memory_order failure_order) BOOST_NOEXCEPT
+    {
+        fence_before(success_order);
+        uint32_t success;
+        uint32_t tmp;
+        extended_storage_type original;
+        __asm__ __volatile__
+        (
+            BOOST_ATOMIC_DETAIL_ARM_ASM_START(%[tmp])
+            "mov      %[success], #0\n"                      // success = 0
+            "1:\n"
+            "ldrexh   %[original], %[storage]\n"             // original = zero_extend(*(&storage))
+            "cmp      %[original], %[expected]\n"            // flags = original==expected
+            "bne      2f\n"                                  // if (!flags.equal) goto end
+            "strexh   %[success], %[desired], %[storage]\n"  // *(&storage) = desired, success = store failed
+            "eors     %[success], %[success], #1\n"          // success ^= 1 (i.e. make it 1 if store succeeded); flags.equal = success == 0
+            "beq      1b\n"                                  // if (flags.equal) goto retry
+            "2:\n"
+            BOOST_ATOMIC_DETAIL_ARM_ASM_END(%[tmp])
+            : [original] "=&r" (original),  // %0
+              [success] "=&r" (success),    // %1
+              [tmp] "=&l" (tmp),            // %2
+              [storage] "+Q" (storage)      // %3
+            : [expected] "Ir" (atomics::detail::zero_extend< extended_storage_type >(expected)),   // %4
+              [desired] "r" (desired)       // %5
+            : BOOST_ATOMIC_DETAIL_ASM_CLOBBER_CC
+        );
+        if (success)
+            fence_after(success_order);
+        else
+            fence_after(failure_order);
+        expected = static_cast< storage_type >(original);
+        return !!success;
+    }
+
+    static BOOST_FORCEINLINE storage_type fetch_add(storage_type volatile& storage, storage_type v, memory_order order) BOOST_NOEXCEPT
+    {
+        fence_before(order);
+        uint32_t tmp;
+        extended_storage_type original, result;
+        __asm__ __volatile__
+        (
+            BOOST_ATOMIC_DETAIL_ARM_ASM_START(%[tmp])
+            "1:\n"
+            "ldrexh   %[original], %[storage]\n"           // original = zero_extend(*(&storage))
+            "add      %[result], %[original], %[value]\n"  // result = original + value
+            "strexh   %[tmp], %[result], %[storage]\n"     // *(&storage) = result, tmp = store failed
+            "teq      %[tmp], #0\n"                        // flags = tmp==0
+            "bne      1b\n"                                // if (!flags.equal) goto retry
+            BOOST_ATOMIC_DETAIL_ARM_ASM_END(%[tmp])
+            : [original] "=&r" (original),  // %0
+              [result] "=&r" (result),      // %1
+              [tmp] "=&l" (tmp),            // %2
+              [storage] "+Q" (storage)      // %3
+            : [value] "Ir" (v)              // %4
+            : BOOST_ATOMIC_DETAIL_ASM_CLOBBER_CC
+        );
+        fence_after(order);
+        return static_cast< storage_type >(original);
+    }
+
+    static BOOST_FORCEINLINE storage_type fetch_sub(storage_type volatile& storage, storage_type v, memory_order order) BOOST_NOEXCEPT
+    {
+        fence_before(order);
+        uint32_t tmp;
+        extended_storage_type original, result;
+        __asm__ __volatile__
+        (
+            BOOST_ATOMIC_DETAIL_ARM_ASM_START(%[tmp])
+            "1:\n"
+            "ldrexh   %[original], %[storage]\n"           // original = zero_extend(*(&storage))
+            "sub      %[result], %[original], %[value]\n"  // result = original - value
+            "strexh   %[tmp], %[result], %[storage]\n"     // *(&storage) = result, tmp = store failed
+            "teq      %[tmp], #0\n"                        // flags = tmp==0
+            "bne      1b\n"                                // if (!flags.equal) goto retry
+            BOOST_ATOMIC_DETAIL_ARM_ASM_END(%[tmp])
+            : [original] "=&r" (original),  // %0
+              [result] "=&r" (result),      // %1
+              [tmp] "=&l" (tmp),            // %2
+              [storage] "+Q" (storage)      // %3
+            : [value] "Ir" (v)              // %4
+            : BOOST_ATOMIC_DETAIL_ASM_CLOBBER_CC
+        );
+        fence_after(order);
+        return static_cast< storage_type >(original);
+    }
+
+    static BOOST_FORCEINLINE storage_type fetch_and(storage_type volatile& storage, storage_type v, memory_order order) BOOST_NOEXCEPT
+    {
+        fence_before(order);
+        uint32_t tmp;
+        extended_storage_type original, result;
+        __asm__ __volatile__
+        (
+            BOOST_ATOMIC_DETAIL_ARM_ASM_START(%[tmp])
+            "1:\n"
+            "ldrexh   %[original], %[storage]\n"           // original = zero_extend(*(&storage))
+            "and      %[result], %[original], %[value]\n"  // result = original & value
+            "strexh   %[tmp], %[result], %[storage]\n"     // *(&storage) = result, tmp = store failed
+            "teq      %[tmp], #0\n"                        // flags = tmp==0
+            "bne      1b\n"                                // if (!flags.equal) goto retry
+            BOOST_ATOMIC_DETAIL_ARM_ASM_END(%[tmp])
+            : [original] "=&r" (original),  // %0
+              [result] "=&r" (result),      // %1
+              [tmp] "=&l" (tmp),            // %2
+              [storage] "+Q" (storage)      // %3
+            : [value] "Ir" (v)              // %4
+            : BOOST_ATOMIC_DETAIL_ASM_CLOBBER_CC
+        );
+        fence_after(order);
+        return static_cast< storage_type >(original);
+    }
+
+    static BOOST_FORCEINLINE storage_type fetch_or(storage_type volatile& storage, storage_type v, memory_order order) BOOST_NOEXCEPT
+    {
+        fence_before(order);
+        uint32_t tmp;
+        extended_storage_type original, result;
+        __asm__ __volatile__
+        (
+            BOOST_ATOMIC_DETAIL_ARM_ASM_START(%[tmp])
+            "1:\n"
+            "ldrexh   %[original], %[storage]\n"           // original = zero_extend(*(&storage))
+            "orr      %[result], %[original], %[value]\n"  // result = original | value
+            "strexh   %[tmp], %[result], %[storage]\n"     // *(&storage) = result, tmp = store failed
+            "teq      %[tmp], #0\n"                        // flags = tmp==0
+            "bne      1b\n"                                // if (!flags.equal) goto retry
+            BOOST_ATOMIC_DETAIL_ARM_ASM_END(%[tmp])
+            : [original] "=&r" (original),  // %0
+              [result] "=&r" (result),      // %1
+              [tmp] "=&l" (tmp),            // %2
+              [storage] "+Q" (storage)      // %3
+            : [value] "Ir" (v)              // %4
+            : BOOST_ATOMIC_DETAIL_ASM_CLOBBER_CC
+        );
+        fence_after(order);
+        return static_cast< storage_type >(original);
+    }
+
+    static BOOST_FORCEINLINE storage_type fetch_xor(storage_type volatile& storage, storage_type v, memory_order order) BOOST_NOEXCEPT
+    {
+        fence_before(order);
+        uint32_t tmp;
+        extended_storage_type original, result;
+        __asm__ __volatile__
+        (
+            BOOST_ATOMIC_DETAIL_ARM_ASM_START(%[tmp])
+            "1:\n"
+            "ldrexh   %[original], %[storage]\n"           // original = zero_extend(*(&storage))
+            "eor      %[result], %[original], %[value]\n"  // result = original ^ value
+            "strexh   %[tmp], %[result], %[storage]\n"     // *(&storage) = result, tmp = store failed
+            "teq      %[tmp], #0\n"                        // flags = tmp==0
+            "bne      1b\n"                                // if (!flags.equal) goto retry
+            BOOST_ATOMIC_DETAIL_ARM_ASM_END(%[tmp])
+            : [original] "=&r" (original),  // %0
+              [result] "=&r" (result),      // %1
+              [tmp] "=&l" (tmp),            // %2
+              [storage] "+Q" (storage)      // %3
+            : [value] "Ir" (v)              // %4
+            : BOOST_ATOMIC_DETAIL_ASM_CLOBBER_CC
+        );
+        fence_after(order);
+        return static_cast< storage_type >(original);
+    }
+
+    static BOOST_FORCEINLINE bool test_and_set(storage_type volatile& storage, memory_order order) BOOST_NOEXCEPT
+    {
+        return !!exchange(storage, (storage_type)1, order);
+    }
+
+    static BOOST_FORCEINLINE void clear(storage_type volatile& storage, memory_order order) BOOST_NOEXCEPT
+    {
+        store(storage, 0, order);
+    }
+};
+
+#else // defined(BOOST_ATOMIC_DETAIL_ARM_HAS_LDREXH_STREXH)
 
 template< >
 struct operations< 2u, false > :
@@ -564,7 +987,7 @@ struct operations< 2u, false > :
               [result] "=&r" (result),      // %1
               [tmp] "=&l" (tmp),            // %2
               [storage] "+Q" (storage)      // %3
-            : [value] "r" (v)               // %4
+            : [value] "Ir" (v)              // %4
             : BOOST_ATOMIC_DETAIL_ASM_CLOBBER_CC
         );
         fence_after(order);
@@ -591,7 +1014,7 @@ struct operations< 2u, false > :
               [result] "=&r" (result),      // %1
               [tmp] "=&l" (tmp),            // %2
               [storage] "+Q" (storage)      // %3
-            : [value] "r" (v)               // %4
+            : [value] "Ir" (v)              // %4
             : BOOST_ATOMIC_DETAIL_ASM_CLOBBER_CC
         );
         fence_after(order);
@@ -626,7 +1049,7 @@ struct operations< 2u, true > :
               [result] "=&r" (result),      // %1
               [tmp] "=&l" (tmp),            // %2
               [storage] "+Q" (storage)      // %3
-            : [value] "r" (v)               // %4
+            : [value] "Ir" (v)              // %4
             : BOOST_ATOMIC_DETAIL_ASM_CLOBBER_CC
         );
         fence_after(order);
@@ -653,7 +1076,7 @@ struct operations< 2u, true > :
               [result] "=&r" (result),      // %1
               [tmp] "=&l" (tmp),            // %2
               [storage] "+Q" (storage)      // %3
-            : [value] "r" (v)               // %4
+            : [value] "Ir" (v)              // %4
             : BOOST_ATOMIC_DETAIL_ASM_CLOBBER_CC
         );
         fence_after(order);
@@ -661,6 +1084,7 @@ struct operations< 2u, true > :
     }
 };
 
+#endif // defined(BOOST_ATOMIC_DETAIL_ARM_HAS_LDREXH_STREXH)
 
 #if defined(BOOST_ATOMIC_DETAIL_ARM_HAS_LDREXD_STREXD)
 
@@ -679,8 +1103,11 @@ template< bool Signed >
 struct operations< 8u, Signed > :
     public gcc_arm_operations_base
 {
-    typedef typename make_storage_type< 8u, Signed >::type storage_type;
-    typedef typename make_storage_type< 8u, Signed >::aligned aligned_storage_type;
+    typedef typename make_storage_type< 8u >::type storage_type;
+    typedef typename make_storage_type< 8u >::aligned aligned_storage_type;
+
+    static BOOST_CONSTEXPR_OR_CONST std::size_t storage_size = 8u;
+    static BOOST_CONSTEXPR_OR_CONST bool is_signed = Signed;
 
     static BOOST_FORCEINLINE void store(storage_type volatile& storage, storage_type v, memory_order order) BOOST_NOEXCEPT
     {
@@ -946,11 +1373,6 @@ struct operations< 8u, Signed > :
     {
         store(storage, 0, order);
     }
-
-    static BOOST_FORCEINLINE bool is_lock_free(storage_type const volatile&) BOOST_NOEXCEPT
-    {
-        return true;
-    }
 };
 
 #endif // defined(BOOST_ATOMIC_DETAIL_ARM_HAS_LDREXD_STREXD)