ipxact-ruby 0.11.1

data/spec/test_data/spiritconsortium.org/Leon2TLM/uart_scml/1.0/tlmsrc/inc/uart_fifo.h

@@ -0,0 +1,113 @@
+// 
+// Revision:    $Revision: 1506 $
+// Date:        $Date: 2009-04-26 01:51:56 -0500 (Sun, 26 Apr 2009) $
+// 
+// Copyright (c) 2005, 2006, 2007, 2008, 2009 The SPIRIT Consortium.
+// 
+// This work forms part of a deliverable of The SPIRIT Consortium.
+// 
+// Use of these materials are governed by the legal terms and conditions
+// outlined in the disclaimer available from www.spiritconsortium.org.
+// 
+// This source file is provided on an AS IS basis.  The SPIRIT
+// Consortium disclaims any warranty express or implied including
+// any warranty of merchantability and fitness for use for a
+// particular purpose.
+// 
+// The user of the source file shall indemnify and hold The SPIRIT
+// Consortium and its members harmless from any damages or liability.
+// Users are requested to provide feedback to The SPIRIT Consortium
+// using either mailto:feedback@lists.spiritconsortium.org or the forms at 
+// http://www.spiritconsortium.org/about/contact_us/
+// 
+// This file may be copied, and distributed, with or without
+// modifications; but this notice must be included on any copy.
+
+
+// uart_fifo.h
+
+#ifndef H_UART_FIFO
+#define H_UART_FIFO
+
+//***************************
+//*		Includes			*
+//***************************
+#include "systemc.h"	// For 'sc_module'
+
+//***********************************
+//*		UART FIFO Module Class		*
+//***********************************
+template <class DT>		// Template for the Data Type of the fifo
+class UART_FIFO : public sc_module {
+	public:
+		//**** Constructor ****//
+		UART_FIFO<DT>(sc_module_name N, int pSize) :  sc_module(N) {
+			fifo = new std::queue<DT>;		// Create a new queue object
+			Size = pSize;
+			TriggerLevel = 1;
+			CurrentLevel = 0;
+		};
+		//**** Destructor ****//
+		~UART_FIFO() { delete fifo;	};
+		
+		// Function for writing data to the fifo
+		void write(DT WriteData) {
+			if (CurrentLevel < Size) {
+				cout << sc_time_stamp() << ": " << name() << ": Writing to FIFO: " << WriteData;
+				fifo->push(WriteData);
+				CurrentLevel++;
+				cout << " (New FIFO Level = " << CurrentLevel << ")" << endl;
+			}
+		};
+		// Function for reading data from the fifo
+		DT read() {
+			if (CurrentLevel > 0) {
+				DT ReturnData;
+				ReturnData = fifo->front();
+				fifo->pop();
+				CurrentLevel--;
+				cout << sc_time_stamp() << ": " << name() << ": Reading from FIFO: " << ReturnData << " (New FIFO Level = " << CurrentLevel << ")" << endl;
+				return ReturnData;
+			}
+			return 0;
+		};
+		// Function for setting a new trigger level
+		void SetTriggerLevel(int level) {
+			if (level == 0)
+				TriggerLevel = 1;		// Minimum Trigger level = 1
+			if (level > Size-2)
+				TriggerLevel = Size-2;	// Maximum Trigger level = Size - 2
+			else
+				TriggerLevel = level;
+			cout << sc_time_stamp() << ": " << name() << ": Trigger Level set to: " << TriggerLevel << endl;
+		};
+		// Function that returns 1 if FIFO is empty
+		bool IsEmpty() {
+			return (CurrentLevel == 0);
+		};
+		// Function that returns 1 if FIFO is full
+		bool IsFull() {
+			return (CurrentLevel == Size);
+		};
+		// Function that returns 1 if FIFO is above (or at) the trigger level
+		bool IsAboveTriggerLevel() {
+			if (CurrentLevel >= TriggerLevel)
+				return true;
+			else
+				return false;
+		};
+		// Function that returns 1 if FIFO is below the trigger level
+		bool IsBelowTriggerLevel() {
+			if (CurrentLevel < TriggerLevel)
+				return true;
+			else
+				return false;
+		};
+	private:
+		int Size;				// The size of the FIFO
+		int TriggerLevel;		// Trigger Level of the FIFO
+		int CurrentLevel;		// This variable indicates how many elements are currently in the FIFO
+		std::queue<DT> * fifo;	// Pointer to the FIFO queue
+};
+
+#endif //H_UART_FIFO

data/spec/test_data/spiritconsortium.org/Leon2TLM/uart_scml/1.0/tlmsrc/inc/uart_memory_map.h

@@ -0,0 +1,96 @@
+// 
+// Revision:    $Revision: 1506 $
+// Date:        $Date: 2009-04-26 01:51:56 -0500 (Sun, 26 Apr 2009) $
+// 
+// Copyright (c) 2005, 2006, 2007, 2008, 2009 The SPIRIT Consortium.
+// 
+// This work forms part of a deliverable of The SPIRIT Consortium.
+// 
+// Use of these materials are governed by the legal terms and conditions
+// outlined in the disclaimer available from www.spiritconsortium.org.
+// 
+// This source file is provided on an AS IS basis.  The SPIRIT
+// Consortium disclaims any warranty express or implied including
+// any warranty of merchantability and fitness for use for a
+// particular purpose.
+// 
+// The user of the source file shall indemnify and hold The SPIRIT
+// Consortium and its members harmless from any damages or liability.
+// Users are requested to provide feedback to The SPIRIT Consortium
+// using either mailto:feedback@lists.spiritconsortium.org or the forms at 
+// http://www.spiritconsortium.org/about/contact_us/
+// 
+// This file may be copied, and distributed, with or without
+// modifications; but this notice must be included on any copy.
+
+
+#ifndef H_UART_MEMORY_MAP
+#define H_UART_MEMORY_MAP
+
+// Register Address Map:
+#define UART_MEM_SIZE	6					          // Size of the UART address space
+#define UART_REG_WIDTH	sizeof(DATA_TYPE)	// Byte width of the registers
+
+// Index of UART registers
+#define UART_REG_RBR	0	// Receiver Buffer Register
+#define UART_REG_THR	0	// Transmitter Holding Register
+#define UART_REG_IER	1	// Interrupt Enable (Mask) Register
+#define UART_REG_IIR	2	// Interrupt Identification Register
+#define UART_REG_FCR	2	// FIFO Control Register
+#define UART_REG_LCR	3	// Line Control Register
+#define UART_REG_LSR	5	// Line Status Register
+
+// Individual Bit positions within registers
+#define UART_BIT_FCR_FIFOE	0	// Position of FIFO Enable bit in FCR register	
+
+#define UART_BIT_LSR_THRE	5	// Position of THR Empty bit in LSR register
+#define UART_BIT_LSR_BI		4	// Position of Break Indicator bit in LSR register
+#define UART_BIT_LSR_FE		3	// Position of Frame Error bit in LSR register
+#define UART_BIT_LSR_PE		2	// Position of Parity Error bit in LSR register
+#define UART_BIT_LSR_OE		1	// Position of Overflow Error bit in LSR register
+#define UART_BIT_LSR_DR		0	// Position of Data Ready bit in LSR register
+
+#define UART_BIT_IER_ELSI	2	// Position of Enable Line Status Interrupt bit in IER register
+#define UART_BIT_IER_ETBEI	1	// Position of Enable Transmit Buffer Empty Interrupt bit in IER register
+#define UART_BIT_IER_ERBFI	0	// Position of Enable Receive Buffer Full Interrupt bit in IER register
+
+#define UART_BIT_LCR_SB		6	// Position of Set Break bit in LCR register
+#define UART_BIT_LCR_SP		5	// Position of Stick Parity bit in LCR register
+#define UART_BIT_LCR_EPS	4	// Position of Even Parity Select bit in LCR register
+#define UART_BIT_LCR_PEN	3	// Position of Parity Enable bit in LCR register
+#define UART_BIT_LCR_STB	2 	// Position of Number of Stop Bits bit in LCR register
+#define UART_BIT_LCR_WLS1	1	// Position of Word Length Select bit 1 in LCR register
+#define UART_BIT_LCR_WLS0	0	// Position of Word Length Select bit 0 in LCR register
+
+// Line Control Register Options
+#define UART_LCR_SET_BREAK		(1 << UART_BIT_LCR_SB)	
+
+#define UART_LCR_NO_PARITY		((0 << UART_BIT_LCR_PEN) | (0 << UART_BIT_LCR_EPS) | (0 << UART_BIT_LCR_SP))
+#define UART_LCR_ODD_PARITY		((1 << UART_BIT_LCR_PEN) | (0 << UART_BIT_LCR_EPS) | (0 << UART_BIT_LCR_SP))
+#define UART_LCR_EVEN_PARITY	((1 << UART_BIT_LCR_PEN) | (1 << UART_BIT_LCR_EPS) | (0 << UART_BIT_LCR_SP))
+#define UART_LCR_STICK1_PARITY	((1 << UART_BIT_LCR_PEN) | (0 << UART_BIT_LCR_EPS) | (1 << UART_BIT_LCR_SP))
+#define UART_LCR_STICK0_PARITY	((1 << UART_BIT_LCR_PEN) | (1 << UART_BIT_LCR_EPS) | (1 << UART_BIT_LCR_SP))
+
+#define UART_LCR_TWO_STOPBITS	(1 << UART_BIT_LCR_STB)
+
+#define UART_LCR_WL5		((0 << UART_BIT_LCR_WLS1) | (0 << UART_BIT_LCR_WLS0))
+#define UART_LCR_WL6		((0 << UART_BIT_LCR_WLS1) | (1 << UART_BIT_LCR_WLS0))
+#define UART_LCR_WL7		((1 << UART_BIT_LCR_WLS1) | (0 << UART_BIT_LCR_WLS0))
+#define UART_LCR_WL8		((1 << UART_BIT_LCR_WLS1) | (1 << UART_BIT_LCR_WLS0))
+
+// Interrupt Identification
+#define UART_IRQ_NONE		0x01	// No Interrupt			
+#define UART_IRQ_LS			0x06	// Line Status Interrupt
+#define UART_IRQ_RX			0x04	// Data Received or RX FIFO trigger level reached
+#define UART_IRQ_TX			0x02	// THR Empty or TX FIFO below trigger level
+
+// Default Register values
+#define UART_DEFAULT_RBR	0x00	//00000000b
+#define UART_DEFAULT_THR	0x00	//00000000b
+#define UART_DEFAULT_IER	0x00	//00000001b
+#define UART_DEFAULT_IIR	0x01	//00000001b
+#define UART_DEFAULT_FCR	0x01	//00000001b
+#define UART_DEFAULT_LCR	(UART_LCR_ODD_PARITY | UART_LCR_WL7)
+#define UART_DEFAULT_LSR	0x60	//01100000b
+
+#endif // H_UART_MEMORY_MAP

data/spec/test_data/spiritconsortium.org/Leon2TLM/uart_scml/1.0/tlmsrc/inc/uart_types.h

@@ -0,0 +1,60 @@
+// 
+// Revision:    $Revision: 1506 $
+// Date:        $Date: 2009-04-26 01:51:56 -0500 (Sun, 26 Apr 2009) $
+// 
+// Copyright (c) 2005, 2006, 2007, 2008, 2009 The SPIRIT Consortium.
+// 
+// This work forms part of a deliverable of The SPIRIT Consortium.
+// 
+// Use of these materials are governed by the legal terms and conditions
+// outlined in the disclaimer available from www.spiritconsortium.org.
+// 
+// This source file is provided on an AS IS basis.  The SPIRIT
+// Consortium disclaims any warranty express or implied including
+// any warranty of merchantability and fitness for use for a
+// particular purpose.
+// 
+// The user of the source file shall indemnify and hold The SPIRIT
+// Consortium and its members harmless from any damages or liability.
+// Users are requested to provide feedback to The SPIRIT Consortium
+// using either mailto:feedback@lists.spiritconsortium.org or the forms at 
+// http://www.spiritconsortium.org/about/contact_us/
+// 
+// This file may be copied, and distributed, with or without
+// modifications; but this notice must be included on any copy.
+
+
+// uart_types.h
+
+#ifndef H_UART_TYPES
+#define H_UART_TYPES
+
+//*******************************
+//*		Type Definitions		*
+//*******************************
+typedef unsigned int DATA_TYPE;						
+typedef unsigned int ADDRESS_TYPE;
+
+typedef struct SerialDataStructure {			// This structure is send and received through the serial UART interface
+	bool StartBit;
+	unsigned char Data;
+	bool Parity;
+	bool StopBit;
+
+	// Default Constructor
+	SerialDataStructure() {
+		StartBit = 1;
+		Data = '0';
+		Parity = 1;
+		StopBit = 1;
+	};
+	// Constructor with argument passing
+	SerialDataStructure(bool pStartBit, unsigned char pData, bool pParity, bool pStopBit) {
+		StartBit = pStartBit;
+		Data = pData;
+		Parity = pParity;
+		StopBit = pStopBit;
+	}
+} SERIAL_DATA_STRUCTURE;
+
+#endif // H_UART_TYPES

data/spec/test_data/spiritconsortium.org/Leon2TLM/uart_scml/1.0/tlmsrc/src/uart.cc

@@ -0,0 +1,125 @@
+// 
+// Revision:    $Revision: 1506 $
+// Date:        $Date: 2009-04-26 01:51:56 -0500 (Sun, 26 Apr 2009) $
+// 
+// Copyright (c) 2005, 2006, 2007, 2008, 2009 The SPIRIT Consortium.
+// 
+// This work forms part of a deliverable of The SPIRIT Consortium.
+// 
+// Use of these materials are governed by the legal terms and conditions
+// outlined in the disclaimer available from www.spiritconsortium.org.
+// 
+// This source file is provided on an AS IS basis.  The SPIRIT
+// Consortium disclaims any warranty express or implied including
+// any warranty of merchantability and fitness for use for a
+// particular purpose.
+// 
+// The user of the source file shall indemnify and hold The SPIRIT
+// Consortium and its members harmless from any damages or liability.
+// Users are requested to provide feedback to The SPIRIT Consortium
+// using either mailto:feedback@lists.spiritconsortium.org or the forms at 
+// http://www.spiritconsortium.org/about/contact_us/
+// 
+// This file may be copied, and distributed, with or without
+// modifications; but this notice must be included on any copy.
+
+
+// uart.cpp
+
+//***************************
+//*		Includes			*
+//***************************
+#include "uart.h"
+
+//***************************************
+//*		UART Module: Constructor	*
+//***************************************
+uart::uart(sc_module_name Name) :
+	sc_module(Name),
+	pPVTargetPort("pPVTargetPort"),
+	pReset("pReset"),
+	pInterrupt("pInterrupt"),
+	pSerialOut("pSerialOut"),
+	pSerialIn("pSerialIn"),
+	mRegisterBank("mRegisterBank", scml_memsize(UART_MEM_SIZE)),
+	rRBR_THR("rRBR_THR", mRegisterBank, UART_REG_RBR, 1),
+	rIIR_FCR("rIIR_FCR", mRegisterBank, UART_REG_IIR, 1),
+	rIER("rIER", mRegisterBank, UART_REG_IER, 1),
+	bIER_ELSI("bIER_ELSI", rIER, UART_BIT_IER_ELSI, 1),
+	bIER_ETBEI("bIER_ETBEI", rIER, UART_BIT_IER_ETBEI, 1),
+	bIER_ERBFI("bIER_ERBFI", rIER, UART_BIT_IER_ERBFI, 1),
+	rLCR("rLCR", mRegisterBank, UART_REG_LCR, 1),
+	bLCR_SB("bLCR_SB", rLCR, UART_BIT_LCR_SB, 1),
+	bLCR_SP("bLCR_SP", rLCR, UART_BIT_LCR_SP, 1),
+	bLCR_EPS("bLCR_EPS", rLCR, UART_BIT_LCR_EPS, 1),
+	bLCR_PEN("bLCR_PEN", rLCR, UART_BIT_LCR_PEN, 1),
+	bLCR_STB("bLCR_STB", rLCR, UART_BIT_LCR_STB, 1),
+	bLCR_WLS1("bLCR_WLS1", rLCR, UART_BIT_LCR_WLS1, 1),
+	bLCR_WLS0("bLCR_WLS0", rLCR, UART_BIT_LCR_WLS0, 1),
+	rLSR("rLSR", mRegisterBank, UART_REG_LSR, 1),
+	bLSR_THRE("bLSR_THRE", rLSR, UART_BIT_LSR_THRE, 1),
+	bLSR_BI("bLSR_BI", rLSR, UART_BIT_LSR_BI, 1),
+	bLSR_FE("bLSR_FE", rLSR, UART_BIT_LSR_FE, 1),
+	bLSR_PE("bLSR_PE", rLSR, UART_BIT_LSR_PE, 1),
+	bLSR_OE("bLSR_OE", rLSR, UART_BIT_LSR_OE, 1),
+	bLSR_DR("bLSR_DR", rLSR, UART_BIT_LSR_DR, 1),
+	rRBR("rRBR", scml_memsize(1)),
+	rTHR("rTHR", scml_memsize(1)),
+	rIIR("rIIR", scml_memsize(1)),
+	rFCR("rFCR", scml_memsize(1)),
+	bFCR_FIFOE("bFCR_FIFOE", rFCR, UART_BIT_FCR_FIFOE, 1),
+	TX_FIFO("TX_FIFO", TX_FIFO_SIZE),
+	RX_FIFO("RX_FIFO", RX_FIFO_SIZE)
+	{
+
+	mRegisterBank.set_addressing_mode(8);	// Set memory to byte addressing
+
+	pPVTargetPort(mRegisterBank);			// Bind the PV port to the register bank
+	
+	// Initialize global class variables
+	Clear_LS_Interrupt = false;
+	Clear_RX_Interrupt = false;
+	Clear_TX_Interrupt = false;
+	CurrentInterruptPriority = 6;
+
+	pSerialIn.bind(*this);					// bind the 'pSerialIn' export to this module
+
+	// Register the call-back functions of the register aliases
+	MEMORY_REGISTER_NB_WRITE(rRBR_THR, RegCB_RBR_THR_Write);
+	MEMORY_REGISTER_NB_READ(rRBR_THR, RegCB_RBR_THR_Read);
+
+	MEMORY_REGISTER_NB_WRITE(rIIR_FCR, RegCB_IIR_FCR_Write);
+	MEMORY_REGISTER_NB_READ(rIIR_FCR, RegCB_IIR_FCR_Read);
+
+	MEMORY_REGISTER_NB_READ(rLSR, RegCB_LSR_Read);
+	
+	MEMORY_REGISTER_NB_WRITE(rIER, RegCB_IER_Write);
+  
+	// Declare methods
+	SC_METHOD(Serial_Transmit);
+	sensitive << TransmitEvent;
+	dont_initialize();
+
+	SC_METHOD(Handle_Interrupts);
+	sensitive << InterruptEvent;
+	dont_initialize();
+
+	SC_METHOD(Reset);
+	sensitive << pReset.pos();
+};
+
+//*******************************************************************
+//*		UART Module: Reset()									*
+//*		This Function resets all registers to their default value.	*
+//*******************************************************************
+void uart::Reset() {
+  cout << name() << " resetting registers" << endl;
+	mRegisterBank.initialize(0);
+	rRBR = UART_DEFAULT_RBR;
+	rTHR = UART_DEFAULT_THR;
+	rIER = UART_DEFAULT_IER;
+	rIIR = UART_DEFAULT_IIR;
+	rFCR = UART_DEFAULT_FCR;
+	rLCR = UART_DEFAULT_LCR;
+	rLSR = UART_DEFAULT_LSR;
+};

data/spec/test_data/spiritconsortium.org/Leon2TLM/uart_scml/1.0/tlmsrc/src/uart_interrupt_handler.cc

@@ -0,0 +1,136 @@
+// 
+// Revision:    $Revision: 1506 $
+// Date:        $Date: 2009-04-26 01:51:56 -0500 (Sun, 26 Apr 2009) $
+// 
+// Copyright (c) 2005, 2006, 2007, 2008, 2009 The SPIRIT Consortium.
+// 
+// This work forms part of a deliverable of The SPIRIT Consortium.
+// 
+// Use of these materials are governed by the legal terms and conditions
+// outlined in the disclaimer available from www.spiritconsortium.org.
+// 
+// This source file is provided on an AS IS basis.  The SPIRIT
+// Consortium disclaims any warranty express or implied including
+// any warranty of merchantability and fitness for use for a
+// particular purpose.
+// 
+// The user of the source file shall indemnify and hold The SPIRIT
+// Consortium and its members harmless from any damages or liability.
+// Users are requested to provide feedback to The SPIRIT Consortium
+// using either mailto:feedback@lists.spiritconsortium.org or the forms at 
+// http://www.spiritconsortium.org/about/contact_us/
+// 
+// This file may be copied, and distributed, with or without
+// modifications; this notice must be included on any copy.
+
+
+// uart_interrupt_handler.cpp
+
+//***************************
+//*		Includes			*
+//***************************
+#include "uart.h"
+
+//***********************************************************************************
+//*		UART Module: Handle_Interrupts()										*
+//*		This Method is triggered by the 'InterruptEvent' event.						*
+//*		It checks the status of the UART and issues interrupts when necessary.		*
+//***********************************************************************************
+void uart::Handle_Interrupts() {
+	
+	rIIR = (bFCR_FIFOE << 7) | (bFCR_FIFOE << 6) | UART_IRQ_NONE;					// Set the IIR register do default value (NO interrupt pending)
+
+	if (CurrentInterruptPriority == 1 && Clear_LS_Interrupt == true) {					// If the Line Status Interrupt is to be cleared...
+		cout << sc_time_stamp() << ": " << name() << ": Line Status Interrupt Cleared." << endl;
+		Clear_LS_Interrupt = false;
+		bLSR_OE = 0;								// Clear the Overflow Error bit
+		bLSR_PE = 0;								// Clear the Parity Error bit
+		bLSR_FE = 0;								// Clear the Framing Error bit
+		bLSR_BI = 0;								// Clear the Break Indicator bit
+		CurrentInterruptPriority = 6;				// Reset interrupt priority level
+		pInterrupt = 0;							// Clear Interrupt line
+		InterruptEvent.notify();		// Check for additional interrupts
+		return;
+	}
+	if (CurrentInterruptPriority == 2 && Clear_RX_Interrupt == true) {				// If the Receive Buffer full Interrupt is to be cleared...
+		cout << sc_time_stamp() << ": " << name() << ": Receiver Interrupt Cleared." << endl;
+		Clear_RX_Interrupt = false;
+		CurrentInterruptPriority = 6;		// Reset interrupt priority level
+		pInterrupt = 0;					// Clear Interrupt line
+		InterruptEvent.notify();			// Check for additional interrupts
+		return;
+	}
+	if (CurrentInterruptPriority == 3 && Clear_TX_Interrupt == true) {				// If the Transmit Buffer empty Interrupt is to be cleared...
+		cout << sc_time_stamp() << ": " << name() << ": Transmitter Interrupt Cleared." << endl;
+		Clear_TX_Interrupt = false;
+		CurrentInterruptPriority = 6;		// Reset interrupt priority level
+		pInterrupt = 0;					// Clear Interrupt line
+		InterruptEvent.notify();			// Check for additional interrupts
+		return;
+	}
+	// Reset the Clear Interrupt variables
+	Clear_LS_Interrupt = false;	
+	Clear_TX_Interrupt = false;
+	Clear_RX_Interrupt = false;
+
+	// Check for new Interrupts:
+	if (bIER_ELSI){								// If the Line Status Interrupt is Enabled...
+		if (bLSR_OE | bLSR_PE | bLSR_FE | bLSR_BI) {			// If the Overflow Error, Parity Error, Framing Error or Break Indicator flag is set...
+			rIIR = (bFCR_FIFOE << 7) | (bFCR_FIFOE << 6) | UART_IRQ_LS;		// Update IIR to indicate a Line Status Interrupt is set
+			CurrentInterruptPriority = 1;						// Update Interrupt Priority level
+			if (pInterrupt == 1) {							// If there already is an interrupt pending
+				pInterrupt = 0;								// Clear the interrupt line
+				InterruptEvent.notify(SC_ZERO_TIME);	// Call this function again, with a delta cycle delay. This should make the interrupt line low for one delta cycle.
+				return;
+			}
+			pInterrupt = 1;									// Set the interrupt line
+			return;
+		}
+	}
+	if (bIER_ERBFI) {							// If the Receive Buffer Full Interrupt is Enabled...
+		if (bLSR_DR) {									// If the Data Ready flag is set...
+			if (bFCR_FIFOE) {							// If the FIFOs are Enabled...
+				if (RX_FIFO.IsAboveTriggerLevel()) {	// If the Receive FIFO is above its trigger level...
+					rIIR = (bFCR_FIFOE << 7) | (bFCR_FIFOE << 6) | UART_IRQ_RX;	// Update IIR to indicate a Receive Buffer Full Interrupt is set
+					CurrentInterruptPriority = 2;		// Update Interrupt Priority level
+					if (pInterrupt == 1) {			// If there already is an interrupt pending...
+						pInterrupt = 0;				// Clear the interrupt line
+						InterruptEvent.notify(SC_ZERO_TIME);	// Call this function again, with a delta cycle delay. This should make the interrupt line low for one delta cycle.
+						return;
+					}
+					pInterrupt = 1;					// Set the interrupt line
+					return;
+				}
+			} else {
+				rIIR = (bFCR_FIFOE << 7) | (bFCR_FIFOE << 6) | UART_IRQ_RX;	// Update IIR to indicate a Receive Buffer Full Interrupt is set
+				CurrentInterruptPriority = 2;						// Update Interrupt Priority level
+				if (pInterrupt == 1) {							// If there already is an interrupt pending...
+					pInterrupt = 0;								// Clear the interrupt line
+					InterruptEvent.notify(SC_ZERO_TIME);	// Call this function again, with a delta cycle delay. This should make the interrupt line low for one delta cycle.
+					return;
+				}
+				pInterrupt = 1;						// Set the interrupt line
+				return;
+			}
+		}
+	}
+	if (bIER_ETBEI) {								// If the Transmit Buffer Empty Interrupt is Enabled...
+		if (bLSR_THRE) {										// If the THR Empty bit is set...
+			rIIR = (bFCR_FIFOE << 7) | (bFCR_FIFOE << 6) | UART_IRQ_TX;		// Update IIR to indicate a Transmit Buffer Empty Interrupt is set
+			CurrentInterruptPriority = 3;						// Update Interrupt Priority level
+			if (pInterrupt == 1) {							// If there already is an interrupt pending...
+				pInterrupt = 0;								// Clear the interrupt line
+				InterruptEvent.notify(SC_ZERO_TIME);	// Call this function again, with a delta cycle delay. This should make the interrupt line low for one delta cycle.
+				return;
+			}
+			pInterrupt = 1;							// Set the interrupt line
+			return;
+		}
+	}
+
+	// No interrups 
+	CurrentInterruptPriority = 6;						// Reset interrupt priority level
+	pInterrupt = 0;									// Clear the interrupt line
+	
+	return;
+};