ipxact-ruby 0.11.1

data/spec/test_data/spiritconsortium.org/Leon2TLM/timers/1.4/tlmsrc/timers.cc

@@ -0,0 +1,201 @@
+// 
+// Revision:    $Revision: 1506 $
+// Date:        $Date: 2009-04-26 01:51:56 -0500 (Sun, 26 Apr 2009) $
+// 
+// Copyright (c) 2005, 2006, 2007, 2008, 2009 The SPIRIT Consortium.
+// 
+// This work forms part of a deliverable of The SPIRIT Consortium.
+// 
+// Use of these materials are governed by the legal terms and conditions
+// outlined in the disclaimer available from www.spiritconsortium.org.
+// 
+// This source file is provided on an AS IS basis.  The SPIRIT
+// Consortium disclaims any warranty express or implied including
+// any warranty of merchantability and fitness for use for a
+// particular purpose.
+// 
+// The user of the source file shall indemnify and hold The SPIRIT
+// Consortium and its members harmless from any damages or liability.
+// Users are requested to provide feedback to The SPIRIT Consortium
+// using either mailto:feedback@lists.spiritconsortium.org or the forms at 
+// http://www.spiritconsortium.org/about/contact_us/
+// 
+// This file may be copied, and distributed, with or without
+// modifications; but this notice must be included on any copy.
+
+/*------------------------------------------------------------------------------
+ * Includes							       
+ *----------------------------------------------------------------------------*/
+#include "timers.h"
+
+/*------------------------------------------------------------------------------
+ * Methods
+ *----------------------------------------------------------------------------*/
+timers::timers( sc_module_name module_name ) :
+  sc_module( module_name ),
+  pv_slave_base<ADDRESS_TYPE,DATA_TYPE>(name()),
+  apb_slave_port("apb_slave_port"),
+  int0("int0"),
+  int1("int1"),
+  clk("clk")
+{
+  apb_slave_port( *this );
+  int0.initialize(false);
+  int1.initialize(false);
+  init_registers();
+  SC_METHOD(count); // timer process
+  dont_initialize();
+  sensitive << clk;
+}
+
+timers::~timers() {
+}
+
+void timers::end_of_elaboration() {
+  cout << name() << " constructed." << endl;
+}
+
+tlm::tlm_status timers::write( const ADDRESS_TYPE &addr , const DATA_TYPE &data,
+			       const unsigned int byte_enable,
+			       const tlm::tlm_mode mode,
+			       const unsigned int export_id)
+{
+  tlm::tlm_status status;
+  if ((addr < TIMER_BASE_ADDR) || (addr >= TIMER_BASE_ADDR+TIMER_SIZE)) {
+    cout << "ERROR\t" << name() << " : trying to write out of bounds at address " << addr << endl;
+    status.set_error();
+    return status;
+  }
+  // Write the register with the correct mask.
+  switch (addr) {
+    case TIMER0_CONTROL:
+      registers[addr] = data & 0x7;
+      break;
+    case TIMER1_CONTROL:
+      registers[addr] = data & 0x7;
+      break;
+    case PRESCALER_COUNTER:
+      registers[addr] = data & 0x3FF;
+      break;
+    case PRESCALER_RELOAD_VALUE:
+      registers[addr] = data & 0x3FF;
+      break;
+    default :
+      registers[addr] = data & 0xFFFFFF;
+      break;
+  }
+
+  if (addr==TIMER0_CONTROL) {
+    // reload timer
+    if (data & TIMER_CTRL) {
+      cout << name() << " Timer0 forced reload" << endl;
+      registers[TIMER0_COUNTER] = registers[TIMER0_RELOAD];
+      registers[TIMER0_CONTROL] = data & 0x3; // reset reload bit
+    }
+    if ((data & TIMER_ENABLE) == TIMER_DISABLED) {
+      cout << name() << " Timer0 disabled (clear control register0)" << endl;
+    }
+  }
+
+  if (addr==TIMER1_CONTROL) {
+    // reload timer
+    if (data & TIMER_CTRL) {
+      cout << name() << " Timer1 forced reload" << endl;
+      registers[TIMER1_COUNTER] = registers[TIMER1_RELOAD];
+      registers[TIMER1_CONTROL] = data & 0x3; // reset reload bit
+    }
+    if ((data & TIMER_ENABLE) == TIMER_DISABLED) {
+      cout << name() << " Timer1 disabled (clear control register1)" << endl;
+    }
+  }
+
+  status.set_ok();
+  return status;
+}
+
+tlm::tlm_status timers::read( const ADDRESS_TYPE &addr , DATA_TYPE &data,
+			      const unsigned int byte_enable,
+			      const tlm::tlm_mode mode,
+			      const unsigned int export_id)
+{
+  tlm::tlm_status status;
+  if ((addr < TIMER_BASE_ADDR) || (addr >= TIMER_BASE_ADDR+TIMER_SIZE)) {
+    cout << "ERROR\t" << name() << " : trying to read out of bounds at address " << addr << endl;
+    status.set_error();
+    return status;
+  }
+  data = registers[addr];
+  status.set_ok();
+  return status;
+}
+
+void timers::init_registers() 
+{
+  for (int i=0; i < 9; i++) registers[i]=0;
+}
+
+void timers::count() 
+{
+  
+  if (clk.posedge()) {
+
+  // Prescaler
+  if ((registers[PRESCALER_COUNTER] > 0)) { 
+    registers[PRESCALER_COUNTER]--;
+  }
+  else {
+    registers[PRESCALER_COUNTER] = registers[PRESCALER_RELOAD_VALUE];
+  }
+ 
+  // Update the timer only if the prescaler value is 0
+  if ((registers[PRESCALER_COUNTER] == 0)) { 
+    // Timer 0
+    if ((registers[TIMER0_CONTROL] & TIMER_ENABLE) == TIMER_ENABLED) {
+      if ((registers[TIMER0_COUNTER] > 0)) { 
+	cout << "... T0=" << registers[TIMER0_COUNTER] << " At Time " << sc_time_stamp() << endl;
+	registers[TIMER0_COUNTER]--;
+      }
+      if (registers[TIMER0_COUNTER] == 0) {
+ 	int0.write(1);
+	if ((registers[TIMER0_CONTROL] & TIMER_LOAD)) {
+	  registers[TIMER0_COUNTER] = registers[TIMER0_RELOAD];
+	}
+      }
+      else {
+	if (int0.read() == 1) 
+  	  int0.write(0);
+      }
+    }
+
+    // Timer 1
+    if ((registers[TIMER1_CONTROL] & TIMER_ENABLE) == TIMER_ENABLED) {
+      if ((registers[TIMER1_COUNTER] > 0)) { 
+	cout << "... T1=" << registers[TIMER1_COUNTER] << " At Time " << sc_time_stamp() << endl;
+	registers[TIMER1_COUNTER]--;
+      }
+      if (registers[TIMER1_COUNTER] == 0) {
+	int1.write(1);
+	if ((registers[TIMER1_CONTROL] & TIMER_LOAD)) {
+	  registers[TIMER1_COUNTER] = registers[TIMER1_RELOAD];
+	}
+      }
+      else {
+	if (int1.read() == 1) 
+	  int1.write(0);
+      }
+    }
+  }
+
+  if ((registers[TIMER0_CONTROL] & TIMER_ENABLE) == TIMER_DISABLED && int0.read() == 1) {
+    int0.write(0);
+  }
+
+  if ((registers[TIMER1_CONTROL] & TIMER_ENABLE) == TIMER_DISABLED && int1.read() == 1) {
+    int1.write(0);
+  }
+
+  // Timer count rate ( SC kernel recall this method when simulation time
+  // reaches now + 10 ns
+  //next_trigger(10,SC_NS);
+  }
+}

data/spec/test_data/spiritconsortium.org/Leon2TLM/timers/1.4/tlmsrc/timers.h

@@ -0,0 +1,102 @@
+// 
+// Revision:    $Revision: 1506 $
+// Date:        $Date: 2009-04-26 01:51:56 -0500 (Sun, 26 Apr 2009) $
+// 
+// Copyright (c) 2005, 2006, 2007, 2008, 2009 The SPIRIT Consortium.
+// 
+// This work forms part of a deliverable of The SPIRIT Consortium.
+// 
+// Use of these materials are governed by the legal terms and conditions
+// outlined in the disclaimer available from www.spiritconsortium.org.
+// 
+// This source file is provided on an AS IS basis.  The SPIRIT
+// Consortium disclaims any warranty express or implied including
+// any warranty of merchantability and fitness for use for a
+// particular purpose.
+// 
+// The user of the source file shall indemnify and hold The SPIRIT
+// Consortium and its members harmless from any damages or liability.
+// Users are requested to provide feedback to The SPIRIT Consortium
+// using either mailto:feedback@lists.spiritconsortium.org or the forms at 
+// http://www.spiritconsortium.org/about/contact_us/
+// 
+// This file may be copied, and distributed, with or without
+// modifications; but this notice must be included on any copy.
+
+
+#ifndef _TIMERS_H_
+#define _TIMERS_H_
+
+/*------------------------------------------------------------------------------
+ * Includes							       
+ *----------------------------------------------------------------------------*/
+#include <systemc.h>
+
+#include "pv_slave_base.h"
+#include "pv_target_port.h"
+#include "user_types.h"
+
+
+/*------------------------------------------------------------------------------
+ * Define device parameters
+ *----------------------------------------------------------------------------*/
+#define TIMER_BASE_ADDR     0x0000 // in global systems, start at: 0x30001000
+#define TIMER_SIZE          0x1000 // 4Kb
+
+/*------------------------------------------------------------------------------
+ * Define Timer Registers
+ * Note : here static, but could be read from external description
+ *----------------------------------------------------------------------------*/
+
+#define TIMER_REGISTER_SIZE     0x4 // in bytes
+#define TIMER0_COUNTER          TIMER_BASE_ADDR
+#define TIMER0_RELOAD           TIMER_BASE_ADDR + 1*TIMER_REGISTER_SIZE
+#define TIMER0_CONTROL          TIMER_BASE_ADDR + 2*TIMER_REGISTER_SIZE
+#define WATCHDOG_COUNTER        TIMER_BASE_ADDR + 3*TIMER_REGISTER_SIZE
+#define TIMER1_COUNTER          TIMER_BASE_ADDR + 4*TIMER_REGISTER_SIZE
+#define TIMER1_RELOAD           TIMER_BASE_ADDR + 5*TIMER_REGISTER_SIZE
+#define TIMER1_CONTROL          TIMER_BASE_ADDR + 6*TIMER_REGISTER_SIZE
+#define PRESCALER_COUNTER       TIMER_BASE_ADDR + 7*TIMER_REGISTER_SIZE
+#define PRESCALER_RELOAD_VALUE  TIMER_BASE_ADDR + 8*TIMER_REGISTER_SIZE
+
+#define TIMER_ENABLE        1
+#define TIMER_LOAD          2
+#define TIMER_CTRL          4
+#define TIMER_DISABLED      0
+#define TIMER_ENABLED       1
+/*------------------------------------------------------------------------------
+ * leon2 timers
+ *----------------------------------------------------------------------------*/
+
+class timers :
+  public sc_module ,
+  public pv_slave_base< ADDRESS_TYPE , DATA_TYPE >
+{
+public:
+  SC_HAS_PROCESS(timers);
+  timers( sc_module_name module_name );
+  ~timers();
+
+  pv_target_port<ADDRESS_TYPE,DATA_TYPE>    apb_slave_port;
+  sc_out<int>		int0;
+  sc_out<int>		int1;
+  sc_in<sc_logic>	clk;
+
+  tlm::tlm_status write( const ADDRESS_TYPE &addr , const DATA_TYPE &data,
+			 const unsigned int byte_enable = tlm::NO_BE,
+			 const tlm::tlm_mode mode = tlm::REGULAR,
+			 const unsigned int export_id = 0 );
+  tlm::tlm_status read( const ADDRESS_TYPE &addr , DATA_TYPE &data,
+			const unsigned int byte_enable = tlm::NO_BE,
+			const tlm::tlm_mode mode = tlm::REGULAR,
+			const unsigned int export_id = 0 );
+
+private:
+  sc_pvector<DATA_TYPE> registers;
+  int prescaler;
+  void init_registers();
+  void count();
+  void end_of_elaboration();
+};
+
+#endif /* _TIMERS_H_ */

data/spec/test_data/spiritconsortium.org/Leon2TLM/uart_scml/1.0/tlmsrc/inc/uart.h

@@ -0,0 +1,152 @@
+// 
+// Revision:    $Revision: 1506 $
+// Date:        $Date: 2009-04-26 01:51:56 -0500 (Sun, 26 Apr 2009) $
+// 
+// Copyright (c) 2005, 2006, 2007, 2008, 2009 The SPIRIT Consortium.
+// 
+// This work forms part of a deliverable of The SPIRIT Consortium.
+// 
+// Use of these materials are governed by the legal terms and conditions
+// outlined in the disclaimer available from www.spiritconsortium.org.
+// 
+// This source file is provided on an AS IS basis.  The SPIRIT
+// Consortium disclaims any warranty express or implied including
+// any warranty of merchantability and fitness for use for a
+// particular purpose.
+// 
+// The user of the source file shall indemnify and hold The SPIRIT
+// Consortium and its members harmless from any damages or liability.
+// Users are requested to provide feedback to The SPIRIT Consortium
+// using either mailto:feedback@lists.spiritconsortium.org or the forms at 
+// http://www.spiritconsortium.org/about/contact_us/
+// 
+// This file may be copied, and distributed, with or without
+// modifications; but this notice must be included on any copy.
+
+
+// uart.h
+
+#ifndef H_UART
+#define H_UART
+
+//***************************
+//*		Includes			*
+//***************************
+#include "scml.h"							            // For 'scml_memory' and 'scml_bitfield'
+#include "tlm_interfaces/tlm_core_ifs.h"	// For 'tlm_blocking_put_if'
+#include "PV/PV.h"							          // For 'PVTarget_port'
+
+#include "uart_fifo.h"					// For 'UART_FIFO'
+#include "uart_types.h"					// For UART data types
+#include "uart_memory_map.h"		// For the register and bit positions
+
+//***********************
+//*		Definitions		*
+//***********************
+#define TX_FIFO_SIZE	16		// Size of Transmit FIFO
+#define RX_FIFO_SIZE	16		// Size of Receive FIFO
+
+//***********************************
+//*		UART Module Class		*
+//***********************************
+class uart : 
+	public sc_module,
+	virtual public tlm::tlm_blocking_put_if<SERIAL_DATA_STRUCTURE> {
+public:
+	//**** Port Declarations ****//
+	PVTarget_port<DATA_TYPE, ADDRESS_TYPE> pPVTargetPort;		// PV port
+	
+	sc_in<bool> pReset;									  // Reset pin to reset the registers to their default values. active high
+	sc_out<int> pInterrupt;								// Interrupt Line, active high
+	
+	sc_port<tlm::tlm_blocking_put_if<SERIAL_DATA_STRUCTURE> > pSerialOut;	// Serial data output port.
+	sc_export<tlm::tlm_blocking_put_if<SERIAL_DATA_STRUCTURE> > pSerialIn;	// Serial data input port. export bound to this module.
+	
+	SC_HAS_PROCESS(uart);
+	//**** Constructor ****//
+	uart(sc_module_name Name);
+
+private:
+	void Reset();		// Function to reset all registers to their default values (which are defined in 'uart_memory_map.h')
+	
+	// ******************
+	// * Register Bank	*
+	// ******************
+	scml_memory<DATA_TYPE> mRegisterBank;
+	// Aliases of 'mRegisterBank'
+		scml_memory<DATA_TYPE> rRBR_THR;	// Shared RBR(read-only) and THR(write-only) location
+		scml_memory<DATA_TYPE> rIIR_FCR;	// Shared IIR(read-only) and FCR(write-only) location
+		scml_memory<DATA_TYPE> rIER;		// Interrupt Enable (Mask) Register
+		// Bitfield aliases of IER register:
+			scml_bitfield	bIER_ELSI;		// Enable Line Status Interrupt bit
+			scml_bitfield	bIER_ETBEI;		// Enable Transmit Buffer Empty Interrupt bit
+			scml_bitfield	bIER_ERBFI;		// Enable Receive Buffer Full Interrupt bit
+		scml_memory<DATA_TYPE> rLCR;		// Line Control Register
+		// Bitfield aliases of LCR register:
+			scml_bitfield	bLCR_SB;		// Set Break bit
+			scml_bitfield	bLCR_SP;		// Stick Parity bit
+			scml_bitfield	bLCR_EPS;		// Even Parity Select bit
+			scml_bitfield	bLCR_PEN;		// Parity ENable bit
+			scml_bitfield	bLCR_STB;		// number of STop Bits bit
+			scml_bitfield	bLCR_WLS1;		// Word Length Select bit 1
+			scml_bitfield	bLCR_WLS0;		// Word Length Select bit 0
+		scml_memory<DATA_TYPE> rLSR;		// Line Status Register
+		// Bitfield aliases of LSR register:
+			scml_bitfield	bLSR_THRE;		// THR Empty bit
+			scml_bitfield	bLSR_BI;		// Break Indicator bit
+			scml_bitfield	bLSR_FE;		// Frame Error bit
+			scml_bitfield	bLSR_PE;		// Parity Error bit
+			scml_bitfield	bLSR_OE;		// Overflow Error bit
+			scml_bitfield	bLSR_DR;		// Data Ready bit
+
+	// Seperate registers (1 word big)
+	scml_memory<DATA_TYPE> rRBR;		// Receiver Buffer Register (read-only)
+	scml_memory<DATA_TYPE> rTHR;		// Transmitter Holding Register (write-only)
+	scml_memory<DATA_TYPE> rIIR;		// Interrupt Identification Register (read-only)
+	scml_memory<DATA_TYPE> rFCR;		// FIFO Control Register (write-only)
+		// Bitfield aliases of FCR register:
+		scml_bitfield	bFCR_FIFOE;		// FIFOs Enable bit
+	
+	// **********************************
+	// *  Register Call-back Functions	*
+	// **********************************
+	void		RegCB_RBR_THR_Write(DATA_TYPE WriteData, unsigned int AccessSize, unsigned int Offset);
+	DATA_TYPE	RegCB_RBR_THR_Read(unsigned int AccessSize, unsigned int Offset);
+	
+	void		RegCB_IIR_FCR_Write(DATA_TYPE WriteData, unsigned int AccessSize, unsigned int Offset);
+	DATA_TYPE	RegCB_IIR_FCR_Read(unsigned int AccessSize, unsigned int Offset);
+
+	DATA_TYPE	RegCB_LSR_Read(unsigned int AccessSize, unsigned int Offset);
+	
+	void RegCB_IER_Write(DATA_TYPE WriteData, unsigned int AccessSize, unsigned int Offset);
+	
+	// ****************
+	// * FIFO Buffers *
+	// ****************
+	UART_FIFO<DATA_TYPE>	TX_FIFO;	// Transmit FIFO
+	UART_FIFO<DATA_TYPE>	RX_FIFO;	// Receive FIFO
+
+	// ********************************
+	// * Serial Transmit and Receive  *
+	// ********************************
+	void Serial_Transmit();		// Method triggerd by 'TransmitEvent' event
+	sc_event TransmitEvent;		// Event to trigger 'Serial_Transmit()'
+	
+	//**** Interface Method of 'tlm_blocking_put_if' ****//
+	void put( const SERIAL_DATA_STRUCTURE &DataStruct );		// All 'put' method calls made to pSerialIn call this function.
+
+	// *********************
+	// * Interrupt Handler *
+	// *********************
+	bool Clear_LS_Interrupt;	// Boolean to clear the Line Status Interrupt
+	bool Clear_RX_Interrupt;	// Boolean to clear the Receive buffer full Interrupt
+	bool Clear_TX_Interrupt;	// Boolean to clear the Transmit buffer empty Interrupt
+	int CurrentInterruptPriority; // Indicator of the priority of the current interrupt.
+	
+	void Handle_Interrupts();	// Method triggered by 'InterruptEvent' event
+	sc_event InterruptEvent;	// Event to trigger 'Handle_Interrupts()'
+	
+};
+
+#endif // H_UART
+