crabstone 4.0.3 → 5.0.0

checksums.yaml

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data/CHANGES.md

@@ -1,3 +1,23 @@
+## 5.0.0
+* Support Capstone 5!
+* New architectures: BPF, MOS65XX, RISC-V, TriCore, SuperH, and WASM
+* Ensured Ruby version support 3.1 ~ 3.3
+* [Diff from previous release](https://github.com/david942j/crabstone/compare/v4.0.4...v5.0.0)
+
+## 4.0.4
+* Ensured Ruby version support 2.6 ~ 3.1
+* [Diff from previous release](https://github.com/david942j/crabstone/compare/v4.0.3...v4.0.4)
+
+## 4.0.3
+* Fixed Instruction class redefinition ([#12](https://github.com/david942j/crabstone/pull/12))
+* [Diff from previous release](https://github.com/david942j/crabstone/compare/v4.0.2...v4.0.3)
+
+## 4.0.2
+* Supported binding Capstone 4.0.2
+* Raised errors when the version of libcapstone is not supported
+* Internal refactors and code cleanup
+* [Diff from previous release](https://github.com/david942j/crabstone/compare/4.0.0...v4.0.2)
+
 ## 4.0.0
 * Supported *both* Capstone 3.x and 4.x.
 * Supported 4 new architectures: M68K, M680X, TMS320C64x, and EVM.

data/README.md

@@ -1,4 +1,5 @@
 [![Gem Version](https://badge.fury.io/rb/crabstone.svg)](https://badge.fury.io/rb/crabstone)
+[![Build Status](https://github.com/david942j/crabstone/workflows/build/badge.svg)](https://github.com/david942j/crabstone/actions)
 [![Issue Count](https://codeclimate.com/github/david942j/crabstone/badges/issue_count.svg)](https://codeclimate.com/github/david942j/crabstone)
 [![Test Coverage](https://codeclimate.com/github/david942j/crabstone/badges/coverage.svg)](https://codeclimate.com/github/david942j/crabstone/coverage)
 [![License](https://img.shields.io/badge/License-BSD%203--Clause-blue.svg)](https://opensource.org/licenses/BSD-3-Clause)
@@ -6,7 +7,7 @@
 crabstone
 ====
 
-Current library support: Capstone 3 \& 4
+Current library support: Capstone 3 \& 4 \& 5
 ----
 
 ( FROM THE CAPSTONE README )
@@ -47,7 +48,7 @@ Capstone offers some unparalleled features:
 To install:
 ----
 
-First install the capstone library from either https://github.com/aquynh/capstone
+First install the capstone library from either https://github.com/capstone-engine/capstone
 or http://www.capstone-engine.org
 
 Then:
@@ -59,17 +60,17 @@ gem install crabstone
 To write code:
 ----
 
-Check the tests in [Capstone](https://github.com/aquynh/capstone) for more examples. Here is "Hello World":
+Check the tests in [Capstone](https://github.com/capstone-engine/capstone) for
+more examples. Here is "Hello World":
 ```ruby
-
 require 'crabstone'
-include Crabstone
+
 arm =
   "\xED\xFF\xFF\xEB\x04\xe0\x2d\xe5\x00\x00\x00\x00\xe0\x83\x22" \
   "\xe5\xf1\x02\x03\x0e\x00\x00\xa0\xe3\x02\x30\xc1\xe7\x00\x00\x53\xe3"
 
 begin
-  cs = Disassembler.new(ARCH_ARM, MODE_ARM)
+  cs = Crabstone::Disassembler.new(Crabstone::ARCH_ARM, Crabstone::MODE_ARM)
   puts "Hello from Capstone v#{cs.version.join('.')}!"
   puts 'Disasm:'
 
@@ -77,16 +78,32 @@ begin
     cs.disasm(arm, 0x1000).each do |i|
       printf("0x%x:\t%s\t\t%s\n", i.address, i.mnemonic, i.op_str)
     end
-  rescue StandardError => e
+  rescue Crabstone::Error => e
     raise "Disassembly error: #{e.message}"
   ensure
     cs.close
   end
-rescue StandardError => e
+rescue Crabstone::Error => e
   raise "Unable to open engine: #{e.message}"
 end
 ```
 
+Sample output (exact content may differ according to the Capstone engine version
+you are using):
+
+```
+Hello from Capstone v3.0!
+Disasm:
+0x1000: bl              #0xfbc
+0x1004: str             lr, [sp, #-4]!
+0x1008: andeq           r0, r0, r0
+0x100c: str             r8, [r2, #-0x3e0]!
+0x1010: mcreq           p2, #0, r0, c3, c1, #7
+0x1014: mov             r0, #0
+0x1018: strb            r3, [r1, r2]
+0x101c: cmp             r3, #0
+```
+
 Contributing:
 ----
 

data/lib/crabstone/arch/3/constants.rb

@@ -0,0 +1,86 @@
+# frozen_string_literal: true
+
+# THIS FILE WAS AUTO-GENERATED -- DO NOT EDIT!
+
+module Crabstone
+  API_MAJOR = 3
+  API_MINOR = 0
+
+  VERSION_MAJOR = API_MAJOR
+  VERSION_MINOR = API_MINOR
+  VERSION_EXTRA = 5
+
+  ARCH_ARM = 0
+  ARCH_ARM64 = 1
+  ARCH_MIPS = 2
+  ARCH_X86 = 3
+  ARCH_PPC = 4
+  ARCH_SPARC = 5
+  ARCH_SYSZ = 6
+  ARCH_XCORE = 7
+  ARCH_MAX = 8
+  ARCH_ALL = 0xFFFF
+
+  MODE_LITTLE_ENDIAN = 0      # little-endian mode (default mode)
+  MODE_ARM = 0                # ARM mode
+  MODE_16 = (1 << 1)          # 16-bit mode (for X86)
+  MODE_32 = (1 << 2)          # 32-bit mode (for X86)
+  MODE_64 = (1 << 3)          # 64-bit mode (for X86, PPC)
+  MODE_THUMB = (1 << 4)       # ARM's Thumb mode, including Thumb-2
+  MODE_MCLASS = (1 << 5)      # ARM's Cortex-M series
+  MODE_V8 = (1 << 6)          # ARMv8 A32 encodings for ARM
+  MODE_MICRO = (1 << 4)       # MicroMips mode (MIPS architecture)
+  MODE_MIPS3 = (1 << 5)       # Mips III ISA
+  MODE_MIPS32R6 = (1 << 6)    # Mips32r6 ISA
+  MODE_MIPSGP64 = (1 << 7)    # General Purpose Registers are 64-bit wide (MIPS arch)
+  MODE_V9 = (1 << 4)          # Sparc V9 mode (for Sparc)
+  MODE_BIG_ENDIAN = (1 << 31) # big-endian mode
+  MODE_MIPS32 = MODE_32    # Mips32 ISA
+  MODE_MIPS64 = MODE_64    # Mips64 ISA
+
+  OPT_SYNTAX = 1    # Intel X86 asm syntax (ARCH_X86 arch)
+  OPT_DETAIL = 2    # Break down instruction structure into details
+  OPT_MODE = 3      # Change engine's mode at run-time
+  OPT_MEM = 4       # Change engine's mode at run-time
+  OPT_SKIPDATA = 5  # Skip data when disassembling
+  OPT_SKIPDATA_SETUP = 6 # Setup user-defined function for SKIPDATA option
+
+  OPT_OFF = 0             # Turn OFF an option - default option of OPT_DETAIL
+  OPT_ON = 3              # Turn ON an option (OPT_DETAIL)
+
+  OP_INVALID = 0
+  OP_REG = 1
+  OP_IMM = 2
+  OP_MEM = 3
+  OP_FP  = 4
+
+  GRP_INVALID = 0  # uninitialized/invalid group.
+  GRP_JUMP    = 1  # all jump instructions (conditional+direct+indirect jumps)
+  GRP_CALL    = 2  # all call instructions
+  GRP_RET     = 3  # all return instructions
+  GRP_INT     = 4  # all interrupt instructions (int+syscall)
+  GRP_IRET    = 5  # all interrupt return instructions
+
+  OPT_SYNTAX_DEFAULT = 0 # Default assembly syntax of all platforms (OPT_SYNTAX)
+  OPT_SYNTAX_INTEL = 1    # Intel X86 asm syntax - default syntax on X86 (OPT_SYNTAX, ARCH_X86)
+  OPT_SYNTAX_ATT = 2      # ATT asm syntax (OPT_SYNTAX, ARCH_X86)
+  OPT_SYNTAX_NOREGNAME = 3 # Asm syntax prints register name with only number - (OPT_SYNTAX, ARCH_PPC, ARCH_ARM)
+
+  ERR_OK = 0      # No error: everything was fine
+  ERR_MEM = 1     # Out-Of-Memory error: cs_open(), cs_disasm()
+  ERR_ARCH = 2    # Unsupported architecture: cs_open()
+  ERR_HANDLE = 3  # Invalid handle: cs_op_count(), cs_op_index()
+  ERR_CSH = 4     # Invalid csh argument: cs_close(), cs_errno(), cs_option()
+  ERR_MODE = 5    # Invalid/unsupported mode: cs_open()
+  ERR_OPTION = 6  # Invalid/unsupported option: cs_option()
+  ERR_DETAIL = 7  # Invalid/unsupported option: cs_option()
+  ERR_MEMSETUP = 8
+  ERR_VERSION = 9 # Unsupported version (bindings)
+  ERR_DIET = 10   # Information irrelevant in diet engine
+  ERR_SKIPDATA = 11 # Access irrelevant data for "data" instruction in SKIPDATA mode
+  ERR_X86_ATT = 12 # X86 AT&T syntax is unsupported (opt-out at compile time)
+  ERR_X86_INTEL = 13 # X86 Intel syntax is unsupported (opt-out at compile time)
+
+  SUPPORT_DIET = ARCH_ALL + 1
+  SUPPORT_X86_REDUCE = ARCH_ALL + 2
+end

data/lib/crabstone/arch/4/constants.rb

@@ -0,0 +1,116 @@
+# frozen_string_literal: true
+
+# THIS FILE WAS AUTO-GENERATED -- DO NOT EDIT!
+
+module Crabstone
+  API_MAJOR = 4
+  API_MINOR = 0
+
+  VERSION_MAJOR = API_MAJOR
+  VERSION_MINOR = API_MINOR
+  VERSION_EXTRA = 2
+
+  ARCH_ARM = 0
+  ARCH_ARM64 = 1
+  ARCH_MIPS = 2
+  ARCH_X86 = 3
+  ARCH_PPC = 4
+  ARCH_SPARC = 5
+  ARCH_SYSZ = 6
+  ARCH_XCORE = 7
+  ARCH_M68K = 8
+  ARCH_TMS320C64X = 9
+  ARCH_M680X = 10
+  ARCH_EVM = 11
+  ARCH_MAX = 12
+  ARCH_ALL = 0xFFFF
+
+  MODE_LITTLE_ENDIAN = 0      # little-endian mode (default mode)
+  MODE_ARM = 0                # ARM mode
+  MODE_16 = (1 << 1)          # 16-bit mode (for X86)
+  MODE_32 = (1 << 2)          # 32-bit mode (for X86)
+  MODE_64 = (1 << 3)          # 64-bit mode (for X86, PPC)
+  MODE_THUMB = (1 << 4)       # ARM's Thumb mode, including Thumb-2
+  MODE_MCLASS = (1 << 5)      # ARM's Cortex-M series
+  MODE_V8 = (1 << 6)          # ARMv8 A32 encodings for ARM
+  MODE_MICRO = (1 << 4)       # MicroMips mode (MIPS architecture)
+  MODE_MIPS3 = (1 << 5)       # Mips III ISA
+  MODE_MIPS32R6 = (1 << 6)    # Mips32r6 ISA
+  MODE_MIPS2 = (1 << 7)       # Mips II ISA
+  MODE_V9 = (1 << 4)          # Sparc V9 mode (for Sparc)
+  MODE_QPX = (1 << 4)         # Quad Processing eXtensions mode (PPC)
+  MODE_M68K_000 = (1 << 1)    # M68K 68000 mode
+  MODE_M68K_010 = (1 << 2)    # M68K 68010 mode
+  MODE_M68K_020 = (1 << 3)    # M68K 68020 mode
+  MODE_M68K_030 = (1 << 4)    # M68K 68030 mode
+  MODE_M68K_040 = (1 << 5)    # M68K 68040 mode
+  MODE_M68K_060 = (1 << 6)    # M68K 68060 mode
+  MODE_BIG_ENDIAN = (1 << 31) # big-endian mode
+  MODE_MIPS32 = MODE_32    # Mips32 ISA
+  MODE_MIPS64 = MODE_64    # Mips64 ISA
+  MODE_M680X_6301 = (1 << 1)  # M680X HD6301/3 mode
+  MODE_M680X_6309 = (1 << 2)  # M680X HD6309 mode
+  MODE_M680X_6800 = (1 << 3)  # M680X M6800/2 mode
+  MODE_M680X_6801 = (1 << 4)  # M680X M6801/3 mode
+  MODE_M680X_6805 = (1 << 5)  # M680X M6805 mode
+  MODE_M680X_6808 = (1 << 6)  # M680X M68HC08 mode
+  MODE_M680X_6809 = (1 << 7)  # M680X M6809 mode
+  MODE_M680X_6811 = (1 << 8)  # M680X M68HC11 mode
+  MODE_M680X_CPU12 = (1 << 9) # M680X CPU12 mode
+  MODE_M680X_HCS08 = (1 << 10) # M680X HCS08 mode
+
+  OPT_SYNTAX = 1    # Intel X86 asm syntax (ARCH_X86 arch)
+  OPT_DETAIL = 2    # Break down instruction structure into details
+  OPT_MODE = 3      # Change engine's mode at run-time
+  OPT_MEM = 4       # Change engine's mode at run-time
+  OPT_SKIPDATA = 5  # Skip data when disassembling
+  OPT_SKIPDATA_SETUP = 6 # Setup user-defined function for SKIPDATA option
+  OPT_MNEMONIC = 7  # Customize instruction mnemonic
+  OPT_UNSIGNED = 8  # Print immediate in unsigned form
+
+  OPT_OFF = 0             # Turn OFF an option - default option of OPT_DETAIL
+  OPT_ON = 3              # Turn ON an option (OPT_DETAIL)
+
+  OP_INVALID = 0
+  OP_REG = 1
+  OP_IMM = 2
+  OP_MEM = 3
+  OP_FP  = 4
+
+  GRP_INVALID = 0  # uninitialized/invalid group.
+  GRP_JUMP    = 1  # all jump instructions (conditional+direct+indirect jumps)
+  GRP_CALL    = 2  # all call instructions
+  GRP_RET     = 3  # all return instructions
+  GRP_INT     = 4  # all interrupt instructions (int+syscall)
+  GRP_IRET    = 5  # all interrupt return instructions
+  GRP_PRIVILEGE = 6 # all privileged instructions
+
+  AC_INVALID  = 0        # Invalid/unitialized access type.
+  AC_READ     = (1 << 0) # Operand that is read from.
+  AC_WRITE    = (1 << 1) # Operand that is written to.
+
+  OPT_SYNTAX_DEFAULT = 0 # Default assembly syntax of all platforms (OPT_SYNTAX)
+  OPT_SYNTAX_INTEL = 1    # Intel X86 asm syntax - default syntax on X86 (OPT_SYNTAX, ARCH_X86)
+  OPT_SYNTAX_ATT = 2      # ATT asm syntax (OPT_SYNTAX, ARCH_X86)
+  OPT_SYNTAX_NOREGNAME = 3 # Asm syntax prints register name with only number - (OPT_SYNTAX, ARCH_PPC, ARCH_ARM)
+  OPT_SYNTAX_MASM = 4 # MASM syntax (OPT_SYNTAX, ARCH_X86)
+
+  ERR_OK = 0      # No error: everything was fine
+  ERR_MEM = 1     # Out-Of-Memory error: cs_open(), cs_disasm()
+  ERR_ARCH = 2    # Unsupported architecture: cs_open()
+  ERR_HANDLE = 3  # Invalid handle: cs_op_count(), cs_op_index()
+  ERR_CSH = 4     # Invalid csh argument: cs_close(), cs_errno(), cs_option()
+  ERR_MODE = 5    # Invalid/unsupported mode: cs_open()
+  ERR_OPTION = 6  # Invalid/unsupported option: cs_option()
+  ERR_DETAIL = 7  # Invalid/unsupported option: cs_option()
+  ERR_MEMSETUP = 8
+  ERR_VERSION = 9 # Unsupported version (bindings)
+  ERR_DIET = 10   # Information irrelevant in diet engine
+  ERR_SKIPDATA = 11 # Access irrelevant data for "data" instruction in SKIPDATA mode
+  ERR_X86_ATT = 12 # X86 AT&T syntax is unsupported (opt-out at compile time)
+  ERR_X86_INTEL = 13 # X86 Intel syntax is unsupported (opt-out at compile time)
+  ERR_X86_MASM = 14 # X86 Intel syntax is unsupported (opt-out at compile time)
+
+  SUPPORT_DIET = ARCH_ALL + 1
+  SUPPORT_X86_REDUCE = ARCH_ALL + 2
+end

data/lib/crabstone/arch/5/arm.rb

@@ -0,0 +1,111 @@
+# frozen_string_literal: true
+
+# THIS FILE WAS AUTO-GENERATED -- DO NOT EDIT!
+
+require 'ffi'
+
+require 'crabstone/arch/extension'
+require_relative 'arm_const'
+
+module Crabstone
+  module ARM
+    class OperandShift < FFI::Struct
+      layout(
+        :type, :uint,
+        :value, :uint
+      )
+    end
+
+    class OperandMemory < FFI::Struct
+      layout(
+        :base, :uint,
+        :index, :uint,
+        :scale, :int,
+        :disp, :int,
+        :lshift, :int
+      )
+    end
+
+    class OperandValue < FFI::Union
+      layout(
+        :reg, :uint,
+        :imm, :int,
+        :fp, :double,
+        :mem, OperandMemory,
+        :setend, :int
+      )
+    end
+
+    class Operand < FFI::Struct
+      layout(
+        :vector_index, :int,
+        :shift, OperandShift,
+        :type, :uint,
+        :value, OperandValue,
+        :subtracted, :bool,
+        :access, :uint8,
+        :neon_lane, :int8
+      )
+
+      include Crabstone::Extension::Operand
+
+      def reg?
+        [
+          OP_REG,
+          OP_SYSREG
+        ].include?(self[:type])
+      end
+
+      def imm?
+        [
+          OP_IMM,
+          OP_CIMM,
+          OP_PIMM
+        ].include?(self[:type])
+      end
+
+      def mem?
+        self[:type] == OP_MEM
+      end
+
+      def fp?
+        self[:type] == OP_FP
+      end
+
+      def cimm?
+        self[:type] == OP_CIMM
+      end
+
+      def pimm?
+        self[:type] == OP_PIMM
+      end
+
+      def setend?
+        self[:type] == OP_SETEND
+      end
+
+      def sysreg?
+        self[:type] == OP_SYSREG
+      end
+    end
+
+    class Instruction < FFI::Struct
+      layout(
+        :usermode, :bool,
+        :vector_size, :int,
+        :vector_data, :int,
+        :cps_mode, :int,
+        :cps_flag, :int,
+        :cc, :uint,
+        :update_flags, :bool,
+        :writeback, :bool,
+        :post_index, :bool,
+        :mem_barrier, :int,
+        :op_count, :uint8,
+        :operands, [Operand, 36]
+      )
+
+      include Crabstone::Extension::Instruction
+    end
+  end
+end

data/lib/crabstone/arch/5/arm64.rb

@@ -0,0 +1,131 @@
+# frozen_string_literal: true
+
+# THIS FILE WAS AUTO-GENERATED -- DO NOT EDIT!
+
+require 'ffi'
+
+require 'crabstone/arch/extension'
+require_relative 'arm64_const'
+
+module Crabstone
+  module ARM64
+    class OperandShift < FFI::Struct
+      layout(
+        :type, :uint,
+        :value, :uint
+      )
+    end
+
+    class OperandMemory < FFI::Struct
+      layout(
+        :base, :uint,
+        :index, :uint,
+        :disp, :int
+      )
+    end
+
+    class OperandSmeIndex < FFI::Struct
+      layout(
+        :reg, :uint,
+        :base, :uint,
+        :disp, :int
+      )
+    end
+
+    class OperandValue < FFI::Union
+      layout(
+        :reg, :uint,
+        :imm, :long,
+        :fp, :double,
+        :mem, OperandMemory,
+        :pstate, :int,
+        :sys, :uint,
+        :prefetch, :int,
+        :barrier, :int,
+        :sme_index, OperandSmeIndex
+      )
+    end
+
+    class Operand < FFI::Struct
+      layout(
+        :vector_index, :int,
+        :vas, :int,
+        :shift, OperandShift,
+        :ext, :uint,
+        :type, :uint,
+        :svcr, :uint,
+        :value, OperandValue,
+        :access, :uint8
+      )
+      def shift?
+        self[:shift][:type] != SFT_INVALID
+      end
+
+      def ext?
+        self[:ext] != EXT_INVALID
+      end
+
+      include Crabstone::Extension::Operand
+
+      def reg?
+        self[:type] == OP_REG
+      end
+
+      def imm?
+        [
+          OP_IMM,
+          OP_CIMM
+        ].include?(self[:type])
+      end
+
+      def mem?
+        self[:type] == OP_MEM
+      end
+
+      def fp?
+        self[:type] == OP_FP
+      end
+
+      def cimm?
+        self[:type] == OP_CIMM
+      end
+
+      def pstate?
+        self[:type] == OP_PSTATE
+      end
+
+      def sys?
+        self[:type] == OP_SYS
+      end
+
+      def svcr?
+        self[:type] == OP_SVCR
+      end
+
+      def prefetch?
+        self[:type] == OP_PREFETCH
+      end
+
+      def barrier?
+        self[:type] == OP_BARRIER
+      end
+
+      def sme_index?
+        self[:type] == OP_SME_INDEX
+      end
+    end
+
+    class Instruction < FFI::Struct
+      layout(
+        :cc, :uint,
+        :update_flags, :bool,
+        :writeback, :bool,
+        :post_index, :bool,
+        :op_count, :uint8,
+        :operands, [Operand, 8]
+      )
+
+      include Crabstone::Extension::Instruction
+    end
+  end
+end