badline 0.17.0 → 0.18.0

data/lib/badline/drives/model8050.rb

@@ -10,6 +10,8 @@ require "badline/drives/model8050/parts"
 require "badline/drives/model8050/ieee_port"
 require "badline/drives/model8050/disk"
 require "badline/drives/model8050/mechanism"
+require "badline/drives/model8050/dos_board"
+require "badline/drives/model8050/board"
 require "badline/drives/model8050/idle"
 require "badline/drives/model8050/keyed_state"
 
@@ -18,25 +20,21 @@ module Badline
     # The 8050 dual disk drive of the PET and CBM-II, two drives on one
     # IEEE-488 unit (schematic 8050001; the 8050/8250 service manual).
     #
-    # Two 6502s share the board, clocked at 1 MHz from one 12 MHz crystal
-    # on opposite phases. The interface processor (IP) runs DOS 2.7 from
-    # 16 KB of ROM at $C000, with two 6532s (IPBus): their RAM is its zero
-    # page and stack, and their ports face the IEEE-488 bus (IEEEPort). The
-    # floppy controller (FDC) runs the 1 KB program in its 6530's ROM, with
-    # a VIA and the 6530 facing the drives (FDCBus, Mechanism). The two
-    # meet in 4 KB of common RAM, which each reaches in its own half of
-    # the cycle: the IP leaves jobs there, and the FDC runs them.
+    # Two 6502s share the board (Board), clocked at 1 MHz from one 12 MHz
+    # crystal on opposite phases. The interface processor (IP) runs DOS 2.7
+    # from 16 KB of ROM at $C000, with two 6532s (IPBus): their RAM is its
+    # zero page and stack, and their ports face the IEEE-488 bus
+    # (IEEEPort). The floppy controller (FDC) runs the 1 KB program in its
+    # 6530's ROM, with a VIA and the 6530 facing the drives (FDCBus,
+    # Mechanism). The two meet in 4 KB of common RAM, which each reaches in
+    # its own half of the cycle: the IP leaves jobs there, and the FDC runs
+    # them.
     #
     # Reset starts both. The FDC waits on the common RAM for the IP, which
     # tests it, copies the FDC's start-up code into it ($C370) and waits for
     # the FDC to answer, before both settle into their idle loops.
-    #
-    # The drive clocks against the host through a phase accumulator, as
-    # Drives::Engine::Core does: each host cycle adds 1 MHz of phase, and
-    # every whole host period in it runs a cycle of both processors. While
-    # both processors idle, it sleeps instead (Idle), and the readers of its
-    # parts catch it up first.
     class Model8050
+      include Board
       include Idle
 
       CLOCK_HZ = 1_000_000
@@ -45,37 +43,10 @@ module Badline
       # run the IP's RAM test and the FDC's start-up and reads its jumpers.
       BOOT_CYCLES = 1_500_000
 
-      attr_reader :device, :ieee_bus
-
-      def ip_cpu = settled(@ip_cpu)
-
-      def fdc_cpu = settled(@fdc_cpu)
-
-      def ip_bus = settled(@ip_bus)
-
-      def fdc_bus = settled(@fdc_bus)
-
-      def common = settled(@common)
-
-      def data_riot = settled(@data_riot)
-
-      def control_riot = settled(@control_riot)
-
-      def via = settled(@via)
-
-      def rriot = settled(@rriot)
-
-      def mechanism = settled(@mechanism)
-
-      def cycles
-        settle!
-        @cycles
-      end
-
-      attr_writer :host_clock_hz
-
       def model_name = "8050"
 
+      def boot_cycles = BOOT_CYCLES
+
       # The sides each drive's disk has.
       def sides = 1
 
@@ -91,39 +62,10 @@ module Badline
         build_fdc(fdc_rom || ROM.read("8050/fdc-901869-01.rom"))
         @ip_cpu = IPCPU.new(@ip_bus)
         @fdc_cpu = FDCCPU.new(@fdc_bus)
-        init_idle
+        init_idle(Idle::IP_LOOP, Idle::FDC_LOOP)
         @ieee_bus.attach(self)
       end
 
-      # Plugs the unit into an IEEE-488 bus, leaving the one it was on.
-      def connect(ieee_bus)
-        settle!
-        @ieee_bus.detach(self)
-        @ieee_bus = ieee_bus
-        @ieee_port.bus = ieee_bus
-        ieee_bus.attach(self)
-      end
-
-      # The lines the unit pulls on the bus while ATN is low or not
-      # (IEEEPort).
-      def ieee_low_lines(atn) = @ieee_port.ieee_low_lines(atn)
-
-      # The controller pushed its lines into the bus.
-      def host_written! = nil
-
-      # Which LEDs are lit: bit 0 drive 1's, bit 1 drive 0's, bit 2 the
-      # error LED. They hold still while the unit sleeps, so reading them
-      # leaves it asleep.
-      def leds = @ieee_port.leds
-
-      def led_on? = leds.anybits?(0x03)
-
-      # Puts a Disk in +drive+, 0 or 1. Nil takes the disk out.
-      def insert(disk, drive: 0)
-        settle!
-        @mechanism.insert(disk, drive)
-      end
-
       # Puts in the .d80 or .d82 image at +path+, write-protected with
       # `read_only`.
       def insert_image(path, drive: 0, read_only: false)
@@ -131,65 +73,8 @@ module Badline
         insert(Disk.new(image_class.new(path, read_only:)), drive:)
       end
 
-      # The Disk in +drive+, or nil.
-      def disk(drive = 0) = @mechanism.disk(drive)
-
-      # Stores what the heads wrote in the disks' images, as the motors
-      # stopping do.
-      def flush
-        settle!
-        @mechanism.flush
-      end
-
-      def power_led_on? = true
-
-      # Runs the drive cycles that fall in one host cycle, then takes the
-      # controller's lines for the next. Asleep, the unit owes the cycles
-      # instead, and wakes once the controller has moved a line.
-      def host_cycle!
-        phase = @phase + CLOCK_HZ
-        while phase >= @host_clock_hz
-          @asleep ? owe_cycle : run_cycle
-          phase -= @host_clock_hz
-        end
-        @phase = phase
-        settle! if @asleep && @ieee_port.lines_moved?
-        @ieee_port.latch_host
-      end
-
-      def cycle!
-        settle!
-        run_cycle
-      end
-
-      # The bus's IFC line resets both processors and every chip. RAM keeps
-      # its contents.
-      def reset!
-        settle!
-        @data_riot.reset!
-        @control_riot.reset!
-        @via.reset!
-        @rriot.reset!
-        @ip_cpu.reset!
-        @fdc_cpu.reset!
-      end
-
-      def inspect
-        "#<#{self.class.name} cycles=#{@cycles} ip=(#{@ip_cpu.inspect}) fdc=(#{@fdc_cpu.inspect})>"
-      end
-
       private
 
-      def settled(part)
-        settle!
-        part
-      end
-
-      def run_cycle
-        step
-        watch_loops if @idle_skip
-      end
-
       def build_ip(rom)
         @common = Memory.new([], length: 0x1000)
         @ieee_bus = IEEEBus.new
@@ -210,6 +95,9 @@ module Badline
         @mechanism.rriot = @rriot
       end
 
+      # The disk a BL-D8-DISK module holds (KeyedState).
+      def disk_from_fields(input, detached) = Disk.from_fields(input, detached:)
+
       # One cycle of the board: the drives, then the chips, then the IP and
       # the FDC, each in its own half of the cycle. ATN reaches UE1's PA7 as
       # the port latched it. UE1 pulls the IP's IRQ, and the VIA and the

data/lib/badline/drives/model9060/idle.rb

@@ -0,0 +1,149 @@
+# frozen_string_literal: true
+
+module Badline
+  module Drives
+    class Model9060
+      # Sleeping through the two processors' idle loops, exactly, as
+      # Model8050::Idle does.
+      #
+      # With nothing to do, the IP goes round DOS 3.0's idle loop from
+      # IP_LOOP, and the SASI host round its job loop from SASI_LOOP, each
+      # pass finding the job queue empty, until ATN interrupts the IP. The
+      # host has no interrupt of its own. A pass puts back what it found, so
+      # each processor comes back to its loop's start as it left it.
+      #
+      # Each time a processor comes to its loop's start, the unit compares
+      # what that processor sees with what it saw last time round: the CPU,
+      # its chips but for their counters, its RAM and the common RAM. The
+      # same, with no read of a counter or an interrupt flag between, makes
+      # the pass repeatable. Once both are, with the hard disk's controller
+      # idle and no interrupt pulled, the unit sleeps until a counter is due
+      # to pull IRQ, the IEEE-488 controller moves a line, or something
+      # outside reads or changes the unit (settle!).
+      module Idle
+        IP_LOOP = 0xc131
+        SASI_LOOP = 0xf8f1
+
+        # Whether the unit may sleep through its idle loops.
+        attr_reader :idle_skip
+
+        def idle_skip=(on)
+          settle!
+          @idle_skip = on
+        end
+
+        def asleep? = @asleep
+
+        # Brings the unit up to the present, cycle for cycle, and drops the
+        # passes it found, since whoever called may change it.
+        def settle!
+          wake! if @asleep
+          forget_passes
+        end
+
+        private
+
+        def init_idle
+          @idle_skip = true
+          @asleep = false
+          @owed = 0
+          @budget = 0
+          forget_passes
+        end
+
+        def forget_passes
+          @ip_mark = nil
+          @sasi_mark = nil
+          @ip_pass = nil
+          @sasi_pass = nil
+        end
+
+        def owe_cycle
+          @owed += 1
+          wake! if @owed >= @budget
+        end
+
+        def watch_loops
+          ip = @ip_cpu
+          @ip_pass = nil if ip.irq
+          @sasi_pass = nil if @sasi_cpu.irq
+          ip_pass_found if ip.program_counter == IP_LOOP && ip.boundary?
+          host = @sasi_cpu
+          sasi_pass_found if host.program_counter == SASI_LOOP && host.boundary?
+        end
+
+        def ip_pass_found
+          state = ip_state
+          @ip_pass = repeated(@ip_mark, state, @ip_cpu, @ip_bus.volatile)
+          @ip_mark = [state, @ip_cpu.cycles, @ip_cpu.instructions]
+          @ip_bus.volatile = false
+          fall_asleep if @ip_pass && @sasi_pass
+        end
+
+        def sasi_pass_found
+          state = sasi_state
+          @sasi_pass = repeated(@sasi_mark, state, @sasi_cpu, @sasi_bus.volatile)
+          @sasi_mark = [state, @sasi_cpu.cycles, @sasi_cpu.instructions]
+          @sasi_bus.volatile = false
+          fall_asleep if @ip_pass && @sasi_pass
+        end
+
+        def repeated(mark, state, cpu, volatile)
+          return nil if mark.nil? || volatile || mark[0] != state
+
+          [cpu.cycles - mark[1], cpu.instructions - mark[2]]
+        end
+
+        def fall_asleep
+          target = @target
+          return unless target.quiet? && !target.busy? && !@ip_cpu.irq && !@sasi_cpu.irq
+
+          budget = quiet_cycles
+          return if budget < 2
+
+          @asleep = true
+          @owed = 0
+          @budget = budget
+        end
+
+        def quiet_cycles
+          [@data_riot.quiet_cycles, @control_riot.quiet_cycles, @via.quiet_cycles].min
+        end
+
+        def wake!
+          owed = @owed
+          @asleep = false
+          @owed = 0
+          return if owed.zero?
+
+          @data_riot.fast_forward(owed)
+          @control_riot.fast_forward(owed)
+          @via.fast_forward(owed)
+          @target.fast_forward(owed)
+          skip(@ip_cpu, @ip_pass, @ip_mark, owed)
+          skip(@sasi_cpu, @sasi_pass, @sasi_mark, owed)
+          @cycles += owed
+        end
+
+        def skip(cpu, pass, mark, owed)
+          passes = owed / pass[0]
+          cpu.fast_forward(passes * pass[0], passes * pass[1])
+          mark[1] += passes * pass[0]
+          mark[2] += passes * pass[1]
+          (owed - (passes * pass[0])).times { cpu.cycle! }
+        end
+
+        def ip_state
+          [*@ip_cpu.idle_state, *@data_riot.idle_state, *@control_riot.idle_state, @ip_bus.data, common_changes]
+        end
+
+        def sasi_state
+          [*@sasi_cpu.idle_state, *@via.idle_state, *@lines.state, *@sasi_bus.ram.read(0, 0x80), @sasi_bus.data,
+           common_changes]
+        end
+
+        def common_changes = @ip_bus.common_changes + @sasi_bus.common_changes
+      end
+    end
+  end
+end

data/lib/badline/drives/model9060/keyed_state.rb

@@ -0,0 +1,123 @@
+# frozen_string_literal: true
+
+module Badline
+  module Drives
+    class Model9060
+      class SASITarget
+        # The controller's fields in a keyed snapshot module (BL-D8-SASI):
+        # the bus phase, REQ, the cycles left to the next, the command, the
+        # bytes of the phase and the place in them, the write under way,
+        # the sense bytes, the fast mode, its clock, the heads' cylinder, the
+        # geometry and the block buffer, then the image's path and how it
+        # was opened. The image itself stays in its file, which each write
+        # reached as it ended.
+        module KeyedState
+          def save_fields(out)
+            out.int("phase", @phase).bool("request", @request).int("delay", @delay)
+            out.ints("command", @command).ints("buffer", @buffer).int("index", @index)
+            out.bool("writing", @writing).ints("sense", @sense).ints("last_sense", @last_sense)
+            out.bool("fast", @fast).int("cycle", @cycle).int("cylinder", @cylinder)
+            out.int("heads", @heads).int("sectors", @sectors).ints("block_buffer", @block_buffer)
+            disk = @disk
+            out.text("path", disk.nil? ? "" : disk.path.to_s).bool("read_only", disk.nil? || disk.read_only?)
+            out.int("disk_heads", disk.nil? ? 0 : disk.heads)
+          end
+
+          # A detached reader, or a host file that is gone, leaves the drive
+          # empty.
+          def load_fields(input, detached: false)
+            load_bus_fields(input)
+            path = input.text("path", "")
+            read_only = input.bool("read_only", false)
+            heads = input.int("disk_heads", 4)
+            @disk = detached || !File.file?(path) ? nil : Storage::D90Image.new(path, read_only:, heads:)
+          end
+
+          private
+
+          def load_bus_fields(input)
+            @phase = input.int("phase", @phase)
+            @request = input.bool("request", @request)
+            @delay = input.int("delay", @delay)
+            @command = input.ints("command", @command).dup
+            @buffer = input.ints("buffer", @buffer).dup
+            @index = input.int("index", @index)
+            @writing = input.bool("writing", @writing)
+            @sense = input.ints("sense", @sense).dup
+            @last_sense = input.ints("last_sense", @last_sense).dup
+            @fast = input.bool("fast", @fast)
+            @cycle = input.int("cycle", @cycle)
+            @cylinder = input.int("cylinder", @cylinder)
+            @heads = input.int("heads", @heads)
+            @sectors = input.int("sectors", @sectors)
+            @block_buffer = input.ints("block_buffer", @block_buffer).dup
+          end
+        end
+
+        include KeyedState
+      end
+
+      # The unit's own fields in a keyed snapshot module (BL-D8): its model,
+      # its clock phase and cycle count, each bus's last byte, the
+      # controller's lines as the port latched them, under ieee.*, and the
+      # SASI lines' ACK and RST levels. A save settles the unit first, so it
+      # is awake; a load finds its passes afresh.
+      module KeyedState
+        def save_fields(out)
+          settle!
+          out.text("model", model_name).int("phase", @phase).int("cycles", @cycles)
+          out.int("ip_data", @ip_bus.data).int("sasi_data", @sasi_bus.data)
+          out.int("ieee.host", @ieee_port.host)
+          ack_high, reset_high = @lines.state
+          out.bool("sasi.ack_high", ack_high).bool("sasi.reset_high", reset_high)
+          out
+        end
+
+        def load_fields(input)
+          settle!
+          input.choice("model", [model_name], model_name)
+          @phase = input.int("phase", @phase)
+          @cycles = input.int("cycles", @cycles)
+          @ip_bus.data = input.byte("ip_data", @ip_bus.data)
+          @sasi_bus.data = input.byte("sasi_data", @sasi_bus.data)
+          @ieee_port.host = input.int("ieee.host", @ieee_port.host)
+          @lines.state = [input.bool("sasi.ack_high", true), input.bool("sasi.reset_high", false)]
+        end
+
+        # The unit as modules of its own, named from `name` (BL-D8 for
+        # device 8): its own fields, the common RAM, UC1 and UE1 with their
+        # RAM, each processor, the host's RAM and VIA, and the hard disk's
+        # controller.
+        def save_modules(sections, name)
+          sections << Snapshot::Keyed.section(name) { |out| save_fields(out) }
+          sections << Snapshot::Keyed.section("#{name}-COMMON") { |out| @common.save_fields(out, "ram") }
+          sections << Snapshot::Keyed.section("#{name}-RIOT1") { |out| @data_riot.save_fields(out) }
+          sections << Snapshot::Keyed.section("#{name}-RIOT2") { |out| @control_riot.save_fields(out) }
+          sections << Snapshot::Keyed.section("#{name}-IPCPU") { |out| @ip_cpu.save_fields(out) }
+          sections << Snapshot::Keyed.section("#{name}-SASICPU") { |out| @sasi_cpu.save_fields(out) }
+          sections << Snapshot::Keyed.section("#{name}-SASIRAM") { |out| @sasi_bus.ram.save_fields(out, "ram") }
+          sections << Snapshot::Keyed.section("#{name}-VIA") { |out| @via.save_fields(out) }
+          sections << Snapshot::Keyed.section("#{name}-SASI") { |out| @target.save_fields(out) }
+        end
+
+        # The unit from its modules, `input` being its own.
+        def load_modules(modules, input, name)
+          load_fields(input)
+          @common.load_fields(modules.required("#{name}-COMMON"), "ram")
+          @data_riot.load_fields(modules.required("#{name}-RIOT1"))
+          @control_riot.load_fields(modules.required("#{name}-RIOT2"))
+          @ip_cpu.load_fields(modules.required("#{name}-IPCPU"))
+          @sasi_cpu.load_fields(modules.required("#{name}-SASICPU"))
+          @sasi_bus.ram.load_fields(modules.required("#{name}-SASIRAM"), "ram")
+          @via.load_fields(modules.required("#{name}-VIA"))
+          @target.load_fields(modules.required("#{name}-SASI"), detached: modules.detached?)
+          @via.restored!
+          @ip_cpu.restored!
+          @sasi_cpu.restored!
+        end
+      end
+
+      include KeyedState
+    end
+  end
+end

data/lib/badline/drives/model9060/parts.rb

@@ -0,0 +1,98 @@
+# frozen_string_literal: true
+
+module Badline
+  module Drives
+    class Model9060
+      # The SASI host's VIA, at $0080, a class of its own so it keeps one
+      # type of peripheral.
+      class SASIVIA < Chips::VIA
+      end
+
+      # The SASI host's 6502, on the SASIBus.
+      class SASICPU
+        include Badline::Chips::CPU::Core
+        include Engine::IdleCPU
+      end
+
+      # The VIA's lines to the controller (SASITarget), on the board's
+      # transceivers:
+      #
+      #   PA0-7  the data bus             PB0  SEL out
+      #   CA1    REQ, rising as it rises  PB1  RST out
+      #   CA2    ACK, pulsed on each      PB2  C/D in
+      #          read or write of ORA     PB3  BSY in
+      #   CB2    the transceivers'        PB4  jumper J14: high for four
+      #          direction                     heads (D9060), low for six
+      #                                   PB6  I/O in
+      #                                   PB7  MSG in
+      #
+      # The ports read and drive each line high while it is asserted, SEL
+      # and RST only while PB0 and PB1 are outputs.
+      # SEL raised selects the controller with the data bus as the host
+      # drives it, and RST raised resets it. ACK falling hands it the byte
+      # on the data bus.
+      class SASILines
+        SEL = 0x01
+        RST = 0x02
+        CD = 0x04
+        BSY = 0x08
+        J14 = 0x10
+        IO = 0x40
+        MSG = 0x80
+
+        attr_reader :target
+        attr_writer :via
+
+        # `four_heads` is J14.
+        def initialize(target, four_heads:)
+          @target = target
+          @four_heads = four_heads
+          @via = nil
+          @ack_high = true
+          @reset_high = false
+        end
+
+        # The data bus: the controller's byte while it drives it.
+        def read_a(_lines)
+          target = @target
+          target.input? ? target.data : 0xff
+        end
+
+        def read_b(_lines)
+          target = @target
+          value = 0x23
+          value |= CD if target.control?
+          value |= BSY if target.busy?
+          value |= J14 if @four_heads
+          value |= IO if target.input?
+          value |= MSG if target.message?
+          value
+        end
+
+        # One cycle of the controller, then the host's ACK, RST and SEL to
+        # the controller, and REQ to CA1.
+        def cycle!
+          target = @target
+          via = @via
+          target.clock
+          ack_high = via.ca2_output
+          target.acknowledge(via.port_a_output) if @ack_high && !ack_high
+          @ack_high = ack_high
+          host = via.port_b_output & via.peek(0x82)
+          reset_high = host.anybits?(RST)
+          target.reset if reset_high && !@reset_high
+          @reset_high = reset_high
+          target.select(via.port_a_output) if host.anybits?(SEL)
+          via.ca1 = target.request?
+        end
+
+        # Everything the lines hold between cycles.
+        def state = [@ack_high, @reset_high]
+
+        def state=(values)
+          @ack_high, @reset_high = values
+        end
+      end
+    end
+  end
+end

data/lib/badline/drives/model9060/sasi_bus.rb

@@ -0,0 +1,88 @@
+# frozen_string_literal: true
+
+module Badline
+  module Drives
+    class Model9060
+      # The SASI host processor's bus on the DOS board (300010), where the
+      # 8050's floppy controller sits, with its decode and common RAM:
+      #
+      # $0000-$007F - the 6810's 128 bytes, mirrored at $0100 for the stack
+      # $0080-$008F - the VIA (SASILines)
+      # $0400-$13FF - the common RAM, 1 KB in each of the 8050's windows
+      # $F800-$FFFF - 300515, the host's program
+      #
+      # Writes to the ROM and to open bus go nowhere, and a read from open
+      # bus finds the last byte on the data bus.
+      class SASIBus
+        include Addressable
+
+        attr_reader :common, :ram, :via
+        attr_accessor :data
+
+        # How many writes have changed a byte of the common RAM
+        # (Model9060::Idle).
+        attr_reader :common_changes
+
+        # Whether a counter or an interrupt flag has been read since it was
+        # last cleared (Model9060::Idle).
+        attr_accessor :volatile
+
+        def initialize(rom:, common:, via:)
+          addressable_at(0, length: 2**16)
+          @rom = rom
+          @common = common
+          @via = via
+          @ram = Memory.new([], length: 0x80)
+          @data = 0
+          @volatile = false
+          @common_changes = 0
+        end
+
+        def peek(addr)
+          @data = if addr >= 0xf800
+                    @rom.peek(addr & 0x07ff)
+                  elsif addr < 0x0200
+                    peek_low(addr)
+                  elsif addr.between?(0x0400, 0x13ff)
+                    @common.peek(addr - 0x0400)
+                  else
+                    @data
+                  end
+        end
+
+        def poke(addr, value)
+          @data = value
+          if addr < 0x0200
+            poke_low(addr, value)
+          elsif addr.between?(0x0400, 0x13ff)
+            poke_common(addr - 0x0400, value)
+          end
+        end
+
+        private
+
+        def peek_low(addr)
+          return @ram.peek(addr & 0x7f) if addr.nobits?(0x80)
+          return @data if addr.anybits?(0x70)
+
+          register = addr & 0x0f
+          @volatile = true if register.between?(0x04, 0x0a) || register == 0x0d
+          @via.peek(0x80 | register)
+        end
+
+        def poke_low(addr, value)
+          if addr.nobits?(0x80)
+            @ram.poke(addr & 0x7f, value)
+          elsif addr.nobits?(0x70)
+            @via.poke(0x80 | (addr & 0x0f), value)
+          end
+        end
+
+        def poke_common(index, value)
+          @common_changes += 1 if @common.peek(index) != value
+          @common.poke(index, value)
+        end
+      end
+    end
+  end
+end