badline 0.17.0 → 0.18.0

data/lib/badline/cbm2/keyed_state.rb

@@ -71,7 +71,9 @@ module Badline
         out.int("refresh", @refresh)
         pending = @pending_keys
         out.ints("host.pending_keys", pending) if pending
+        save_init_keys(out)
         out.int("host.init_pending", @cycles <= @init_threshold ? @init_handlers.length : 0)
+        save_ieee_drive_fields(out)
       end
 
       def load_machine_fields(input)
@@ -82,7 +84,9 @@ module Badline
         @refresh = input.int("refresh", 0).clamp(0, REFRESH_COUNT)
         pending = input.ints("host.pending_keys", [])
         @pending_keys = pending.empty? ? nil : pending.dup
+        load_init_keys(input)
         @init_handlers_lost = [input.int("host.init_pending", 0) - @init_handlers.length, 0].max
+        load_ieee_drive_fields(input)
       end
     end
 

data/lib/badline/cbm2/p500.rb

@@ -71,8 +71,9 @@ module Badline
       def region = @model.region
 
       # +model+ names one of Model::ALL, and +mains_hz+ the mains, 50 or
-      # 60, the model's region's unless given.
-      def initialize(model: Model::DEFAULT, mains_hz: nil, debug: false)
+      # 60, the model's region's unless given. +true_drive_model+ names the
+      # drive plug_true_drive plugs in (Drives::IEEEModels).
+      def initialize(model: Model::DEFAULT, mains_hz: nil, debug: false, true_drive_model: Drives::IEEEModels::DEFAULT)
         @model = Model.named(model)
         @mains_hz = mains_hz || @model.region.mains_hz
         raise ArgumentError, "the mains is 50 or 60 Hz, not #{@mains_hz}" unless [50, 60].include?(@mains_hz)
@@ -112,10 +113,11 @@ module Badline
         @acia_due = Chips::ACIA::NEVER
         @init_handlers = []
         @pending_keys = nil
+        @init_keys = nil
         @dos = nil
         @ieee_trap = nil
         @capture_output = nil
-        init_ieee_drives
+        init_ieee_drives(true_drive_model)
         @init_threshold = INIT_THRESHOLD
         update_video_bus
       end

data/lib/badline/cbm2.rb

@@ -94,8 +94,10 @@ module Badline
     # +model+ names one of Model::ALL, +kernal+ one of Model::KERNALS, and
     # +mains_hz+ the mains, 50 or 60, which also sets a 600's jumper for
     # the editor's 60 Hz CRTC table. +refresh+ false leaves out the DRAM
-    # refresh's stolen cycles.
-    def initialize(model: Model::DEFAULT, kernal: "04a", mains_hz: 50, refresh: true, debug: false)
+    # refresh's stolen cycles. +true_drive_model+ names the drive
+    # plug_true_drive plugs in (Drives::IEEEModels).
+    def initialize(model: Model::DEFAULT, kernal: "04a", mains_hz: 50, refresh: true, debug: false,
+                   true_drive_model: Drives::IEEEModels::DEFAULT)
       @model = Model.named(model)
       raise ArgumentError, "no CBM-II KERNAL named #{kernal}" unless Model::KERNALS.key?(kernal)
       raise ArgumentError, "the mains is 50 or 60 Hz, not #{mains_hz}" unless [50, 60].include?(mains_hz)
@@ -131,10 +133,11 @@ module Badline
       @acia_due = Chips::ACIA::NEVER
       @init_handlers = []
       @pending_keys = nil
+      @init_keys = nil
       @dos = nil
       @ieee_trap = nil
       @capture_output = nil
-      init_ieee_drives
+      init_ieee_drives(true_drive_model)
       @init_threshold = boot_cycles
     end
 

data/lib/badline/chips/cia/timer.rb

@@ -52,7 +52,7 @@ module Badline
         end
 
         def cycle!(feed)
-          feed &&= @control.value & 0x01 != 0
+          feed &&= @control.value.anybits?(0x01)
           if @settled
             return @counter -= 1 if feed && @counter > 1
           elsif @empty
@@ -102,7 +102,7 @@ module Badline
         private
 
         def started?
-          @control.value & 0x01 != 0
+          @control.value.anybits?(0x01)
         end
 
         # Where fast_forward lands +cycles+ after an underflow, with

data/lib/badline/chips/cpu/instruction_set.rb

@@ -40,7 +40,7 @@ module Badline
 
         def update_number_flags(value)
           status.zero = value.zero?
-          status.negative = value & 0x80 != 0
+          status.negative = value.anybits?(0x80)
           value
         end
 

data/lib/badline/chips/m6809/arithmetic.rb

@@ -0,0 +1,140 @@
+# frozen_string_literal: true
+
+module Badline
+  module Chips
+    class M6809
+      # The ALU: each method returns its result and sets the flags it
+      # changes.
+      module Arithmetic
+        private
+
+        def flags(clear, set)
+          @cc = (@cc & ~clear & 0xff) | set
+        end
+
+        def nz8(result) = (result.nobits?(0x80) ? 0 : NEGATIVE) | (result.zero? ? ZERO : 0)
+
+        def nz16(result) = (result.nobits?(0x8000) ? 0 : NEGATIVE) | (result.zero? ? ZERO : 0)
+
+        # Loads, stores, AND, OR, EOR and TST: N and Z, V cleared.
+        def logic8(result)
+          flags(NEGATIVE | ZERO | OVERFLOW, nz8(result))
+          result
+        end
+
+        def logic16(result)
+          flags(NEGATIVE | ZERO | OVERFLOW, nz16(result))
+          result
+        end
+
+        def add8(left, right, carry)
+          sum = left + right + carry
+          result = sum & 0xff
+          overflow = ((left ^ result) & (right ^ result)).nobits?(0x80) ? 0 : OVERFLOW
+          half = (left ^ right ^ sum).nobits?(0x10) ? 0 : HALF_CARRY
+          flags(HALF_CARRY | NEGATIVE | ZERO | OVERFLOW | CARRY,
+                half | nz8(result) | overflow | (sum > 0xff ? CARRY : 0))
+          result
+        end
+
+        def sub8(left, right, borrow)
+          difference = left - right - borrow
+          result = difference & 0xff
+          overflow = ((left ^ right) & (left ^ result)).nobits?(0x80) ? 0 : OVERFLOW
+          flags(NEGATIVE | ZERO | OVERFLOW | CARRY, nz8(result) | overflow | (difference.negative? ? CARRY : 0))
+          result
+        end
+
+        def add16(left, right)
+          sum = left + right
+          result = sum & 0xffff
+          @alu_word = result
+          overflow = ((left ^ result) & (right ^ result)).nobits?(0x8000) ? 0 : OVERFLOW
+          flags(NEGATIVE | ZERO | OVERFLOW | CARRY, nz16(result) | overflow | (sum > 0xffff ? CARRY : 0))
+          result
+        end
+
+        def sub16(left, right)
+          difference = left - right
+          result = difference & 0xffff
+          @alu_word = result
+          overflow = ((left ^ right) & (left ^ result)).nobits?(0x8000) ? 0 : OVERFLOW
+          flags(NEGATIVE | ZERO | OVERFLOW | CARRY, nz16(result) | overflow | (difference.negative? ? CARRY : 0))
+          result
+        end
+
+        def carry = @cc & CARRY
+
+        def neg8(value) = sub8(0, value, 0)
+
+        def com8(value)
+          result = ~value & 0xff
+          flags(NEGATIVE | ZERO | OVERFLOW | CARRY, nz8(result) | CARRY)
+          result
+        end
+
+        # The undocumented XNC: NEG with C clear, COM with C set.
+        def xnc8(value) = carry.zero? ? neg8(value) : com8(value)
+
+        def lsr8(value)
+          result = value >> 1
+          flags(NEGATIVE | ZERO | CARRY, nz8(result) | (value & 1))
+          result
+        end
+
+        def ror8(value)
+          result = (value >> 1) | (carry << 7)
+          flags(NEGATIVE | ZERO | CARRY, nz8(result) | (value & 1))
+          result
+        end
+
+        def asr8(value)
+          result = (value >> 1) | (value & 0x80)
+          flags(NEGATIVE | ZERO | CARRY, nz8(result) | (value & 1))
+          result
+        end
+
+        def asl8(value) = rotate_left8(value, 0)
+
+        def rol8(value) = rotate_left8(value, carry)
+
+        def rotate_left8(value, low)
+          result = ((value << 1) | low) & 0xff
+          overflow = (value ^ (value << 1)).nobits?(0x80) ? 0 : OVERFLOW
+          flags(NEGATIVE | ZERO | OVERFLOW | CARRY, nz8(result) | overflow | (value >> 7))
+          result
+        end
+
+        def dec8(value)
+          result = (value - 1) & 0xff
+          flags(NEGATIVE | ZERO | OVERFLOW, nz8(result) | (value == 0x80 ? OVERFLOW : 0))
+          result
+        end
+
+        # The undocumented XDEC: DEC, with C set unless the operand was 0.
+        def xdec8(value)
+          result = dec8(value)
+          flags(CARRY, value.zero? ? 0 : CARRY)
+          result
+        end
+
+        def inc8(value)
+          result = (value + 1) & 0xff
+          flags(NEGATIVE | ZERO | OVERFLOW, nz8(result) | (value == 0x7f ? OVERFLOW : 0))
+          result
+        end
+
+        def clr8
+          flags(NEGATIVE | ZERO | OVERFLOW | CARRY, ZERO)
+          0
+        end
+
+        # The undocumented XCLRA and XCLRB: CLR, but C stays.
+        def xclr8
+          flags(NEGATIVE | ZERO | OVERFLOW, ZERO)
+          0
+        end
+      end
+    end
+  end
+end

data/lib/badline/chips/m6809/bus_steps.rb

@@ -0,0 +1,223 @@
+# frozen_string_literal: true
+
+module Badline
+  module Chips
+    class M6809
+      PREFIX_PLAN = %i[fetch_paged].freeze
+
+      # The steps that fetch opcodes and operands, work out direct and
+      # extended addresses and branch targets, and read and write the
+      # operand, one bus cycle each.
+      module BusSteps
+        private
+
+        def read_pc
+          value = @bus.read(@pc)
+          @pc = (@pc + 1) & 0xffff
+          value
+        end
+
+        def fetch
+          return halted_cycle if @halt_seen
+          return take_interrupt if interrupt_due?
+
+          opcode = read_pc
+          @opcode = opcode
+          case opcode
+          when 0x10
+            @page = PAGE2
+            switch_to(PREFIX_PLAN)
+          when 0x11
+            @page = PAGE3
+            switch_to(PREFIX_PLAN)
+          else start(PAGE1[opcode])
+          end
+        end
+
+        # The opcode after a prefix. A further prefix only costs a cycle.
+        def fetch_paged
+          opcode = read_pc
+          return @index -= 1 if [0x10, 0x11].include?(opcode)
+
+          @opcode = opcode
+          start(@page[opcode])
+        end
+
+        def dead_pc = @bus.read(@pc)
+
+        def dead_pc_next = @bus.read((@pc + 1) & 0xffff)
+
+        def dead_pc_next2 = @bus.read((@pc + 2) & 0xffff)
+
+        def dead_v = @bus.read(0xffff)
+
+        def dead_ea = @bus.read(@ea)
+
+        # A cycle without a bus access.
+        def idle; end
+
+        def dead_pc_exec
+          dead_pc
+          execute
+        end
+
+        # A dead read of the byte after the opcode, which the undocumented
+        # $18 uses.
+        def next_byte_exec
+          @value = @bus.read(@pc)
+          execute
+        end
+
+        def dead_v_exec
+          dead_v
+          execute
+        end
+
+        def direct
+          @ea = (@dp << 8) | read_pc
+        end
+
+        def extended_hi
+          @ea = read_pc << 8
+        end
+
+        def extended_lo
+          @ea |= read_pc
+        end
+
+        def immediate_exec
+          @value = read_pc
+          execute
+        end
+
+        def immediate_hi
+          @value = read_pc << 8
+        end
+
+        def immediate_lo_exec
+          @value |= read_pc
+          execute
+        end
+
+        def immediate_discard = read_pc
+
+        # The undocumented 16-bit stores immediate write the register's low
+        # byte over the operand's.
+        def store_immediate
+          execute
+          @bus.write(@pc, @value)
+          @pc = (@pc + 1) & 0xffff
+        end
+
+        def read_post
+          @post = read_pc
+        end
+
+        def read_exec
+          @value = @bus.read(@ea)
+          execute
+        end
+
+        def read_hi
+          @value = @bus.read(@ea) << 8
+        end
+
+        def read_lo_exec
+          @value |= @bus.read((@ea + 1) & 0xffff)
+          execute
+        end
+
+        def write_exec
+          execute
+          @bus.write(@ea, @value)
+        end
+
+        def write_hi_exec
+          execute
+          @bus.write(@ea, @value >> 8)
+        end
+
+        def write_lo
+          @bus.write((@ea + 1) & 0xffff, @value & 0xff)
+        end
+
+        def rmw_read
+          @value = @bus.read(@ea)
+          execute
+        end
+
+        def rmw_write
+          @bus.write(@ea, @value)
+        end
+
+        # A short branch's offset, and the target it gives.
+        def offset8_branch
+          offset = read_pc
+          @ea = (@pc + offset - ((offset & 0x80) * 2)) & 0xffff
+        end
+
+        def offset_hi
+          @value = read_pc << 8
+        end
+
+        # The low byte of a 16-bit offset from PC, and its target.
+        def offset_lo_pc
+          @value |= read_pc
+          @ea = (@pc + @value) & 0xffff
+        end
+
+        def dead_v_branch
+          dead_v
+          @pc = @ea if condition?(@opcode)
+        end
+
+        # A long branch taken takes one more cycle.
+        def dead_v_long_branch
+          dead_v
+          switch_to(LONG_BRANCH_TAKEN_PLAN) if condition?(@opcode)
+        end
+
+        def dead_v_take
+          dead_v
+          @pc = @ea
+        end
+
+        # The undocumented $14, $15 and $CD read on from PC, a byte a cycle,
+        # until reset.
+        def free_run
+          read_pc
+          @index -= 1
+        end
+
+        def condition?(opcode)
+          cc = @cc
+          case opcode & 0x0f
+          when 0x0 then true
+          when 0x1 then false
+          when 0x2 then cc.nobits?(CARRY | ZERO)
+          when 0x3 then cc.anybits?(CARRY | ZERO)
+          when 0x4 then cc.nobits?(CARRY)
+          when 0x5 then cc.anybits?(CARRY)
+          when 0x6 then cc.nobits?(ZERO)
+          when 0x7 then cc.anybits?(ZERO)
+          when 0x8 then cc.nobits?(OVERFLOW)
+          when 0x9 then cc.anybits?(OVERFLOW)
+          when 0xa then cc.nobits?(NEGATIVE)
+          when 0xb then cc.anybits?(NEGATIVE)
+          else signed_condition?(opcode, cc)
+          end
+        end
+
+        def signed_condition?(opcode, cc)
+          less = cc.anybits?(NEGATIVE) != cc.anybits?(OVERFLOW)
+          case opcode & 0x0f
+          when 0xc then !less
+          when 0xd then less
+          when 0xe then !less && cc.nobits?(ZERO)
+          else less || cc.anybits?(ZERO)
+          end
+        end
+      end
+    end
+  end
+end

data/lib/badline/chips/m6809/core.rb

@@ -0,0 +1,149 @@
+# frozen_string_literal: true
+
+require "badline/chips/m6809/opcodes"
+require "badline/chips/m6809/registers"
+require "badline/chips/m6809/bus_steps"
+require "badline/chips/m6809/indexed"
+require "badline/chips/m6809/stack"
+require "badline/chips/m6809/interrupts"
+require "badline/chips/m6809/arithmetic"
+require "badline/chips/m6809/operations"
+require "badline/chips/m6809/keyed_state"
+
+module Badline
+  module Chips
+    class M6809
+      # The Motorola 6809E, one bus cycle per #cycle!, on whatever bus +bus+
+      # is. The bus answers read(address) and write(address, value). Dead
+      # cycles are reads like any other, of the addresses Figure 17 of the
+      # MC6809E datasheet gives them, and the cycles the CPU leaves the bus
+      # alone (SYNC's, and HALT's) call nothing.
+      #
+      # Each instruction is a plan of steps, one a cycle, as the 6502 core
+      # runs them: the opcode fetch picks an Entry, whose address steps
+      # run first and whose tail follows.
+      module Core
+        include Registers
+        include BusSteps
+        include Indexed
+        include Stack
+        include Interrupts
+        include Arithmetic
+        include Operations
+        include KeyedState
+
+        attr_reader :bus, :cycles
+
+        def initialize(bus)
+          @bus = bus
+          @cycles = 0
+          @a = @b = @dp = 0
+          @x = @y = @u = @s = @pc = 0
+          @cc = IRQ_MASK | FIRQ_MASK
+          @ea = @value = @post = @opcode = 0
+          @group = @previous_group = GROUP_OTHER
+          @alu_word = 0
+          @vector = 0xfffe
+          @interrupt_mask = 0
+          @stack_u = false
+          @operation = :none
+          @page = PAGE1
+          @tail = NO_TAIL
+          clear_interrupts
+          reset!
+        end
+
+        # RESET going high: the CPU masks FIRQ and IRQ, clears DP, disarms
+        # NMI until S is loaded, and reads its vector from $FFFE.
+        def reset!
+          @cc |= IRQ_MASK | FIRQ_MASK
+          @dp = 0
+          @nmi_armed = false
+          clear_interrupts
+          @tail = NO_TAIL
+          @plan = RESET_PLAN
+          @index = 0
+        end
+
+        # Drops the instruction in flight so the next cycle fetches an
+        # opcode at PC, and sets the cycle count.
+        def resume(cycles)
+          @cycles = cycles
+          clear_interrupts
+          boundary
+        end
+
+        def cycle!
+          index = @index
+          @index = index + 1
+          send(@plan[index])
+          @cycles += 1
+          next_plan if @index >= @plan.length
+          sample_lines
+          nil
+        end
+
+        # Runs to the end of the instruction or interrupt sequence.
+        def step!
+          cycle!
+          cycle! until boundary? || waiting?
+          nil
+        end
+
+        # Whether the next cycle fetches an opcode, or takes an interrupt.
+        def boundary? = @index.zero? && @plan.equal?(FETCH_PLAN)
+
+        def inspect
+          format("Cycles: %<cycles>d, PC: %<pc>04x, S: %<s>04x, U: %<u>04x, X: %<x>04x, Y: %<y>04x, " \
+                 "A: %<a>02x, B: %<b>02x, DP: %<dp>02x, CC: %<cc>02x",
+                 cycles: @cycles, pc: @pc, s: @s, u: @u, x: @x, y: @y, a: @a, b: @b, dp: @dp, cc: @cc)
+        end
+
+        private
+
+        def boundary
+          @plan = FETCH_PLAN
+          @index = 0
+          @tail = NO_TAIL
+        end
+
+        # Starts an opcode's plan after its fetch.
+        def start(entry)
+          @operation = entry.operation
+          @previous_group = @group
+          @group = entry.group
+          @stack_u = false
+          plan = entry.plan
+          if plan.empty?
+            @tail = NO_TAIL
+            switch_to(entry.tail)
+          else
+            @tail = entry.tail
+            @plan = plan
+            @index = 0
+          end
+        end
+
+        # Replaces the rest of the plan.
+        def switch_to(plan)
+          @plan = plan
+          @index = 0
+        end
+
+        def next_plan
+          tail = @tail
+          return boundary if tail.equal?(NO_TAIL)
+
+          @tail = NO_TAIL
+          return switch_to(tail) unless tail.empty?
+
+          execute
+          boundary
+        end
+
+        # Runs the instruction method of the opcode in flight.
+        def execute = send(@operation)
+      end
+    end
+  end
+end

data/lib/badline/chips/m6809/indexed.rb

@@ -0,0 +1,82 @@
+# frozen_string_literal: true
+
+module Badline
+  module Chips
+    class M6809
+      # Indexed addressing: the postbyte, and the steps INDEXED_PLANS run
+      # after it.
+      module Indexed
+        private
+
+        # Reads the postbyte, works out every address that needs no more
+        # bytes, and moves on to the postbyte's plan. The undefined
+        # postbytes $x7, $xA and $xE address $0000 and take no cycles.
+        def postbyte
+          post = read_pc
+          @post = post
+          if post < 0x80
+            @ea = (index_register + (post & 0x0f) - (post & 0x10)) & 0xffff
+          else
+            register_address(post & 0x0f)
+          end
+          plan = INDEXED_PLANS[post]
+          return next_plan if plan.empty?
+
+          switch_to(plan)
+        end
+
+        def register_address(mode)
+          case mode
+          when 0x0 then post_increment(1)
+          when 0x1 then post_increment(2)
+          when 0x2 then pre_decrement(1)
+          when 0x3 then pre_decrement(2)
+          when 0x4 then @ea = index_register
+          when 0x5 then @ea = (index_register + signed8(@b)) & 0xffff
+          when 0x6 then @ea = (index_register + signed8(@a)) & 0xffff
+          when 0xb then @ea = (index_register + d) & 0xffff
+          when 0x7, 0xa, 0xe then @ea = 0
+          end
+        end
+
+        def post_increment(amount)
+          @ea = index_register
+          self.index_register = (@ea + amount) & 0xffff
+        end
+
+        def pre_decrement(amount)
+          @ea = (index_register - amount) & 0xffff
+          self.index_register = @ea
+        end
+
+        def signed8(value) = value - ((value & 0x80) << 1)
+
+        def offset8
+          @ea = (index_register + signed8(read_pc)) & 0xffff
+        end
+
+        def offset8_pc
+          offset = signed8(read_pc)
+          @ea = (@pc + offset) & 0xffff
+        end
+
+        def offset_lo_register
+          @value |= read_pc
+          @ea = (index_register + @value) & 0xffff
+        end
+
+        def offset_lo_absolute
+          @ea = @value | read_pc
+        end
+
+        def indirect_hi
+          @value = @bus.read(@ea) << 8
+        end
+
+        def indirect_lo
+          @ea = @value | @bus.read((@ea + 1) & 0xffff)
+        end
+      end
+    end
+  end
+end