badline 0.17.0 → 0.18.0

data/lib/badline/chips/m6809/operations.rb

@@ -0,0 +1,258 @@
+# frozen_string_literal: true
+
+module Badline
+  module Chips
+    class M6809
+      # The instruction methods the plans' *_exec steps call. A read takes
+      # its operand from @value; a write and a read-modify-write leave the
+      # byte or word to write there.
+      module Operations
+        private
+
+        def none; end
+        def nop; end
+        def sync; end
+
+        def neg = @value = neg8(@value)
+        def xnc = @value = xnc8(@value)
+        def com = @value = com8(@value)
+        def lsr = @value = lsr8(@value)
+        def ror = @value = ror8(@value)
+        def asr = @value = asr8(@value)
+        def asl = @value = asl8(@value)
+        def rol = @value = rol8(@value)
+        def dec = @value = dec8(@value)
+        def xdec = @value = xdec8(@value)
+        def inc = @value = inc8(@value)
+        def tst = logic8(@value)
+        def clr = @value = clr8
+
+        def jmp
+          @pc = @ea
+        end
+
+        def nega = @a = neg8(@a)
+        def xnca = @a = xnc8(@a)
+        def coma = @a = com8(@a)
+        def lsra = @a = lsr8(@a)
+        def rora = @a = ror8(@a)
+        def asra = @a = asr8(@a)
+        def asla = @a = asl8(@a)
+        def rola = @a = rol8(@a)
+        def deca = @a = dec8(@a)
+        def xdeca = @a = xdec8(@a)
+        def inca = @a = inc8(@a)
+        def tsta = logic8(@a)
+        def xclra = @a = xclr8
+        def clra = @a = clr8
+
+        def negb = @b = neg8(@b)
+        def xncb = @b = xnc8(@b)
+        def comb = @b = com8(@b)
+        def lsrb = @b = lsr8(@b)
+        def rorb = @b = ror8(@b)
+        def asrb = @b = asr8(@b)
+        def aslb = @b = asl8(@b)
+        def rolb = @b = rol8(@b)
+        def decb = @b = dec8(@b)
+        def xdecb = @b = xdec8(@b)
+        def incb = @b = inc8(@b)
+        def tstb = logic8(@b)
+        def xclrb = @b = xclr8
+        def clrb = @b = clr8
+
+        def suba = @a = sub8(@a, @value, 0)
+        def cmpa = sub8(@a, @value, 0)
+        def sbca = @a = sub8(@a, @value, carry)
+        def anda = @a = logic8(@a & @value)
+        def bita = logic8(@a & @value)
+        def lda = @a = logic8(@value)
+        def sta = @value = logic8(@a)
+        def eora = @a = logic8(@a ^ @value)
+        def adca = @a = add8(@a, @value, carry)
+        def ora = @a = logic8(@a | @value)
+        def adda = @a = add8(@a, @value, 0)
+
+        def subb = @b = sub8(@b, @value, 0)
+        def cmpb = sub8(@b, @value, 0)
+        def sbcb = @b = sub8(@b, @value, carry)
+        def andb = @b = logic8(@b & @value)
+        def bitb = logic8(@b & @value)
+        def ldb = @b = logic8(@value)
+        def stb = @value = logic8(@b)
+        def eorb = @b = logic8(@b ^ @value)
+        def adcb = @b = add8(@b, @value, carry)
+        def orb = @b = logic8(@b | @value)
+        def addb = @b = add8(@b, @value, 0)
+
+        def subd = self.d = sub16(d, @value)
+        def addd = self.d = add16(d, @value)
+        def cmpd = sub16(d, @value)
+        def cmpx = sub16(@x, @value)
+        def cmpy = sub16(@y, @value)
+        def cmpu = sub16(@u, @value)
+        def cmps = sub16(@s, @value)
+        def xaddd = add16(d, @value)
+        def xaddu = add16(@u | 0xff00, @value)
+
+        def ldd = self.d = logic16(@value)
+        def ldx = @x = logic16(@value)
+        def ldy = @y = logic16(@value)
+        def ldu = @u = logic16(@value)
+        def lds = load_s(logic16(@value))
+        def std = @value = logic16(d)
+        def stx = @value = logic16(@x)
+        def sty = @value = logic16(@y)
+        def stu = @value = logic16(@u)
+        def sts = @value = logic16(@s)
+
+        # The undocumented stores immediate. Prefixed, they set N and clear
+        # Z and V. Unprefixed, their flags hang on the instruction before
+        # (Banks' "Flags for unprefixed Store Immediate"), and the 16-bit
+        # ones also clear Z unless the register's low byte is 0.
+        def xsta = flags(NEGATIVE | ZERO | OVERFLOW, previous_group_flags)
+        def xstb = flags(NEGATIVE | ZERO | OVERFLOW, previous_group_flags)
+        def xsta2 = flags(NEGATIVE | ZERO | OVERFLOW, NEGATIVE)
+        def xstb2 = flags(NEGATIVE | ZERO | OVERFLOW, NEGATIVE)
+        def xstx = @value = store_word_low(@x)
+        def xstu = @value = store_word_low(@u)
+
+        def xsty = @value = store_word_low_prefixed(@y)
+        def xsts = @value = store_word_low_prefixed(@s)
+        def xstx2 = @value = store_word_low_prefixed(@x)
+        def xstu2 = @value = store_word_low_prefixed(@u)
+
+        def store_word_low(word)
+          low = word & 0xff
+          set = previous_group_flags & (NEGATIVE | ZERO)
+          set &= ~ZERO unless low.zero?
+          flags(NEGATIVE | ZERO | OVERFLOW, set)
+          low
+        end
+
+        def store_word_low_prefixed(word)
+          flags(NEGATIVE | ZERO | OVERFLOW, NEGATIVE)
+          word & 0xff
+        end
+
+        def previous_group_flags
+          case @previous_group
+          when GROUP_N0_Z1 then ZERO
+          when GROUP_A_00 then nz8(@a)
+          when GROUP_A_FF then (@a == 0xff ? ZERO : 0) | (@a.anybits?(0x80) ? 0 : NEGATIVE)
+          when GROUP_A_01 then decremented_flags(@a)
+          when GROUP_B_01 then decremented_flags(@b)
+          when GROUP_WORD_01 then decremented_flags(@alu_word >> 8)
+          when GROUP_LEA then decremented_flags((@alu_word >> 8) | (@alu_word & 0xff))
+          else NEGATIVE
+          end
+        end
+
+        # Z for 1, N for a negative value less one, V for $80.
+        def decremented_flags(value)
+          (value == 1 ? ZERO : 0) | ((value - 1).nobits?(0x80) ? 0 : NEGATIVE) | (value == 0x80 ? OVERFLOW : 0)
+        end
+
+        # JSR, BSR and LBSR, once the return address is stacked.
+        def jsr
+          @pc = @ea
+        end
+
+        def leax
+          @alu_word = @ea
+          @x = @ea
+          flags(ZERO, @ea.zero? ? ZERO : 0)
+        end
+
+        def leay
+          @alu_word = @ea
+          @y = @ea
+          flags(ZERO, @ea.zero? ? ZERO : 0)
+        end
+
+        def leas
+          @alu_word = @ea
+          load_s(@ea)
+        end
+
+        def leau
+          @alu_word = @ea
+          @u = @ea
+        end
+
+        def orcc = @cc |= @value
+        def andcc = @cc &= @value
+
+        def abx = @x = (@x + @b) & 0xffff
+
+        def mul
+          self.d = @a * @b
+          flags(ZERO | CARRY, (d.zero? ? ZERO : 0) | (@b >> 7))
+        end
+
+        def sex
+          @a = @b.nobits?(0x80) ? 0 : 0xff
+          flags(NEGATIVE | ZERO, nz16(d))
+        end
+
+        # DAA. V is C xor bit 7 of the result, as Banks found, where the
+        # datasheet clears it.
+        def daa
+          correction = 0
+          correction |= 0x06 if @cc.anybits?(HALF_CARRY) || (@a & 0x0f) > 0x09
+          high = @a & 0xf0
+          correction |= 0x60 if @cc.anybits?(CARRY) || high > 0x90 || (high > 0x80 && (@a & 0x0f) > 0x09)
+          result = (@a + correction) & 0xff
+          carry = correction >= 0x60 ? CARRY : 0
+          overflow = (carry == 1) == result.anybits?(0x80) ? 0 : OVERFLOW
+          flags(NEGATIVE | ZERO | OVERFLOW | CARRY, nz8(result) | overflow | carry)
+          @a = result
+        end
+
+        # The undocumented $18: each flag, ANDed with its bit of the byte
+        # after the opcode, moves one bit up, and V also takes Z ANDed with
+        # bit 2.
+        def x18
+          masked = @cc & @value
+          @cc = ((masked << 1) & 0xff) | (masked.nobits?(ZERO) ? 0 : OVERFLOW)
+        end
+
+        def exg
+          first = @post >> 4
+          second = @post & 0x0f
+          value = transfer_register(second)
+          set_transfer_register(second, sized(transfer_register(first), first, second))
+          set_transfer_register(first, sized(value, second, first))
+        end
+
+        def tfr
+          source = @post >> 4
+          destination = @post & 0x0f
+          set_transfer_register(destination, sized(transfer_register(source), source, destination))
+        end
+
+        # A value moved from register code +from+ to +to+: an 8-bit register
+        # fills a 16-bit one's high byte with $FF, and a 16-bit one gives an
+        # 8-bit one its low byte.
+        def sized(value, from, to)
+          return value & 0xff if to >= 8
+          return value | 0xff00 if from >= 8
+
+          value
+        end
+
+        def swi = software_interrupt(0xfffa, IRQ_MASK | FIRQ_MASK, ENTIRE)
+        def swi2 = software_interrupt(0xfff4, 0, ENTIRE)
+        def swi3 = software_interrupt(0xfff2, 0, ENTIRE)
+        def xres = software_interrupt(0xfffe, 0, 0)
+        def xswi2 = software_interrupt(0xfff4, 0, 0)
+        def xfirq = software_interrupt(0xfff6, 0, 0)
+
+        def software_interrupt(vector, mask, entire)
+          @cc |= entire
+          interrupt_vector(vector, mask)
+        end
+      end
+    end
+  end
+end

data/lib/badline/chips/m6809/plans.rb

@@ -0,0 +1,143 @@
+# frozen_string_literal: true
+
+module Badline
+  module Chips
+    class M6809
+      # The condition code bits.
+      CARRY = 0x01
+      OVERFLOW = 0x02
+      ZERO = 0x04
+      NEGATIVE = 0x08
+      IRQ_MASK = 0x10
+      HALF_CARRY = 0x20
+      FIRQ_MASK = 0x40
+      ENTIRE = 0x80
+
+      # What an opcode runs: the instruction method its *_exec step calls,
+      # the steps that work out its address, one a cycle, and the steps
+      # that follow them, and the group the undocumented stores immediate
+      # take their flags from when it ran before them. An indexed opcode's
+      # address steps end in the postbyte, which picks the rest from
+      # INDEXED_PLANS.
+      Entry = Struct.new(:operation, :plan, :tail, :group)
+
+      # The groups of David Banks' "Flags for unprefixed Store Immediate".
+      GROUP_OTHER = 0
+      GROUP_N0_Z1 = 1
+      GROUP_A_00 = 2
+      GROUP_A_FF = 3
+      GROUP_A_01 = 4
+      GROUP_B_01 = 5
+      GROUP_WORD_01 = 6
+      GROUP_LEA = 7
+      GROUPS = {
+        GROUP_N0_Z1 => %i[bita cmpa],
+        GROUP_A_00 => %i[lda ldd],
+        GROUP_A_FF => %i[adca adda anda eora ora sbca suba],
+        GROUP_A_01 => %i[asla asra coma daa deca inca lsra nega rola rora subd tsta xdeca xnca],
+        GROUP_B_01 => %i[sex],
+        GROUP_WORD_01 => %i[cmpd cmps cmpu cmpx cmpy xaddd xaddu],
+        GROUP_LEA => %i[leas leau leax leay]
+      }.flat_map { |group, operations| operations.map { |operation| [operation, group] } }.to_h.freeze
+
+      # The plan between instructions: the next cycle fetches an opcode.
+      FETCH_PLAN = %i[fetch].freeze
+
+      # The tail an instruction has once it is running its tail, never run.
+      # The empty tail, JUMP_TAIL, runs the instruction method as the
+      # address steps end.
+      NO_TAIL = %i[none].freeze
+      JUMP_TAIL = [].freeze
+
+      DIRECT_PLAN = %i[direct dead_v].freeze
+      EXTENDED_PLAN = %i[extended_hi extended_lo dead_v].freeze
+      INDEXED_PLAN = %i[postbyte].freeze
+
+      # The steps that read or write the address once it is known.
+      TAILS = {
+        read8: %i[read_exec],
+        read16: %i[read_hi read_lo_exec],
+        read16_dead: %i[read_hi read_lo_exec dead_v],
+        write8: %i[write_exec],
+        write16: %i[write_hi_exec write_lo],
+        rmw: %i[rmw_read dead_v rmw_write],
+        test: %i[read_exec dead_v dead_v],
+        jump: JUMP_TAIL,
+        subroutine: %i[dead_ea dead_v push_pcl push_pch_exec],
+        load_address: %i[dead_v_exec]
+      }.freeze
+
+      IMMEDIATE_TAILS = {
+        read8: %i[immediate_exec],
+        read16: %i[immediate_hi immediate_lo_exec],
+        read16_dead: %i[immediate_hi immediate_lo_exec dead_v]
+      }.freeze
+
+      # The 12 bytes SWI and the hardware interrupts other than FIRQ stack,
+      # in the order they go onto S.
+      PUSH_ALL = %i[push_pcl push_pch push_wl push_wh push_yl push_yh push_xl push_xh push_dp push_b push_a
+                    push_cc].freeze
+      VECTOR_STEPS = %i[dead_v vector_hi vector_lo dead_v].freeze
+
+      # SWI, SWI2, SWI3 and the undocumented XRES, XSWI2 and XFIRQ, after
+      # the opcode. The instruction method picks the vector.
+      SOFTWARE_INTERRUPT_TAIL = [:dead_pc, :dead_v_exec, *PUSH_ALL, *VECTOR_STEPS].freeze
+
+      # IRQ and NMI after the cycle that would have fetched the opcode, and
+      # FIRQ, which stacks only PC and CC.
+      INTERRUPT_PLAN = [:dead_pc, :dead_v_exec, *PUSH_ALL, *VECTOR_STEPS].freeze
+      FAST_INTERRUPT_PLAN = [:dead_pc, :dead_v_exec, :push_pcl, :push_pch, :push_cc, *VECTOR_STEPS].freeze
+
+      # The interrupt CWAI was waiting for: its vector, no more stacking.
+      WAITED_INTERRUPT_PLAN = %i[vector_hi vector_lo dead_v].freeze
+
+      # RTI after pulling CC, with E set and with E clear.
+      RETURN_ENTIRE_PLAN = %i[pull_a pull_b pull_dp pull_xh pull_xl pull_yh pull_yl pull_wh pull_wl pull_pch pull_pcl
+                              dead_stack].freeze
+      RETURN_FAST_PLAN = %i[pull_pch pull_pcl dead_stack].freeze
+
+      # The cycles after RESET goes high: two dead reads of $FFFE, the
+      # vector, and a dead cycle.
+      RESET_PLAN = %i[reset_dead reset_dead reset_hi reset_lo dead_v].freeze
+
+      LONG_BRANCH_TAKEN_PLAN = %i[dead_v_take].freeze
+      SYNC_END_PLAN = %i[idle].freeze
+
+      # PSH and PUL by postbyte: the bytes in the order they go onto or
+      # come off the stack, PC first on and last off.
+      PUSH_ORDER = [[0x80, %i[push_pcl push_pch]], [0x40, %i[push_wl push_wh]], [0x20, %i[push_yl push_yh]],
+                    [0x10, %i[push_xl push_xh]], [0x08, %i[push_dp]], [0x04, %i[push_b]], [0x02, %i[push_a]],
+                    [0x01, %i[push_cc]]].freeze
+      PULL_ORDER = [[0x01, %i[pull_cc]], [0x02, %i[pull_a]], [0x04, %i[pull_b]], [0x08, %i[pull_dp]],
+                    [0x10, %i[pull_xh pull_xl]], [0x20, %i[pull_yh pull_yl]], [0x40, %i[pull_wh pull_wl]],
+                    [0x80, %i[pull_pch pull_pcl]]].freeze
+      PUSH_PLANS = Array.new(256) do |mask|
+        [:dead_v, :dead_v, :dead_stack, *PUSH_ORDER.flat_map { |bit, steps| mask.nobits?(bit) ? [] : steps }].freeze
+      end.freeze
+      PULL_PLANS = Array.new(256) do |mask|
+        [:dead_v, :dead_v, *PULL_ORDER.flat_map { |bit, steps| mask.nobits?(bit) ? [] : steps }, :dead_stack].freeze
+      end.freeze
+
+      # The steps after the postbyte, by postbyte, Figure 17 sheet 4.
+      INDEXED_PLANS = Array.new(256) do |post|
+        next %i[dead_pc dead_v].freeze if post < 0x80
+
+        plan = case post & 0x0f
+               when 0x0, 0x2 then %i[dead_pc dead_v dead_v]
+               when 0x1, 0x3 then %i[dead_pc dead_v dead_v dead_v]
+               when 0x4 then %i[dead_pc]
+               when 0x5, 0x6 then %i[dead_pc dead_v]
+               when 0x8 then %i[offset8 dead_v]
+               when 0x9 then %i[offset_hi offset_lo_register dead_pc dead_v dead_v]
+               when 0xb then %i[dead_pc dead_pc_next dead_pc_next2 dead_v dead_v]
+               when 0xc then %i[offset8_pc dead_v]
+               when 0xd then %i[offset_hi offset_lo_pc dead_pc dead_v dead_v dead_v]
+               when 0xf then %i[offset_hi offset_lo_absolute dead_pc]
+               else []
+               end
+        plan += %i[indirect_hi indirect_lo dead_v] if post.anybits?(0x10)
+        plan.freeze
+      end.freeze
+    end
+  end
+end

data/lib/badline/chips/m6809/registers.rb

@@ -0,0 +1,82 @@
+# frozen_string_literal: true
+
+module Badline
+  module Chips
+    class M6809
+      # The programmer's registers, and the codes TFR and EXG and the
+      # indexed postbyte name them by.
+      module Registers
+        attr_accessor :a, :b, :x, :y, :u, :s, :pc, :dp, :cc
+
+        def d = (@a << 8) | @b
+
+        def d=(value)
+          @a = value >> 8
+          @b = value & 0xff
+        end
+
+        # Whether NMI is armed: a load of S since reset.
+        def nmi_armed? = @nmi_armed
+
+        private
+
+        def load_s(value)
+          @s = value
+          @nmi_armed = true
+        end
+
+        # The register bits 5 and 6 of an indexed postbyte name.
+        def index_register
+          case @post & 0x60
+          when 0x00 then @x
+          when 0x20 then @y
+          when 0x40 then @u
+          else @s
+          end
+        end
+
+        def index_register=(value)
+          case @post & 0x60
+          when 0x00 then @x = value
+          when 0x20 then @y = value
+          when 0x40 then @u = value
+          else load_s(value)
+          end
+        end
+
+        # A TFR or EXG register: D, X, Y, U, S and PC are 0 to 5, A, B, CC
+        # and DP 8 to 11. The other codes read as $FF or $FFFF.
+        def transfer_register(code)
+          case code
+          when 0x0 then d
+          when 0x1 then @x
+          when 0x2 then @y
+          when 0x3 then @u
+          when 0x4 then @s
+          when 0x5 then @pc
+          when 0x8 then @a
+          when 0x9 then @b
+          when 0xa then @cc
+          when 0xb then @dp
+          else code < 8 ? 0xffff : 0xff
+          end
+        end
+
+        def set_transfer_register(code, value)
+          case code
+          when 0x0 then self.d = value
+          when 0x1 then @x = value
+          when 0x2 then @y = value
+          when 0x3 then @u = value
+          when 0x4 then load_s(value)
+          when 0x5 then @pc = value
+          when 0x8 then @a = value
+          when 0x9 then @b = value
+          when 0xa then @cc = value
+          when 0xb then @dp = value
+          end
+        end
+      end
+    end
+  end
+end

data/lib/badline/chips/m6809/stack.rb

@@ -0,0 +1,140 @@
+# frozen_string_literal: true
+
+module Badline
+  module Chips
+    class M6809
+      # The stack steps of PSH, PUL, JSR, BSR, RTS, RTI, the software
+      # interrupts and the hardware ones. Each pushes onto or pulls off the
+      # stack @stack_u names: U for PSHU and PULU, S otherwise. The "other"
+      # stack pointer, w, is the one that isn't.
+      module Stack
+        private
+
+        def push(value)
+          if @stack_u
+            @u = (@u - 1) & 0xffff
+            @bus.write(@u, value)
+          else
+            @s = (@s - 1) & 0xffff
+            @bus.write(@s, value)
+          end
+        end
+
+        def pull
+          if @stack_u
+            value = @bus.read(@u)
+            @u = (@u + 1) & 0xffff
+          else
+            value = @bus.read(@s)
+            @s = (@s + 1) & 0xffff
+          end
+          value
+        end
+
+        def dead_stack = @bus.read(@stack_u ? @u : @s)
+
+        def other_stack = @stack_u ? @s : @u
+
+        def other_stack=(value)
+          @stack_u ? load_s(value) : @u = value
+        end
+
+        def push_s_post = stack_post(false, PUSH_PLANS)
+
+        def push_u_post = stack_post(true, PUSH_PLANS)
+
+        def pull_s_post = stack_post(false, PULL_PLANS)
+
+        def pull_u_post = stack_post(true, PULL_PLANS)
+
+        def stack_post(stack_u, plans)
+          @stack_u = stack_u
+          switch_to(plans[read_pc])
+        end
+
+        def push_pcl = push(@pc & 0xff)
+        def push_pch = push(@pc >> 8)
+        def push_wl = push(other_stack & 0xff)
+        def push_wh = push(other_stack >> 8)
+        def push_yl = push(@y & 0xff)
+        def push_yh = push(@y >> 8)
+        def push_xl = push(@x & 0xff)
+        def push_xh = push(@x >> 8)
+        def push_dp = push(@dp)
+        def push_b = push(@b)
+        def push_a = push(@a)
+        def push_cc = push(@cc)
+
+        def push_pch_exec
+          push_pch
+          execute
+        end
+
+        def pull_cc
+          @cc = pull
+        end
+
+        def pull_a
+          @a = pull
+        end
+
+        def pull_b
+          @b = pull
+        end
+
+        def pull_dp
+          @dp = pull
+        end
+
+        def pull_xh
+          @x = (pull << 8) | (@x & 0xff)
+        end
+
+        def pull_xl
+          @x = (@x & 0xff00) | pull
+        end
+
+        def pull_yh
+          @y = (pull << 8) | (@y & 0xff)
+        end
+
+        def pull_yl
+          @y = (@y & 0xff00) | pull
+        end
+
+        def pull_wh
+          self.other_stack = (pull << 8) | (other_stack & 0xff)
+        end
+
+        def pull_wl
+          self.other_stack = (other_stack & 0xff00) | pull
+        end
+
+        def pull_pch
+          @pc = (pull << 8) | (@pc & 0xff)
+        end
+
+        def pull_pcl
+          @pc = (@pc & 0xff00) | pull
+        end
+
+        # RTI after pulling CC: the whole state when E is set, else PC.
+        def return_cc
+          pull_cc
+          switch_to(@cc.nobits?(ENTIRE) ? RETURN_FAST_PLAN : RETURN_ENTIRE_PLAN)
+        end
+
+        # The vector of the interrupt or SWI being taken. The masks it sets
+        # take effect as its first byte is read.
+        def vector_hi
+          @value = @bus.read(@vector) << 8
+          @cc |= @interrupt_mask
+        end
+
+        def vector_lo
+          @pc = @value | @bus.read(@vector + 1)
+        end
+      end
+    end
+  end
+end

data/lib/badline/chips/m6809.rb

@@ -0,0 +1,13 @@
+# frozen_string_literal: true
+
+require "badline/chips/m6809/core"
+
+module Badline
+  module Chips
+    # The Motorola 6809E, which the SuperPET has beside its 6502. It is not
+    # part of badline/core, so a machine that has one requires it.
+    class M6809
+      include Core
+    end
+  end
+end

data/lib/badline/chips/riot/timer.rb

@@ -13,8 +13,12 @@ module Badline
       # reads N - 1 until cycle T, 0 until cycle N x T, and $FF with the flag
       # set on cycle N x T: 52 at ÷8 sets the flag on cycle 416. From there
       # the counter counts every cycle, so it tells how long ago the flag
-      # set, and each count through 0 sets the flag again. Only a write puts
-      # the prescaler back.
+      # set, and each count through 0 sets the flag again. On the 6532 only
+      # a write puts the prescaler back. On the 6530, as the KIM-1 User
+      # Manual's appendix H has it, a read of the counter after the flag
+      # set does too, and the counter counts on from where it is at the
+      # interval written: a 6530 builds its timer with
+      # read_restores_divider. No test program has confirmed it.
       #
       # Reading or writing the counter clears the flag, except for a read on
       # the cycle that sets it. Each access takes A3 as the interrupt enable.
@@ -24,7 +28,8 @@ module Badline
         attr_reader :counter, :flag
         attr_accessor :irq_enabled
 
-        def initialize
+        def initialize(read_restores_divider: false)
+          @read_restores_divider = read_restores_divider
           @counter = 0
           @divider = 1
           @prescale = 1
@@ -50,6 +55,7 @@ module Badline
         def read(irq_enabled)
           @irq_enabled = irq_enabled
           @flag = false unless @fired
+          restore_divider if @read_restores_divider && @expired
           @counter
         end
 
@@ -66,6 +72,11 @@ module Badline
 
         private
 
+        def restore_divider
+          @expired = false
+          @prescale = @divider
+        end
+
         def count
           @counter = (@counter - 1) & 0xff
           return unless @counter == 0xff

data/lib/badline/chips/rriot.rb

@@ -9,7 +9,9 @@ module Badline
     # of RAM, two 8-bit ports, A and B, each with a direction register, a 1
     # making the pin an output, and the 6532's interval timer (RIOT::Timer).
     # It has no edge detector. The 8050 and 8250's floppy controller has
-    # one, its ROM the controller's program.
+    # one, its ROM the controller's program, and the KIM-1 two. Its timer
+    # reads its counter as the 6532's does, but a read after the flag sets
+    # puts the prescaler back (RIOT::Timer).
     #
     # Which addresses select the ROM, the RAM and the registers is part of
     # the mask, so the board decodes them and calls read_rom (A9-A0),
@@ -36,7 +38,7 @@ module Badline
         @peripheral = peripheral
         @irq_on_pb7 = irq_on_pb7
         @ram = Array.new(64, 0)
-        @timer = RIOT::Timer.new
+        @timer = RIOT::Timer.new(read_restores_divider: true)
         reset!
       end