badline 0.16.0 → 0.17.0

data/lib/badline/drives/model2031/keyed_state.rb

@@ -0,0 +1,66 @@
+# frozen_string_literal: true
+
+module Badline
+  module Drives
+    class Model2031
+      # The drive's own fields in a keyed snapshot module (BL-D8): its
+      # model, its clock phase and cycle count, the SO pulse due, and the
+      # controller's lines as the IEEE-488 port latched them under ieee.*. A
+      # save settles the drive first, so it is awake; a load forgets its
+      # orbits.
+      module KeyedState
+        def save_fields(out)
+          settle!
+          out.text("model", model_name).int("phase", @phase).int("cycles", @cycles)
+          out.bool("so_pending", @mechanism.so_pending)
+          @serial_port.save_fields(out, "ieee.")
+          out
+        end
+
+        def load_fields(input)
+          settle!
+          input.choice("model", [model_name], model_name)
+          @phase = input.int("phase", @phase)
+          @cycles = input.int("cycles", @cycles)
+          @mechanism.so_pending = input.bool("so_pending", @mechanism.so_pending)
+          @serial_port.load_fields(input, "ieee.")
+        end
+
+        # The drive as modules of its own, named from `name` (BL-D8 for
+        # device 8): its own fields, its RAM, each VIA, the CPU, the
+        # mechanism and the disk, when one is in, as the 1541's.
+        def save_modules(sections, name)
+          sections << Snapshot::Keyed.section(name) { |out| save_fields(out) }
+          sections << Snapshot::Keyed.section("#{name}-RAM") { |out| @bus.save_fields(out) }
+          sections << Snapshot::Keyed.section("#{name}-VIA1") { |out| @via1.save_fields(out) }
+          sections << Snapshot::Keyed.section("#{name}-VIA2") { |out| @via2.save_fields(out) }
+          sections << Snapshot::Keyed.section("#{name}-CPU") { |out| @cpu.save_fields(out) }
+          sections << Snapshot::Keyed.section("#{name}-MECH") { |out| @mechanism.save_fields(out) }
+          disk = @mechanism.disk
+          sections << Snapshot::Keyed.section("#{name}-DISK") { |out| disk.save_fields(out) } if disk
+          sections
+        end
+
+        # The drive from its modules, `input` being its own. No disk module
+        # means no disk in the drive.
+        def load_modules(modules, input, name)
+          load_fields(input)
+          @bus.load_fields(modules.required("#{name}-RAM"))
+          @via1.load_fields(modules.required("#{name}-VIA1"))
+          @via2.load_fields(modules.required("#{name}-VIA2"))
+          @cpu.load_fields(modules.required("#{name}-CPU"))
+          disk = modules.optional("#{name}-DISK")
+          mechanism = modules.required("#{name}-MECH")
+          @mechanism.load_fields(mechanism,
+                                 disk.nil? ? nil : Model1541::Disk.from_fields(disk, detached: modules.detached?))
+          @via1.restored!
+          @via2.restored!
+          @cpu.restored!
+          forget_orbits
+        end
+      end
+
+      include KeyedState
+    end
+  end
+end

data/lib/badline/drives/model2031/parts.rb

@@ -0,0 +1,25 @@
+# frozen_string_literal: true
+
+module Badline
+  module Drives
+    class Model2031
+      # VIA 1, facing the IEEE-488 bus (IEEEPort), a class of its own so
+      # its peripheral keeps one type, apart from the serial drives'.
+      class IEEEVIA < Chips::VIA
+        # DDRB, whose PB0 says whether the VIA drives ATNA (IEEEPort).
+        def port_b_directions = @ddrb
+      end
+
+      # The drive CPU's bus, decoded as the 1541's (Model1541::Bus), with
+      # VIA 1 an IEEEVIA.
+      class Bus < Model1541::Bus
+      end
+
+      # The drive's 6502, on the drive's Bus.
+      class CPU
+        include Badline::Chips::CPU::Core
+        include Engine::IdleCPU
+      end
+    end
+  end
+end

data/lib/badline/drives/model2031.rb

@@ -0,0 +1,92 @@
+# frozen_string_literal: true
+
+require "badline/drives/model1541"
+require "badline/drives/ieee_bus"
+require "badline/drives/model2031/parts"
+require "badline/drives/model2031/ieee_port"
+require "badline/drives/model2031/keyed_state"
+
+module Badline
+  module Drives
+    # The 2031 disk drive of the PET and CBM: the 1541's board with an
+    # IEEE-488 interface in place of the serial one (Commodore schematic
+    # 2031038). A 6502 at 1 MHz runs DOS 2.6 from 16 KB of ROM, with 2 KB
+    # of RAM, VIA 1 at $1800 on the IEEE-488 bus (IEEEPort) and VIA 2 at
+    # $1C00 running the 1541's GCR Mechanism, decoded as the 1541's.
+    #
+    # Drives::Engine::Core clocks it against the host and sleeps through
+    # the DOS's idle loop, as the 1541's, until ATN moves or a timer is due
+    # (Engine::VIAs). The bus reads the lines it pulls without waking it.
+    class Model2031
+      include Engine::Core
+      include Engine::VIAs
+
+      CLOCK_HZ = 1_000_000
+
+      # Where the DOS's idle loop starts over (see Drives::Engine::Idle).
+      IDLE_LOOP = 0xec4d
+
+      # The host cycles by which a 2031 switched on with the machine has run
+      # its DOS's RAM test and ROM checksums and reads its jumpers.
+      BOOT_CYCLES = 1_300_000
+
+      attr_reader :ieee_bus
+
+      def model_name = "2031"
+
+      # +rom+ covers $C000-$FFFF, and defaults to the DOS image in the ROM
+      # path. +device+ is the number the jumpers set, 8 to 11.
+      def initialize(rom: nil, host_clock_hz: CLOCK_HZ, device: 8, debug: false)
+        @device = device
+        @ieee_bus = IEEEBus.new
+        @serial_port = IEEEPort.new(device:, bus: @ieee_bus)
+        @via1 = IEEEVIA.new(start: 0x1800, peripheral: @serial_port)
+        @serial_port.via = @via1
+        @mechanism = Model1541::Mechanism.new
+        @via2 = Model1541::DiskVIA.new(start: 0x1c00, mechanism: @mechanism)
+        @bus = Bus.new(rom: rom || ROM.load("dos2031.rom", 0xc000), via1: @via1, via2: @via2)
+        @cpu = CPU.new(@bus, debug:)
+        @clock_hz = CLOCK_HZ
+        @idle_loop = IDLE_LOOP
+        @host_clock_hz = host_clock_hz
+        @phase = 0
+        @cycles = 0
+        init_idle(debug)
+        @via1.ca1 = false
+        @via1.reset!
+        connect(@ieee_bus)
+      end
+
+      # Plugs the drive into an IEEE-488 bus, leaving the one it was on.
+      def connect(ieee_bus)
+        settle!
+        @ieee_bus.detach(self)
+        @ieee_bus = ieee_bus
+        @serial_port.bus = ieee_bus
+        ieee_bus.attach(self)
+        hear_atn
+      end
+
+      # The lines the drive pulls on the bus while ATN is low or not
+      # (IEEEPort). They hold still while it sleeps, so reading them leaves
+      # it asleep.
+      def ieee_low_lines(atn) = @serial_port.ieee_low_lines(atn)
+
+      private
+
+      # One drive cycle, as the 1541's (Model1541#step): the mechanism, then
+      # ATN on VIA 1's CA1, the VIAs and the CPU.
+      def step
+        so = @mechanism.take_so
+        @mechanism.cycle!
+        @via1.ca1 = @serial_port.atn_low?
+        @via1.cycle!
+        @via2.cycle!
+        @cpu.irq = @via1.irq? || @via2.irq?
+        @cpu.so! if so
+        @cpu.cycle!
+        @cycles += 1
+      end
+    end
+  end
+end

data/lib/badline/drives/model8050/disk.rb

@@ -0,0 +1,163 @@
+# frozen_string_literal: true
+
+module Badline
+  module Drives
+    class Model8050
+      # A .d80 or .d82 image as the floppy controller finds it on the disk:
+      # each track a ring of byte cells, each cell ten bit cells the GCR ROM
+      # turns into a data byte (Track::SYNC for a run of ones), so the
+      # mechanism needs no GCR. A track is laid out as the DOS's format code
+      # writes it ($C000-$C363 of DOS 2.7, run on the controller), sector
+      # after sector:
+      #
+      #   4 sync, $08, checksum, sector, track, ID 2, ID 1, $0F,
+      #   19 x $0F, 5 sync, $07, 256 data bytes, checksum, then $00
+      #
+      # the header checksum the EOR of the track, sector and IDs, and the
+      # data block's that of its bytes. The $00 gaps share out what the
+      # track has left over.
+      #
+      # Tracks come off the image as the head first reaches them. What the
+      # head writes goes back to the image when the motor stops (flush):
+      # every data block found on a written track whose header and checksum
+      # read cleanly.
+      class Disk
+        SYNC = 0x100
+
+        attr_reader :image
+
+        def initialize(image)
+          @image = image
+          @tracks = {}
+          @written = {}
+        end
+
+        def write_protected? = @image.read_only?
+
+        # The image's host file.
+        def path = @image.path
+
+        # How many tracks a side holds: 77.
+        def side_tracks = Storage::D80Image::SIDE_TRACKS
+
+        def sides = @image.is_a?(Storage::D82Image) ? 2 : 1
+
+        # The cells of +track+, 1 to 77 on the first side and 78 to 154 on
+        # the second, or nil past the disk's last.
+        def track(number)
+          return nil unless number.between?(1, side_tracks * sides)
+
+          @tracks[number] ||= build(number)
+        end
+
+        # The cells a track of the zone holds in one turn at 300 rpm: the
+        # 200,000 cycles of a turn over the zone's ten bit cells a byte at
+        # 6 MHz / (16 - zone).
+        def self.cells_in(zone) = 120_000 / (16 - zone)
+
+        # The zone a track is recorded in, 3 outermost to 0 innermost.
+        def self.zone_of(track)
+          cylinder = ((track - 1) % Storage::D80Image::SIDE_TRACKS) + 1
+          3 - Storage::D80Image::ZONE_LAST_TRACKS.count { |last| cylinder > last }
+        end
+
+        # The head wrote to +track+.
+        def written(number)
+          @written[number] = true
+        end
+
+        # Stores the blocks the head wrote in the image.
+        def flush
+          return if @written.empty?
+
+          blocks = []
+          @written.each_key { |number| blocks.concat(read_blocks(@tracks[number])) }
+          @written.clear
+          @image.store_blocks(blocks) unless blocks.empty?
+        end
+
+        private
+
+        def build(number)
+          id1, id2 = disk_id
+          cells = []
+          sectors = @image.sectors_in(number)
+          sectors.times do |sector|
+            data = @image.read_block(number, sector)
+            cells.push(SYNC, SYNC, SYNC, SYNC, 0x08, number ^ sector ^ id1 ^ id2, sector, number, id2, id1)
+            cells.concat(Array.new(20, 0x0f))
+            cells.push(SYNC, SYNC, SYNC, SYNC, SYNC, 0x07)
+            cells.concat(data)
+            cells << checksum(data)
+          end
+          pad(cells, sectors, self.class.cells_in(self.class.zone_of(number)))
+        end
+
+        # Shares the $00 gap out after each sector.
+        def pad(cells, sectors, length)
+          sector_length = cells.length / sectors
+          gap = (length - cells.length) / sectors
+          padded = []
+          sectors.times do |sector|
+            padded.concat(cells[sector * sector_length, sector_length])
+            padded.concat(Array.new(sector == sectors - 1 ? length - padded.length : gap, 0x00))
+          end
+          padded
+        end
+
+        def checksum(bytes)
+          sum = 0
+          bytes.each { |byte| sum ^= byte }
+          sum
+        end
+
+        # The ID the header block holds at $18.
+        def disk_id
+          header = @image.read_block(*@image.header_block)
+          [header[0x18], header[0x19]]
+        end
+
+        # Every block whose header and data read cleanly off +cells+, as
+        # [track, sector, data, nil].
+        def read_blocks(cells)
+          blocks = []
+          index = 0
+          length = cells.length
+          while (index = next_block(cells, index, 0x08))
+            header = Array.new(5) { |offset| cells[(index + offset) % length] }
+            index = next_block(cells, index, 0x07)
+            break unless index
+
+            block = data_block(cells, index, header)
+            blocks << block if block
+            break if index + 260 >= length
+          end
+          blocks
+        end
+
+        # The cell after the next sync run followed by +mark+, from
+        # +index+, or nil.
+        def next_block(cells, index, mark)
+          length = cells.length
+          while index < length
+            return index + 2 if cells[index] == SYNC && cells[(index + 1) % length] == mark
+
+            index += 1
+          end
+          nil
+        end
+
+        def data_block(cells, index, header)
+          checksum, sector, track, id2, id1 = header
+          return nil unless checksum == (track ^ sector ^ id1 ^ id2)
+
+          length = cells.length
+          data = Array.new(256) { |offset| cells[(index + offset) % length] }
+          return nil if data.include?(SYNC) || checksum(data) != cells[(index + 256) % length]
+
+          [track, sector, data, nil]
+        end
+      end
+    end
+  end
+end

data/lib/badline/drives/model8050/fdc_bus.rb

@@ -0,0 +1,102 @@
+# frozen_string_literal: true
+
+module Badline
+  module Drives
+    class Model8050
+      # The floppy controller's bus (schematic 8050001, sheet 2), which
+      # decodes A0-A12 only, so it repeats every 8 KB. A 74LS42 on A10-A12
+      # picks a 1 KB block:
+      #
+      # $0000-$03FF - the 6530 and the VIA: with A7 set the 6530's
+      #               registers, else with A6 set the VIA's, else the
+      #               6530's 64 bytes of RAM, which the controller also
+      #               uses as its stack at $0100
+      # $0400-$13FF - the common RAM
+      # $1400-$1BFF - nothing: open bus
+      # $1C00-$1FFF - the 6530's ROM
+      #
+      # Writes to the ROM and to open bus go nowhere, and a read from open
+      # bus finds the last byte on the data bus.
+      class FDCBus
+        include Addressable
+
+        attr_reader :common, :via, :rriot
+        attr_accessor :data
+
+        # How many writes have changed a byte of the common RAM
+        # (Model8050::Idle).
+        attr_reader :common_changes
+
+        # Whether a counter or an interrupt flag has been read since it was
+        # last cleared (Model8050::Idle).
+        attr_accessor :volatile
+
+        def initialize(common:, via:, rriot:)
+          addressable_at(0, length: 2**16)
+          @common = common
+          @via = via
+          @rriot = rriot
+          @data = 0
+          @volatile = false
+          @common_changes = 0
+        end
+
+        def peek(addr)
+          addr &= 0x1fff
+          @data = if addr < 0x0400
+                    peek_chips(addr)
+                  elsif addr < 0x1400
+                    @common.peek(addr - 0x0400)
+                  elsif addr >= 0x1c00
+                    @rriot.read_rom(addr)
+                  else
+                    @data
+                  end
+        end
+
+        def poke(addr, value)
+          @data = value
+          addr &= 0x1fff
+          if addr < 0x0400
+            poke_chips(addr, value)
+          elsif addr < 0x1400
+            poke_common(addr - 0x0400, value)
+          end
+        end
+
+        private
+
+        def poke_common(index, value)
+          @common_changes += 1 if @common.peek(index) != value
+          @common.poke(index, value)
+        end
+
+        def peek_chips(addr)
+          if addr.anybits?(0x80)
+            @volatile = true if addr.anybits?(0x04)
+            return @rriot.peek(addr & 0x0f)
+          end
+          return peek_via(addr & 0x0f) if addr.anybits?(0x40)
+
+          @rriot.read_ram(addr)
+        end
+
+        # The VIA's counters, shift register and flags move on their own.
+        def peek_via(register)
+          @volatile = true if register.between?(0x04, 0x0a) || register == 0x0d
+          @via.peek(0x40 | register)
+        end
+
+        def poke_chips(addr, value)
+          if addr.anybits?(0x80)
+            @rriot.poke(addr & 0x0f, value)
+          elsif addr.anybits?(0x40)
+            @via.poke(0x40 | (addr & 0x0f), value)
+          else
+            @rriot.write_ram(addr, value)
+          end
+        end
+      end
+    end
+  end
+end

data/lib/badline/drives/model8050/idle.rb

@@ -0,0 +1,177 @@
+# frozen_string_literal: true
+
+module Badline
+  module Drives
+    class Model8050
+      # Sleeping through the two processors' idle loops, exactly.
+      #
+      # With nothing to do, the IP goes round DOS 2.7's idle loop from
+      # IP_LOOP, and the FDC round its job loop from FDC_LOOP, each pass
+      # finding the job queue empty, until ATN interrupts the IP or the
+      # 6530's timer the FDC, every 5 ms. A pass puts back what it found,
+      # so each processor comes back to its loop's start as it left it, and
+      # only the chips' counters and the cycle counts move.
+      #
+      # Each time a processor comes to its loop's start, the unit compares
+      # what that processor sees with what it saw last time round: the CPU
+      # (Engine::IdleCPU#idle_state), its chips but for their counters, its
+      # RAM and the common RAM, and on the FDC's side the drives. The same,
+      # with no read of a counter or an interrupt flag between (the buses'
+      # volatile), makes the pass repeatable. Once both processors have a
+      # repeatable pass, with the motors off, no head stepping, no disk
+      # going in or out and no interrupt pulled, the unit sleeps:
+      # host_cycle! only counts the cycles it owes, until one of the chips'
+      # counters is due to pull IRQ (quiet_cycles), the controller moves a
+      # line of the bus, or something outside reads or changes the unit
+      # (settle!).
+      #
+      # Waking runs the counters on in bulk, counts off each processor's
+      # whole passes, and runs the rest of a pass on that processor alone.
+      # Its passes touch nothing the other one or the counters move, so the
+      # order the two run in doesn't matter. Then the unit runs cycle by
+      # cycle again. Woken by a counter, it keeps the passes it found, and
+      # sleeps again as soon as both repeat: the IP's, which the timer's
+      # interrupt doesn't reach, at once, and the FDC's a pass after its
+      # interrupt. Woken from outside, it finds both afresh.
+      module Idle
+        IP_LOOP = 0xc5a1
+        FDC_LOOP = 0xfc17
+
+        # Whether the unit may sleep through its idle loops.
+        attr_reader :idle_skip
+
+        def idle_skip=(on)
+          settle!
+          @idle_skip = on
+        end
+
+        def asleep? = @asleep
+
+        # Brings the unit up to the present, cycle for cycle, and drops the
+        # passes it found, since whoever called may change it.
+        def settle!
+          wake! if @asleep
+          forget_passes
+        end
+
+        private
+
+        def init_idle
+          @idle_skip = true
+          @asleep = false
+          @owed = 0
+          @budget = 0
+          forget_passes
+        end
+
+        def forget_passes
+          @ip_mark = nil
+          @fdc_mark = nil
+          @ip_pass = nil
+          @fdc_pass = nil
+        end
+
+        # A cycle owed while asleep, which wakes the unit once the budget
+        # is spent.
+        def owe_cycle
+          @owed += 1
+          wake! if @owed >= @budget
+        end
+
+        # Looks for the loops' starts after a cycle run awake. An interrupt
+        # pulled breaks the processor's pass.
+        def watch_loops
+          ip = @ip_cpu
+          @ip_pass = nil if ip.irq
+          @fdc_pass = nil if @fdc_cpu.irq
+          ip_pass_found if ip.program_counter == IP_LOOP && ip.boundary?
+          fdc = @fdc_cpu
+          fdc_pass_found if fdc.program_counter == FDC_LOOP && fdc.boundary?
+        end
+
+        def ip_pass_found
+          state = ip_state
+          @ip_pass = repeated(@ip_mark, state, @ip_cpu, @ip_bus.volatile)
+          @ip_mark = [state, @ip_cpu.cycles, @ip_cpu.instructions]
+          @ip_bus.volatile = false
+          fall_asleep if @ip_pass && @fdc_pass
+        end
+
+        def fdc_pass_found
+          state = fdc_state
+          @fdc_pass = repeated(@fdc_mark, state, @fdc_cpu, @fdc_bus.volatile)
+          @fdc_mark = [state, @fdc_cpu.cycles, @fdc_cpu.instructions]
+          @fdc_bus.volatile = false
+          fall_asleep if @ip_pass && @fdc_pass
+        end
+
+        # The pass since +mark+ as [cycles, instructions] if it left the
+        # processor as it found it, or nil.
+        def repeated(mark, state, cpu, volatile)
+          return nil if mark.nil? || volatile || mark[0] != state
+
+          [cpu.cycles - mark[1], cpu.instructions - mark[2]]
+        end
+
+        def fall_asleep
+          return unless @mechanism.quiet? && !@ip_cpu.irq && !@fdc_cpu.irq
+
+          budget = quiet_cycles
+          return if budget < 2
+
+          @asleep = true
+          @owed = 0
+          @budget = budget
+        end
+
+        # How many cycles the chips can run with no counter pulling IRQ.
+        def quiet_cycles
+          [@data_riot.quiet_cycles, @control_riot.quiet_cycles, @rriot.quiet_cycles, @via.quiet_cycles].min
+        end
+
+        # Runs the cycles owed: the counters in bulk, then each processor's
+        # whole passes and the rest of a pass.
+        def wake!
+          owed = @owed
+          @asleep = false
+          @owed = 0
+          return if owed.zero?
+
+          @data_riot.fast_forward(owed)
+          @control_riot.fast_forward(owed)
+          @rriot.fast_forward(owed)
+          @via.fast_forward(owed)
+          skip(@ip_cpu, @ip_pass, @ip_mark, owed)
+          skip(@fdc_cpu, @fdc_pass, @fdc_mark, owed)
+          @cycles += owed
+        end
+
+        # Counts off the processor's whole passes, moving its mark on with
+        # them, and runs the rest on the processor alone.
+        def skip(cpu, pass, mark, owed)
+          passes = owed / pass[0]
+          cpu.fast_forward(passes * pass[0], passes * pass[1])
+          mark[1] += passes * pass[0]
+          mark[2] += passes * pass[1]
+          (owed - (passes * pass[0])).times { cpu.cycle! }
+        end
+
+        # What the IP sees: its CPU, its RIOTs but for their counters, its
+        # bus's last byte and the common RAM, as the count of the writes
+        # that changed it.
+        def ip_state
+          [*@ip_cpu.idle_state, *@data_riot.idle_state, *@control_riot.idle_state, @ip_bus.data, common_changes]
+        end
+
+        # What the FDC sees: its CPU, the VIA and the 6530 but for their
+        # counters, its bus's last byte, the drives and the common RAM.
+        def fdc_state
+          [*@fdc_cpu.idle_state, *@via.idle_state, *@rriot.idle_state, @fdc_bus.data, *@mechanism.idle_state,
+           common_changes]
+        end
+
+        def common_changes = @ip_bus.common_changes + @fdc_bus.common_changes
+      end
+    end
+  end
+end