badline 0.16.0 → 0.17.0

data/lib/badline/chips/tpi.rb

@@ -0,0 +1,233 @@
+# frozen_string_literal: true
+
+require "badline/chips/tpi/keyed_state"
+
+module Badline
+  module Chips
+    # The MOS 6525 TPI (tri-port interface): three 8-bit ports, A, B and C,
+    # each with a direction register, a 1 making the pin an output. Its
+    # three address lines repeat the eight registers every 8 bytes:
+    #
+    # 0 - PRA
+    # 1 - PRB
+    # 2 - PRC, or in mode 1 the interrupt latches (bits 0-4) and the levels
+    #     of IRQ, CA and CB (bits 5-7)
+    # 3 - DDRA
+    # 4 - DDRB
+    # 5 - DDRC, which in mode 1 is the interrupt mask, its bits 0-4 enabling
+    #     I0-I4 with a 1, and reads back all eight bits written
+    # 6 - CR: bit 0 MC, the mode, bit 1 IP, the priority, bits 2-3 IE3 and
+    #     IE4, the active edges of I3 and I4 (1 rising), bits 4-5 CA's mode
+    #     and bits 6-7 CB's
+    # 7 - AIR, the active interrupt register, in mode 1
+    #
+    # A port reads its pins: an output's level, and what the peripheral
+    # lets through of an input, which floats high (read_a, read_b and
+    # read_c pull lines low, as a VIA's peripheral does).
+    #
+    # In mode 1 PC0-PC4 are the interrupt inputs I0-I4 (#interrupt_line).
+    # A falling edge on I0-I2, or the edge IE3 and IE4 pick on I3 and I4,
+    # sets the input's latch whether or not its mask bit is set. A write of
+    # 0 to a latch's bit of PRC clears it, and a 1 does nothing. PC5 is
+    # the IRQ output, open drain, low (#irq?) while the AIR holds a bit;
+    # PC6 is CA and PC7 CB (#ca?, #cb?).
+    #
+    # Without priority (IP 0), the AIR holds every unmasked latch that is
+    # set, and a read of it clears them and it. With priority (IP 1) the
+    # inputs rank I4 > I3 > I2 > I1 > I0, and the AIR holds the one highest
+    # unmasked latch that outranks the interrupt in service, the top of a
+    # five-level stack. A read of the AIR pushes it on the stack, clears it
+    # and its latch, and lets IRQ go; a write pops the stack, letting lower
+    # interrupts through again.
+    #
+    # CA: 00 set high by I3's active edge and low by a read of PRA, 01
+    # pulsed low by a read of PRA, 10 low, 11 high. CB: 00 set low by a
+    # write of PRB and high by I4's active edge, 01 pulsed low by a write of
+    # PRB, 10 low, 11 high. A pulse is shorter than a cycle, so CA and CB
+    # read high in mode 01.
+    #
+    # The rules are the MPS 6525 datasheet's (Commodore Semiconductor
+    # Group), pages 2-81 to 2-83.
+    class TPI
+      STACK_DEPTH = 5
+
+      attr_reader :peripheral, :latches, :control, :stack
+
+      def initialize(peripheral: nil)
+        @peripheral = peripheral
+        @lines = 0x1f
+        @stack = []
+        reset!
+      end
+
+      # The RES pin clears every register: mode 0, and every pin an input.
+      def reset!
+        @pra = @prb = @prc = 0
+        @ddra = @ddrb = @ddrc = 0
+        @control = 0
+        @latches = 0
+        @air = 0
+        @stack.clear
+        @ca = @cb = false
+      end
+
+      # The interrupt mask in mode 1: DDRC's bits 0-4.
+      def mask = @ddrc & 0x1f
+
+      # Whether IRQ is pulled low.
+      def irq? = @air != 0
+
+      # The levels of CA and CB in mode 1.
+      def ca? = @ca
+
+      def cb? = @cb
+
+      # The port lines as the chip drives them, inputs floating high.
+      def port_a_output = driven(@pra, @ddra)
+
+      def port_b_output = driven(@prb, @ddrb)
+
+      def port_c_output = mode1? ? pins_c_mode1 : driven(@prc, @ddrc)
+
+      # Something outside drives interrupt input +index+, I0 to I4, +high+
+      # or low. Its active edge sets its latch in mode 1.
+      def interrupt_line(index, high)
+        bit = 1 << index
+        was_high = @lines.anybits?(bit)
+        return if was_high == high
+
+        @lines = high ? @lines | bit : @lines & ~bit
+        return unless mode1? && high == rising_active?(index)
+
+        @latches |= bit
+        @ca = true if index == 3 && ca_mode.zero?
+        @cb = true if index == 4 && cb_mode.zero?
+        update_air
+      end
+
+      def peek(addr)
+        case addr & 0x07
+        when 0 then read_pra
+        when 1 then pins(@prb, @ddrb, @peripheral ? @peripheral.read_b(port_b_output) : 0xff)
+        when 2 then mode1? ? pins_c_mode1 : read_pins_c
+        when 3 then @ddra
+        when 4 then @ddrb
+        when 5 then @ddrc
+        when 6 then @control
+        else read_air
+        end
+      end
+
+      def poke(addr, value)
+        case addr & 0x07
+        when 0 then @pra = value
+        when 1 then write_prb(value)
+        when 2 then write_prc(value)
+        when 3 then @ddra = value
+        when 4 then @ddrb = value
+        when 5 then write_ddrc(value)
+        when 6 then write_control(value)
+        else pop_air
+        end
+      end
+
+      private
+
+      def mode1? = @control.anybits?(0x01)
+
+      def priority? = @control.anybits?(0x02)
+
+      def ca_mode = (@control >> 4) & 0x03
+
+      def cb_mode = (@control >> 6) & 0x03
+
+      # I3 and I4 latch on the edge IE3 and IE4 pick, the others falling.
+      def rising_active?(index)
+        case index
+        when 3 then @control.anybits?(0x04)
+        when 4 then @control.anybits?(0x08)
+        else false
+        end
+      end
+
+      def driven(register, direction) = (register & direction) | (~direction & 0xff)
+
+      def pins(register, direction, inputs) = (register & direction) | (inputs & ~direction & 0xff)
+
+      def read_pra
+        @ca = false if mode1? && ca_mode.zero?
+        pins(@pra, @ddra, @peripheral ? @peripheral.read_a(port_a_output) : 0xff)
+      end
+
+      def read_pins_c
+        pins(@prc, @ddrc, @peripheral ? @peripheral.read_c(port_c_output) : 0xff)
+      end
+
+      # The latches, IRQ's level, CA's and CB's.
+      def pins_c_mode1
+        @latches | (irq? ? 0 : 0x20) | (@ca ? 0x40 : 0) | (@cb ? 0x80 : 0)
+      end
+
+      def write_prb(value)
+        @prb = value
+        @cb = false if mode1? && cb_mode.zero?
+      end
+
+      def write_prc(value)
+        return @prc = value unless mode1?
+
+        @latches &= value | 0xe0
+        update_air
+      end
+
+      def write_ddrc(value)
+        @ddrc = value
+        update_air
+      end
+
+      def write_control(value)
+        @control = value
+        @ca = ca_mode.anybits?(0x01) unless ca_mode.zero?
+        @cb = cb_mode.anybits?(0x01) unless cb_mode.zero?
+        update_air
+      end
+
+      def read_air
+        value = @air
+        return value unless mode1?
+
+        @latches &= ~value
+        @air = 0
+        if priority?
+          @stack.shift if @stack.length == STACK_DEPTH
+          @stack << value
+        end
+        update_air
+        value
+      end
+
+      def pop_air
+        return unless mode1?
+
+        @stack.pop
+        update_air
+      end
+
+      # The AIR's bits from the latches, the mask and, with priority, the
+      # interrupt in service.
+      def update_air
+        pending = mode1? ? @latches & mask : 0
+        return @air = pending unless priority?
+
+        highest = highest_bit(pending)
+        @air = highest > (@stack.last || 0) ? highest : 0
+      end
+
+      def highest_bit(bits)
+        bit = 0x10
+        bit >>= 1 while bit.positive? && bits.nobits?(bit)
+        bit
+      end
+    end
+  end
+end

data/lib/badline/chips/vic/bank.rb

@@ -10,6 +10,13 @@ module Badline
       # The machine's bus pushes in what the VIC sees through #connect,
       # #map_character_rom and #map whenever it changes. Until then the bank
       # has a CIA 2, RAM, colour RAM and character ROM of its own.
+      #
+      # The P500 wires the VIC another way (#map_video_bus): its phi1
+      # reads go to the character ROM while VICDOTSEL is high, and its phi2
+      # reads to the 1K static video matrix while STATVID is high, VA12
+      # high picking the matrix and VA12 low reading 0. Otherwise both go to
+      # the DRAM's 16K bank that VA14 and VA15 pick (#video_bus_lines). The
+      # colour nibbles come from the colour RAM in every phi2 read.
       class Bank
         include Addressable
 
@@ -30,6 +37,11 @@ module Badline
           map(Memory.new([], length: 2**16, start: 0))
           @lines = 0b11
           @swapped = false
+          @video_bus = false
+          @matrix = @ram
+          @statvid = false
+          @dotsel = false
+          @video_base = 0
         end
 
         # CIA 2, whose port A picks the bank, and the colour RAM, read from
@@ -57,9 +69,31 @@ module Badline
             @base = base
             @starts = BANK_STARTS.map { |start| base + start }.freeze
           end
-          @phi1_ultimax = phi1_ultimax
-          @ultimax = ultimax
           @romh = romh
+          @phi1_other = phi1_ultimax
+          @phi2_other = ultimax
+        end
+
+        # The P500's video bus: +dram+ is segment 0's 64K, +matrix+ the
+        # static video matrix, read from its start address on, and
+        # +color_ram+ the colour RAM, read from +color_base+ on. The
+        # character ROM is the one #map_character_rom gives, read from
+        # +base+ on.
+        def map_video_bus(dram, matrix, color_ram, color_base)
+          @ram = dram
+          @matrix = matrix
+          @color_ram = color_ram
+          @color_base = color_base
+          @video_bus = true
+          @phi1_other = true
+          @phi2_other = true
+        end
+
+        # STATVID, VICDOTSEL and VA14-VA15, as the P500's TPIs drive them.
+        def video_bus_lines(statvid, dotsel, bank)
+          @statvid = statvid
+          @dotsel = dotsel
+          @video_base = bank << 14
         end
 
         # On the 8565, a port A write that swaps the two bank lines, driving
@@ -74,7 +108,7 @@ module Badline
         end
 
         def peek(offset)
-          return ultimax_peek(offset) if @phi1_ultimax
+          return phi1_other(offset) if @phi1_other
 
           bits = bank_switch_register
           if (bits & @shadow_mask) == 0b01 && (offset & 0xf000) == 0x1000
@@ -88,7 +122,13 @@ module Badline
         # memory configuration the CPU does in that half. No cartridge drives
         # Ultimax mode in the first half alone, so otherwise it reads as #peek.
         def peek_phi2(offset)
-          @ultimax ? ultimax_peek(offset) : peek(offset)
+          @phi2_other ? phi2_other(offset) : peek(offset)
+        end
+
+        # A sprite's s-access in phi2: on the P500's video bus as the other
+        # phi2 reads, and otherwise as #peek.
+        def peek_sprite(offset)
+          @video_bus ? phi2_other(offset) : peek(offset)
         end
 
         def peek_color(offset)
@@ -101,7 +141,7 @@ module Badline
 
         # True if the VIC reads the character ROM at this offset.
         def character_rom?(offset)
-          !@phi1_ultimax && (bank_switch_register & @shadow_mask) == 0b01 && (offset & 0xf000) == 0x1000
+          !@phi1_other && (bank_switch_register & @shadow_mask) == 0b01 && (offset & 0xf000) == 0x1000
         end
 
         def start
@@ -110,6 +150,21 @@ module Badline
 
         private
 
+        def phi1_other(offset)
+          return ultimax_peek(offset) unless @video_bus
+          return @character_rom.peek(@character_base + (offset & 0x0fff)) if @dotsel
+
+          @ram.peek(@video_base + offset)
+        end
+
+        def phi2_other(offset)
+          return ultimax_peek(offset) unless @video_bus
+          return @ram.peek(@video_base + offset) unless @statvid
+          return 0 if offset.nobits?(0x1000)
+
+          @matrix.peek(@matrix.start + (offset & 0x03ff))
+        end
+
         # In Ultimax mode the cartridge ROMH replaces the character ROM
         # shadow, visible at $3000-$3FFF of the window. The MAX is in
         # Ultimax mode with no cartridge too.

data/lib/badline/chips/vic/sprite.rb

@@ -322,12 +322,13 @@ module Badline
         end
 
         # The three s-accesses step MC through the sprite's block, wrapping
-        # within it.
+        # within it. The first and third fall in phi2 and the second in
+        # phi1 (Bank#peek_sprite).
         def row_bits(counter)
           base = pointer * 64
-          (@bank.peek(base + counter) << 16) |
+          (@bank.peek_sprite(base + counter) << 16) |
             (@bank.peek(base + ((counter + 1) & MC_MASK)) << 8) |
-            @bank.peek(base + ((counter + 2) & MC_MASK))
+            @bank.peek_sprite(base + ((counter + 2) & MC_MASK))
         end
 
         def pointer = @bank.peek(@registers.screen_base + 0x3f8 + index)

data/lib/badline/drives/datasette/keyed_state.rb

@@ -10,7 +10,8 @@ module Badline
       # bytes and how far it has played. A tape that isn't in leaves tape.* out. A datasette that
       # times the read line's level adds when in the countdown the line
       # rises, and whether a recording's low half wave is on the tape. The
-      # sense and flag handlers don't fire on load.
+      # sense and flag handlers don't fire on load, and the running handler
+      # does when the load starts or stops the tape.
       module KeyedState
         def save_fields(out)
           out.bool("playing", @playing).bool("motor", @motor).int("countdown", @countdown)
@@ -33,6 +34,13 @@ module Badline
           @write_high = input.bool("write_high", @write_high)
           @rise_at = input.int("rise_at", @rise_at)
           @low_recorded = input.bool("low_recorded", @low_recorded)
+          load_tape(input)
+          update_running
+        end
+
+        private
+
+        def load_tape(input)
           bytes = input.bytes("tape.bytes", "".b).bytes
           return @tape = nil if bytes.empty?
 

data/lib/badline/drives/datasette.rb

@@ -14,7 +14,6 @@ module Badline
       # What inserting a tape raises on a machine without a cassette port.
       class Missing < ArgumentError; end
       attr_reader :tape
-      attr_writer :motor
 
       def initialize(tape = nil, level: false)
         @tape = tape
@@ -30,6 +29,8 @@ module Badline
         @low_recorded = false
         @flag_handler = nil
         @sense_handler = nil
+        @running_handler = nil
+        @running = false
       end
 
       # Falling edges on the tape read line.
@@ -42,6 +43,17 @@ module Badline
         @sense_handler = handler
       end
 
+      # Whether the tape runs (#running?), each time that changes, a
+      # snapshot's load included.
+      def on_running_change(&handler)
+        @running_handler = handler
+      end
+
+      def motor=(on)
+        @motor = on
+        update_running
+      end
+
       # Whether the machine has a datasette at its cassette port. The SX-64
       # has none: its keys stay up and it takes no tape.
       def connected? = @connected
@@ -56,11 +68,13 @@ module Badline
 
         @tape = tape
         rewind
+        update_running
       end
 
       def eject
         stop!
         @tape = nil
+        update_running
       end
 
       def rewind
@@ -117,7 +131,8 @@ module Badline
 
       def motor? = @motor
 
-      def running? = @playing && @motor && !@tape.nil?
+      # Whether the tape moves: a key down, the motor on and a tape in.
+      def running? = @running
 
       # The tape read line's level, on a datasette built with +level: true+.
       # Each pulse holds it low for its first half and high for its second,
@@ -131,7 +146,7 @@ module Badline
       end
 
       def cycle!
-        return unless running?
+        return unless @running
         return @since += 1 if @recording
 
         next_pulse if @countdown.zero?
@@ -175,9 +190,18 @@ module Badline
 
         finish_recording unless down
         @playing = down
+        update_running
         @sense_handler&.call
       end
 
+      def update_running
+        running = @playing && @motor && !@tape.nil?
+        return if running == @running
+
+        @running = running
+        @running_handler&.call
+      end
+
       # Releasing the keys ends a recording, and writes the tape out.
       def finish_recording
         return unless @recording

data/lib/badline/drives/ieee_bus.rb

@@ -8,9 +8,13 @@ module Badline
     # pulls it low. The PET is the controller and always on the bus, and
     # reads back every line it drives.
     #
-    # No device plugs in yet, so the lines carry the controller's levels
-    # alone: nobody answers a handshake, and the KERNAL reports DEVICE NOT
-    # PRESENT for every device the traps don't serve.
+    # The controller pushes the lines it pulls whenever they may have moved
+    # (host_lines=), and the bus holds them for the drives, which take them
+    # a host cycle late. Each drive on the bus answers the lines it pulls
+    # (ieee_low_lines) while ATN is or isn't low, from its own outputs, which
+    # hold still while it sleeps. With no drive on the bus nobody answers a
+    # handshake, and the KERNAL reports DEVICE NOT PRESENT for every device
+    # the traps don't serve.
     class IEEEBus
       # The lines as bits, the data lines in the low byte, DIO1 in bit 0.
       DIO = 0x00ff
@@ -20,9 +24,51 @@ module Badline
       NDAC = 0x0800
       ATN = 0x1000
 
+      # The lines the controller last pushed.
+      attr_reader :host_lines
+
+      attr_reader :drives
+
+      def initialize
+        @drives = []
+        @host_lines = 0
+      end
+
+      # The controller pushes the lines it pulls, and the drives look at
+      # them again.
+      def host_lines=(lines)
+        @host_lines = lines
+        drives = @drives
+        i = 0
+        while i < drives.length
+          drives[i].host_written!
+          i += 1
+        end
+      end
+
+      def attach(drive)
+        @drives << drive unless @drives.include?(drive)
+      end
+
+      def detach(drive)
+        @drives.delete(drive)
+      end
+
       # The lines low on the bus while the controller pulls the lines in
       # +controller+ low.
-      def low_lines(controller) = controller
+      def low_lines(controller)
+        low = controller
+        drives = @drives
+        return low if drives.empty?
+
+        atn = controller.anybits?(ATN)
+        i = 0
+        while i < drives.length
+          low |= drives[i].ieee_low_lines(atn)
+          i += 1
+        end
+        low
+      end
     end
   end
 end

data/lib/badline/drives/model2031/ieee_port.rb

@@ -0,0 +1,133 @@
+# frozen_string_literal: true
+
+module Badline
+  module Drives
+    class Model2031
+      # VIA 1's side of the IEEE-488 bus (Drives::IEEEBus), through a 75160
+      # for the data lines and a 75161 for the control lines (schematic
+      # 2031038, sheet 2):
+      #
+      #   PA0-7  DIO1-8                   PB4  T/R, high to talk
+      #   PB0    ATN acknowledge (ATNA)   PB5  HD SEL, unused
+      #   PB1    NRFD                     PB6  DAV
+      #   PB2    NDAC                     PB7  ATN in, high while ATN is low
+      #   PB3    EOI                      CA1  ATN in, as PB7
+      #
+      # The ports read and drive the lines' levels, 0 for a low line. T/R
+      # turns the transceivers: talking, the drive drives the data lines,
+      # DAV and EOI, and reads NRFD and NDAC; listening, the other way round.
+      # EOI turns back to the bus while ATN is low. A pin the transceiver
+      # drives the bus from reads the drive's own side, high but for what
+      # the VIA or a jumper pulls low.
+      #
+      # An XOR of ATN in and ATNA drives two 7406s that pull NRFD and NDAC
+      # low on the bus, so the drive answers ATN before the DOS gets to it,
+      # and holds the bus until the DOS acknowledges. ATNA reaches the XOR
+      # only while PB0 is an output, and is low there otherwise, which
+      # leaves the bus alone while the DOS reads the jumpers.
+      #
+      # The device number jumpers are diodes from PB0 and PB1 to CA2: with
+      # CA2 low, a fitted diode pulls its line low, and the DOS reads the
+      # device number off the two at reset, 8 with both fitted. Lifting the
+      # one on PB0 adds 1, and the one on PB1 2.
+      #
+      # The drive takes the controller's lines a host cycle late, as the
+      # serial drives do (Engine::SerialLines): latch_host takes them at the
+      # end of each host cycle.
+      class IEEEPort
+        ATNA = 0x01
+        NRFD = 0x02
+        NDAC = 0x04
+        EOI = 0x08
+        TALK = 0x10
+        DAV = 0x40
+        ATN_IN = 0x80
+
+        attr_reader :bus
+
+        # The lines the controller pulled, as latch_host took them.
+        attr_reader :host
+
+        def initialize(device:, bus:)
+          raise ArgumentError, "a 2031 is device 8 to 11, not #{device}" unless device.between?(8, 11)
+
+          @diodes = ~(device - 8) & 0x03
+          @via = nil
+          @host = 0
+          self.bus = bus
+        end
+
+        # The drive's VIA 1, whose outputs it drives the bus with.
+        attr_writer :via
+
+        def bus=(bus)
+          @bus = bus
+          latch_host
+        end
+
+        # Takes the controller's lines for the drive cycles of the next host
+        # cycle.
+        def latch_host
+          @host = @bus.host_lines
+        end
+
+        # Whether the controller has moved ATN since the last latch_host.
+        def atn_moved? = (@bus.host_lines ^ @host).anybits?(IEEEBus::ATN)
+
+        def atn_low? = @host.anybits?(IEEEBus::ATN)
+
+        # The data lines, while the transceiver listens.
+        def read_a(_lines) = talking? ? 0xff : ~@bus.low_lines(@host) & 0xff
+
+        # The control lines the transceiver turns towards the drive, and
+        # ATN.
+        def read_b(_lines)
+          low = @bus.low_lines(@host)
+          value = 0x7f
+          if talking?
+            value &= ~NRFD if low.anybits?(IEEEBus::NRFD)
+            value &= ~NDAC if low.anybits?(IEEEBus::NDAC)
+            value &= ~EOI if low.anybits?(IEEEBus::EOI) && low.anybits?(IEEEBus::ATN)
+          else
+            value &= ~EOI if low.anybits?(IEEEBus::EOI)
+            value &= ~DAV if low.anybits?(IEEEBus::DAV)
+          end
+          value |= ATN_IN if low.anybits?(IEEEBus::ATN)
+          value & jumpers
+        end
+
+        # The lines the drive pulls low while ATN is low or not, as bus bits.
+        def ieee_low_lines(atn)
+          via = @via
+          lines = via.port_b_output & jumpers
+          low = 0
+          if lines.anybits?(TALK)
+            low |= ~via.port_a_output & IEEEBus::DIO
+            low |= IEEEBus::DAV if lines.nobits?(DAV)
+            low |= IEEEBus::EOI if lines.nobits?(EOI) && !atn
+          else
+            low |= IEEEBus::NRFD if lines.nobits?(NRFD)
+            low |= IEEEBus::NDAC if lines.nobits?(NDAC)
+          end
+          low |= IEEEBus::NRFD | IEEEBus::NDAC if atn != (lines & via.port_b_directions).anybits?(ATNA)
+          low
+        end
+
+        # The controller's lines as the port latched them, under `prefix`.
+        def save_fields(out, prefix) = out.int("#{prefix}host", @host)
+
+        def load_fields(input, prefix)
+          @host = input.int("#{prefix}host", @host)
+        end
+
+        private
+
+        def talking? = @via.port_b_output.anybits?(TALK)
+
+        # PB0 and PB1 as the jumper diodes leave them: pulled low through
+        # each fitted one while CA2 is low.
+        def jumpers = @via.ca2_output ? 0xff : ~@diodes & 0xff
+      end
+    end
+  end
+end