badline 0.16.0 → 0.17.0

data/lib/badline/drives/model8050/ieee_port.rb

@@ -0,0 +1,147 @@
+# frozen_string_literal: true
+
+module Badline
+  module Drives
+    class Model8050
+      # The interface processor's two 6532s on the IEEE-488 bus
+      # (Drives::IEEEBus), through MC3446 transceivers (schematic 8050001,
+      # sheet 1). UC1 carries the data lines, its port A reading them and
+      # its port B driving them. UE1 carries the rest:
+      #
+      #   PA0  ATN acknowledge (ATNA)     PB0-2  the device number jumpers
+      #   PA1  NDAC out, low while set    PB3    drive 1's LED
+      #   PA2  NRFD out                   PB4    drive 0's LED
+      #   PA3  EOI out                    PB5    the error LED
+      #   PA4  DAV out                    PB6    NDAC in
+      #   PA5  EOI in                     PB7    NRFD in
+      #   PA6  DAV in
+      #   PA7  ATN in, high while ATN is low
+      #
+      # The ports read and drive the lines' levels, 0 for a low line, but
+      # for NDAC out, which pulls NDAC low while set. The DOS sets it as it
+      # waits for a byte and clears it once it has taken one ($C627-$C650).
+      # Every input reads the bus, the drive's own lines included.
+      #
+      # ATN in also reaches UE1's PA7 edge detector, which the DOS arms for
+      # the rising edge ($C58A), so ATN interrupts the interface processor.
+      # While ATN in and ATNA differ, the board pulls NRFD and NDAC low, so
+      # the drive answers ATN before the DOS gets to it, as the 2031 does.
+      #
+      # The device number jumpers ground PB0-2: cutting one adds its weight
+      # to 8.
+      #
+      # The drive takes the controller's lines a host cycle late, as the
+      # 2031 does: latch_host takes them at the end of each host cycle.
+      class IEEEPort
+        ATNA = 0x01
+        NDAC_OUT = 0x02
+        NRFD_OUT = 0x04
+        EOI_OUT = 0x08
+        DAV_OUT = 0x10
+        EOI_IN = 0x20
+        DAV_IN = 0x40
+        ATN_IN = 0x80
+        NDAC_IN = 0x40
+        NRFD_IN = 0x80
+
+        attr_reader :bus
+
+        # The lines the controller pulled, as latch_host took them.
+        attr_accessor :host
+
+        # The RIOTs on the data lines and on the control lines.
+        attr_accessor :data_riot, :control_riot
+
+        def initialize(device:, bus:)
+          raise ArgumentError, "an 8050 is device 8 to 15, not #{device}" unless device.between?(8, 15)
+
+          @jumpers = (device - 8) | 0xf8
+          @host = 0
+          @data_riot = nil
+          @control_riot = nil
+          self.bus = bus
+        end
+
+        def bus=(bus)
+          @bus = bus
+          latch_host
+        end
+
+        # Takes the controller's lines for the drive cycles of the next host
+        # cycle.
+        def latch_host
+          @host = @bus.host_lines
+        end
+
+        # Whether the controller has moved ATN since the last latch_host.
+        def atn_moved? = (@bus.host_lines ^ @host).anybits?(IEEEBus::ATN)
+
+        # Whether the controller has moved any line since the last
+        # latch_host.
+        def lines_moved? = @bus.host_lines != @host
+
+        def atn_low? = @host.anybits?(IEEEBus::ATN)
+
+        # UC1's port A: the data lines.
+        def data_lines = ~@bus.low_lines(@host) & 0xff
+
+        # UE1's port A inputs. ATN in comes through the edge detector's own
+        # pin (RIOT#pa7=), so bit 7 is left high here.
+        def control_a
+          low = @bus.low_lines(@host)
+          value = 0xff
+          value &= ~EOI_IN if low.anybits?(IEEEBus::EOI)
+          value &= ~DAV_IN if low.anybits?(IEEEBus::DAV)
+          value
+        end
+
+        # UE1's port B inputs: the jumpers, NDAC and NRFD.
+        def control_b
+          low = @bus.low_lines(@host)
+          value = @jumpers
+          value &= ~NDAC_IN if low.anybits?(IEEEBus::NDAC)
+          value &= ~NRFD_IN if low.anybits?(IEEEBus::NRFD)
+          value
+        end
+
+        # The lines the drive pulls low while ATN is low or not, as bus bits.
+        def ieee_low_lines(atn)
+          control = @control_riot.port_a_output
+          low = ~@data_riot.port_b_output & IEEEBus::DIO
+          low |= IEEEBus::EOI if control.nobits?(EOI_OUT)
+          low |= IEEEBus::DAV if control.nobits?(DAV_OUT)
+          low |= IEEEBus::NRFD if control.nobits?(NRFD_OUT)
+          low |= IEEEBus::NDAC if control.anybits?(NDAC_OUT)
+          low |= IEEEBus::NRFD | IEEEBus::NDAC if atn != control.anybits?(ATNA)
+          low
+        end
+
+        # Which LEDs UE1 lights: bit 0 drive 1's, bit 1 drive 0's, bit 2 the
+        # error LED.
+        def leds = (@control_riot.port_b_output >> 3) & 0x07
+      end
+
+      # UC1's peripheral: the data lines on port A, port B only driving.
+      class DataLines
+        def initialize(port)
+          @port = port
+        end
+
+        def read_a(_lines) = @port.data_lines
+
+        def read_b(_lines) = 0xff
+      end
+
+      # UE1's peripheral: the control lines and the jumpers.
+      class ControlLines
+        def initialize(port)
+          @port = port
+        end
+
+        def read_a(_lines) = @port.control_a
+
+        def read_b(_lines) = @port.control_b
+      end
+    end
+  end
+end

data/lib/badline/drives/model8050/ip_bus.rb

@@ -0,0 +1,93 @@
+# frozen_string_literal: true
+
+module Badline
+  module Drives
+    class Model8050
+      # The interface processor's bus (schematic 8050001, sheet 1). A
+      # 74LS42 on A12-A15 picks a 4 KB block:
+      #
+      # $0000-$0FFF - the two 6532s. A9 is their RS pin and A7 picks one:
+      #               UC1's RAM at $00-$7F and UE1's at $80-$FF, mirrored at
+      #               $0100 for the stack since A8 isn't decoded, and their
+      #               registers at $0200 (UC1) and $0280 (UE1)
+      # $1000-$4FFF - the common RAM, 1 KB in each block, mirrored through it
+      # $5000-$BFFF - nothing: open bus
+      # $C000-$FFFF - DOS 2.7, 901887-01 and 901888-01
+      #
+      # Writes to the ROM and to open bus go nowhere, and a read from open
+      # bus finds the last byte on the data bus.
+      class IPBus
+        include Addressable
+
+        attr_reader :common, :rom, :data_riot, :control_riot
+        attr_accessor :data
+
+        # How many writes have changed a byte of the common RAM
+        # (Model8050::Idle).
+        attr_reader :common_changes
+
+        # Whether a timer or the interrupt flags have been read since it was
+        # last cleared (Model8050::Idle).
+        attr_accessor :volatile
+
+        def initialize(rom:, common:, data_riot:, control_riot:)
+          addressable_at(0, length: 2**16)
+          @rom = rom
+          @common = common
+          @data_riot = data_riot
+          @control_riot = control_riot
+          @data = 0
+          @volatile = false
+          @common_changes = 0
+        end
+
+        def peek(addr)
+          return @data = @rom.peek(addr) if addr >= 0xc000
+
+          @data = if addr < 0x1000
+                    peek_riots(addr)
+                  elsif addr < 0x5000
+                    @common.peek((((addr >> 12) - 1) << 10) | (addr & 0x03ff))
+                  else
+                    @data
+                  end
+        end
+
+        def poke(addr, value)
+          @data = value
+          return if addr >= 0x5000
+
+          if addr < 0x1000
+            poke_riots(addr, value)
+          else
+            poke_common((((addr >> 12) - 1) << 10) | (addr & 0x03ff), value)
+          end
+        end
+
+        private
+
+        def poke_common(index, value)
+          @common_changes += 1 if @common.peek(index) != value
+          @common.poke(index, value)
+        end
+
+        def peek_riots(addr)
+          @volatile = true if addr & 0x204 == 0x204
+          if addr.anybits?(0x80)
+            addr.anybits?(0x200) ? @control_riot.peek(addr & 0x1f) : @control_riot.read_ram(addr)
+          else
+            addr.anybits?(0x200) ? @data_riot.peek(addr & 0x1f) : @data_riot.read_ram(addr)
+          end
+        end
+
+        def poke_riots(addr, value)
+          if addr.anybits?(0x80)
+            addr.anybits?(0x200) ? @control_riot.poke(addr & 0x1f, value) : @control_riot.write_ram(addr, value)
+          else
+            addr.anybits?(0x200) ? @data_riot.poke(addr & 0x1f, value) : @data_riot.write_ram(addr, value)
+          end
+        end
+      end
+    end
+  end
+end

data/lib/badline/drives/model8050/keyed_state.rb

@@ -0,0 +1,160 @@
+# frozen_string_literal: true
+
+module Badline
+  module Drives
+    class Model8050
+      class Disk
+        # A disk's fields in a keyed snapshot module (BL-D8-DISK, BL-D8-DISK1
+        # for drive 1): the image file's path and how it was opened, the
+        # image as last flushed, embedded under image and image.format, each
+        # track whose cells differ from what the image lays out, as
+        # track<N>, a cell per byte or 256 for a sync, and the tracks
+        # written since the last flush.
+        module KeyedState
+          IMAGE_FORMATS = %w[d80 d82].freeze
+
+          def save_fields(out)
+            image = @image
+            out.text("path", image.path.to_s).bool("read_only", image.read_only?)
+            out.text("image.format", image.is_a?(Storage::D82Image) ? "d82" : "d80")
+            out.bytes("image", image.contents)
+            @tracks.each do |number, cells|
+              out.ints("track#{number}", cells) unless cells == build(number)
+            end
+            out.ints("written", @written.keys)
+          end
+
+          # Puts back the tracks and the writes not yet flushed.
+          def load_track_fields(input)
+            (1..(side_tracks * sides)).each do |number|
+              cells = input.ints("track#{number}", [])
+              @tracks[number] = cells.dup unless cells.empty?
+            end
+            input.ints("written", []).each { |number| @written[number] = true }
+            self
+          end
+        end
+
+        include KeyedState
+
+        # The disk a BL-D8-DISK module holds. A detached reader gets the
+        # image write-protected, and it and a host file that is gone leave
+        # it no path to write back to.
+        def self.from_fields(input, detached: false)
+          path = input.text("path", "")
+          read_only = input.bool("read_only", false) || detached
+          kind = input.choice("image.format", KeyedState::IMAGE_FORMATS, "d80")
+          bytes = input.bytes("image", "".b).bytes
+          path = "" if detached || !File.file?(path)
+          image_class = kind == "d82" ? Storage::D82Image : Storage::D80Image
+          new(image_class.new(path, read_only:, bytes:)).load_track_fields(input)
+        end
+      end
+
+      class Mechanism
+        # The drives' fields in a keyed snapshot module (BL-D8-MECH), a value
+        # a drive in each list: the heads' cylinders, the stepper phases,
+        # each disk's place in its turn and its bit clock, the disk change
+        # under way and the motors, then the byte ready pulse, the byte on
+        # VIA port A and SYNC. The disks load from their own modules.
+        module KeyedState
+          def save_fields(out)
+            out.ints("cylinders", @cylinders).ints("phases", @phases).ints("positions", @positions)
+            out.ints("bit_clocks", @clocks).ints("changing", @changing)
+            out.ints("motors", @motors.map { |on| on ? 1 : 0 }).ints("syncs", @syncs.map { |low| low ? 1 : 0 })
+            out.bool("so_pending", @so_pending).bool("ca1_low", @ca1_low).int("data_in", @data_in)
+          end
+
+          def load_fields(input, disks)
+            @disks = disks
+            input.ints_into("cylinders", @cylinders)
+            input.ints_into("phases", @phases)
+            input.ints_into("positions", @positions)
+            input.ints_into("bit_clocks", @clocks)
+            input.ints_into("changing", @changing)
+            @motors = input.ints("motors", [0, 0]).map { |on| on == 1 }
+            @syncs = input.ints("syncs", [0, 0]).map { |low| low == 1 }
+            @so_pending = input.bool("so_pending", @so_pending)
+            @ca1_low = input.bool("ca1_low", @ca1_low)
+            @data_in = input.byte("data_in", @data_in)
+          end
+        end
+
+        include KeyedState
+      end
+
+      # The unit's own fields in a keyed snapshot module (BL-D8): its model,
+      # its clock phase and cycle count, each bus's last byte, and the
+      # controller's lines as the port latched them, under ieee.*. A save
+      # settles the unit first, so it is awake; a load finds its passes
+      # afresh.
+      module KeyedState
+        def save_fields(out)
+          settle!
+          out.text("model", model_name).int("phase", @phase).int("cycles", @cycles)
+          out.int("ip_data", @ip_bus.data).int("fdc_data", @fdc_bus.data)
+          out.int("ieee.host", @ieee_port.host)
+          out
+        end
+
+        def load_fields(input)
+          settle!
+          input.choice("model", [model_name], model_name)
+          @phase = input.int("phase", @phase)
+          @cycles = input.int("cycles", @cycles)
+          @ip_bus.data = input.byte("ip_data", @ip_bus.data)
+          @fdc_bus.data = input.byte("fdc_data", @fdc_bus.data)
+          @ieee_port.host = input.int("ieee.host", @ieee_port.host)
+        end
+
+        # The unit as modules of its own, named from `name` (BL-D8 for
+        # device 8): its own fields, the common RAM, UC1 and UE1 with their
+        # RAM, each processor, the VIA, the 6530, the drives and each disk
+        # in, drive 1's as -DISK1.
+        def save_modules(sections, name)
+          sections << Snapshot::Keyed.section(name) { |out| save_fields(out) }
+          sections << Snapshot::Keyed.section("#{name}-COMMON") { |out| @common.save_fields(out, "ram") }
+          sections << Snapshot::Keyed.section("#{name}-RIOT1") { |out| @data_riot.save_fields(out) }
+          sections << Snapshot::Keyed.section("#{name}-RIOT2") { |out| @control_riot.save_fields(out) }
+          sections << Snapshot::Keyed.section("#{name}-IPCPU") { |out| @ip_cpu.save_fields(out) }
+          sections << Snapshot::Keyed.section("#{name}-FDCCPU") { |out| @fdc_cpu.save_fields(out) }
+          sections << Snapshot::Keyed.section("#{name}-VIA") { |out| @via.save_fields(out) }
+          sections << Snapshot::Keyed.section("#{name}-RRIOT") { |out| @rriot.save_fields(out) }
+          sections << Snapshot::Keyed.section("#{name}-MECH") { |out| @mechanism.save_fields(out) }
+          [0, 1].each do |drive|
+            disk = @mechanism.disk(drive)
+            sections << Snapshot::Keyed.section(disk_module(name, drive)) { |out| disk.save_fields(out) } if disk
+          end
+          sections
+        end
+
+        # The unit from its modules, `input` being its own. No disk module
+        # means no disk in that drive.
+        def load_modules(modules, input, name)
+          load_fields(input)
+          @common.load_fields(modules.required("#{name}-COMMON"), "ram")
+          @data_riot.load_fields(modules.required("#{name}-RIOT1"))
+          @control_riot.load_fields(modules.required("#{name}-RIOT2"))
+          @ip_cpu.load_fields(modules.required("#{name}-IPCPU"))
+          @fdc_cpu.load_fields(modules.required("#{name}-FDCCPU"))
+          @via.load_fields(modules.required("#{name}-VIA"))
+          @rriot.load_fields(modules.required("#{name}-RRIOT"))
+          disks = [0, 1].map do |drive|
+            disk = modules.optional(disk_module(name, drive))
+            disk.nil? ? nil : Disk.from_fields(disk, detached: modules.detached?)
+          end
+          @mechanism.load_fields(modules.required("#{name}-MECH"), disks)
+          @via.restored!
+          @ip_cpu.restored!
+          @fdc_cpu.restored!
+        end
+
+        private
+
+        def disk_module(name, drive) = drive.zero? ? "#{name}-DISK" : "#{name}-DISK1"
+      end
+
+      include KeyedState
+    end
+  end
+end

data/lib/badline/drives/model8050/mechanism.rb

@@ -0,0 +1,230 @@
+# frozen_string_literal: true
+
+module Badline
+  module Drives
+    class Model8050
+      # The unit's two drives as the floppy controller sees them through
+      # the VIA and the 6530 (schematic 8050001, sheets 2 and 3).
+      #
+      # VIA port B runs the drives: PB5 drive 0's motor and PB4 drive 1's,
+      # each on while low, PB2-3 drive 0's stepper phases and PB0-1 drive
+      # 1's, and PB7 reads SYNC, low while ten one bits sit in the shift
+      # register. The 6530's port B picks the drive on PB0, the zone on
+      # PB1-2 and the side on PB4, low for the second, and reads write
+      # protect on PB3, high while the disk can't be written, and the sides
+      # on PB6, low for two, which jumper E3 grounds on the 8250. Its port
+      # A holds the byte to write.
+      #
+      # Each phase change moves the head a track: the controller steps
+      # through the Gray code 00, 10, 11, 01 outward and back the other way
+      # inward ($FF9C), and bumps the head against track 1 with 92 steps
+      # out.
+      #
+      # A turning disk passes one byte cell under the head every ten bit
+      # cells, at 6 MHz divided by 16 less the track's zone, and the byte
+      # cells come round 300 times a minute (Disk). Each data cell ends in
+      # byte ready, which latches the GCR ROM's byte into VIA port A through
+      # CA1 and pulses the controller's SO pin; a sync cell holds SYNC low
+      # for the cell after it instead. While the VIA's CB2 is low the drive
+      # writes: each cell takes the 6530's port A, or a sync while CA2 is
+      # high, and still ends in byte ready.
+      #
+      # A disk going in or out passes the write-protect sensor, which the
+      # controller watches for a disk change: it reads high for a while.
+      class Mechanism
+        WRITE_PROTECT = 0x08
+        ONE_SIDE = 0x40
+
+        # The cycles the write-protect sensor reads high as a disk goes in
+        # or out, ten of the controller's 5 ms interrupts.
+        CHANGE_CYCLES = 50_000
+
+        attr_reader :sides, :data_in, :cylinders, :so_pending
+        attr_accessor :via, :rriot
+
+        def initialize(sides:)
+          @sides = sides
+          @via = nil
+          @rriot = nil
+          @disks = [nil, nil]
+          @cylinders = [0, 0]
+          @phases = [0, 0]
+          @positions = [0, 0]
+          @clocks = [0, 0]
+          @changing = [0, 0]
+          @motors = [false, false]
+          @so_pending = false
+          @data_in = 0xff
+          @syncs = [false, false]
+          @ca1_low = false
+        end
+
+        # The Disk in +drive+, 0 or 1, or nil.
+        def disk(drive = 0) = @disks[drive]
+
+        def insert(disk, drive = 0)
+          @disks[drive]&.flush
+          @disks[drive] = disk
+          @changing[drive] = CHANGE_CYCLES
+        end
+
+        def flush
+          @disks.each { |disk| disk&.flush }
+        end
+
+        def motor_on?(drive = 0) = @motors[drive]
+
+        # The track under +drive+'s head on the side the 6530 picks.
+        def track(drive = 0)
+          side = drive == selected_drive ? selected_side : 0
+          @cylinders[drive] + 1 + (side * Storage::D80Image::SIDE_TRACKS)
+        end
+
+        def cycle!
+          if @ca1_low
+            @ca1_low = false
+            @via.ca1 = true
+          end
+          drives = @via.port_b_output
+          turn(0, drives.nobits?(0x20), (drives >> 2) & 0x03)
+          turn(1, drives.nobits?(0x10), drives & 0x03)
+        end
+
+        # Whether a cycle would change nothing: both motors off, no disk
+        # going in or out, and no byte ready under way.
+        def quiet?
+          !@motors[0] && !@motors[1] && @changing[0].zero? && @changing[1].zero? && !@ca1_low && !@so_pending
+        end
+
+        # What the drives hold, for comparing them at two points.
+        def idle_state = [*@cylinders, *@phases, *@motors, *@syncs, @data_in]
+
+        # Whether byte ready pulses the controller's SO pin this cycle,
+        # which takes the pulse.
+        def take_so
+          so = @so_pending
+          @so_pending = false
+          so
+        end
+
+        # Whether ten one bits sit in the shift register, off the selected
+        # drive's head.
+        def sync? = @syncs[selected_drive]
+
+        # The 6530's port B inputs.
+        def status_lines
+          lines = 0xff
+          lines &= ~WRITE_PROTECT unless write_protected?(selected_drive)
+          @sides == 2 ? lines & ~ONE_SIDE : lines
+        end
+
+        private
+
+        def selected_drive = @rriot.port_b_output & 0x01
+
+        def selected_side = @sides == 2 && @rriot.port_b_output.nobits?(0x10) ? 1 : 0
+
+        def write_protected?(drive)
+          return true if @changing[drive].positive?
+
+          disk = @disks[drive]
+          disk ? disk.write_protected? : false
+        end
+
+        def turn(drive, motor, phase)
+          @changing[drive] -= 1 if @changing[drive].positive?
+          step(drive, phase) if phase != @phases[drive]
+          motor_off(drive) if @motors[drive] && !motor
+          @motors[drive] = motor
+          return @syncs[drive] = false unless motor && @disks[drive]
+
+          clock = @clocks[drive] + 6
+          byte = 10 * (16 - Disk.zone_of(track(drive)))
+          if clock >= byte
+            clock -= byte
+            pass_cell(drive)
+          end
+          @clocks[drive] = clock
+        end
+
+        # Gray code index of a phase pair: 00, 10, 11, 01.
+        def phase_index(phase) = [0, 3, 1, 2][phase]
+
+        def step(drive, phase)
+          change = (phase_index(phase) - phase_index(@phases[drive])) & 0x03
+          @phases[drive] = phase
+          cylinder = @cylinders[drive]
+          if change == 1
+            cylinder -= 1
+          elsif change == 3
+            cylinder += 1
+          end
+          @cylinders[drive] = cylinder.clamp(0, Storage::D80Image::SIDE_TRACKS - 1)
+        end
+
+        def motor_off(drive)
+          @disks[drive]&.flush
+        end
+
+        # A cell has passed under +drive+'s head.
+        def pass_cell(drive)
+          disk = @disks[drive]
+          number = track(drive)
+          cells = disk.track(number)
+          return unless cells
+
+          position = @positions[drive] % cells.length
+          @positions[drive] = position + 1
+          return unless drive == selected_drive
+
+          writing? ? write_cell(drive, disk, number, cells, position) : read_cell(drive, cells, position)
+        end
+
+        def writing? = (@via.pcr & 0xe0) == 0xc0
+
+        def read_cell(drive, cells, position)
+          cell = cells[position]
+          @syncs[drive] = cell == Disk::SYNC
+          byte_ready(cell) unless cell == Disk::SYNC
+        end
+
+        def write_cell(drive, disk, number, cells, position)
+          cells[position] = @via.pcr.allbits?(0x0e) ? Disk::SYNC : @rriot.port_a_output
+          disk.written(number)
+          @syncs[drive] = false
+          byte_ready(@data_in)
+        end
+
+        def byte_ready(byte)
+          @data_in = byte
+          @via.ca1 = false
+          @ca1_low = true
+          @so_pending = true
+        end
+      end
+
+      # VIA port A reads the decoded byte, and PB7 SYNC, low while the
+      # shift register holds a sync.
+      class ReadLines
+        def initialize(mechanism)
+          @mechanism = mechanism
+        end
+
+        def read_a(_lines) = @mechanism.data_in
+
+        def read_b(_lines) = @mechanism.sync? ? 0x7f : 0xff
+      end
+
+      # The 6530's port B inputs from the drives.
+      class StatusLines
+        def initialize(mechanism)
+          @mechanism = mechanism
+        end
+
+        def read_a(_lines) = 0xff
+
+        def read_b(_lines) = @mechanism.status_lines
+      end
+    end
+  end
+end

data/lib/badline/drives/model8050/parts.rb

@@ -0,0 +1,37 @@
+# frozen_string_literal: true
+
+module Badline
+  module Drives
+    class Model8050
+      # Each chip a class of its own, so each keeps one type of peripheral.
+
+      # UC1, on the IEEE-488 data lines.
+      class DataRIOT < Chips::RIOT
+      end
+
+      # UE1, on the control lines, the jumpers and the LEDs.
+      class ControlRIOT < Chips::RIOT
+      end
+
+      # UM3, the controller's VIA, at $0040.
+      class ControllerVIA < Chips::VIA
+      end
+
+      # UK3, the controller's 6530, its ROM the controller's program.
+      class ControllerRRIOT < Chips::RRIOT
+      end
+
+      # The interface processor's 6502, UN1, on the IPBus.
+      class IPCPU
+        include Badline::Chips::CPU::Core
+        include Engine::IdleCPU
+      end
+
+      # The floppy controller's 6502, UH3, on the FDCBus.
+      class FDCCPU
+        include Badline::Chips::CPU::Core
+        include Engine::IdleCPU
+      end
+    end
+  end
+end