badline 0.16.0 → 0.17.0

data/lib/badline/cbm2.rb

@@ -0,0 +1,267 @@
+# frozen_string_literal: true
+
+require "badline/chips/acia"
+require "badline/chips/tpi"
+require "badline/cbm2/model"
+require "badline/cbm2/p500/model"
+require "badline/cbm2/bus"
+require "badline/cbm2/cpu"
+require "badline/cbm2/acia"
+require "badline/cbm2/keyboard_ports"
+require "badline/cbm2/crtc_video"
+require "badline/cbm2/sid_page"
+require "badline/cbm2/ieee_layout"
+require "badline/cbm2/ieee_traps"
+require "badline/cbm2/ieee_ports"
+require "badline/cbm2/ieee_drive"
+require "badline/snapshot/cbm2_setup"
+require "badline/cbm2/keyed_state"
+require "badline/cbm2/keyed_modules"
+require "badline/cbm2/p500"
+
+module Badline
+  # The Commodore CBM-II's B series, the 610, 620, 710 and 720: a 6509 at
+  # 2 MHz on a bus of sixteen 64K segments (Bus, CPU), a 6845 CRTC at
+  # $D800, a 6581 SID at $DA00, a 6526 CIA at $DC00, a 6551 ACIA at $DD00
+  # and two 6525 TPIs at $DE00 and $DF00. Nothing halts the CPU: the video
+  # reads its own screen RAM between the CPU's accesses.
+  #
+  # TPI1 is the interrupt controller, and its IRQ the CPU's only one. Its
+  # inputs are the mains on I0, the IEEE-488 bus's SRQ on I1, the CIA on
+  # I2, the coprocessor board on I3 and the ACIA on I4, each pulled low to
+  # interrupt. The mains, 50 or 60 Hz, is the system tick, and feeds the
+  # CIA's TOD pin too. TPI2 scans the key matrix and reads the model's
+  # jumpers (KeyboardPorts), and type_text types through the editor's
+  # keyboard buffer in segment 15.
+  #
+  # The DRAM's refresh takes the CPU's clock away for a cycle (Refresh),
+  # every 20 cycles or so: about 4.5% of its time.
+  #
+  # The CRTC paints its picture from the screen RAM and the character ROM
+  # (CRTCVideo). Device 8 answers through traps on the KERNAL's IEEE-488
+  # primitives (IEEETraps), or a true 2031, 8050 or 8250 on the bus
+  # (IEEEPorts, IEEEDrive) answers. It runs headless.
+  class CBM2
+    include Machine::KeyboardBuffer
+    include Machine::Clocking
+    include Machine::Settling
+    include IEEETraps
+    include IEEEDrive
+
+    CLOCK_HZ = 2_000_000
+
+    # The DRAM refresh (sheet 3 of schematic 8256043, U89 and U55): a
+    # counter of the CPU's cycles asks for a refresh once it reaches 20,
+    # stops there, and the refresh comes on the next opcode fetch (SYNC),
+    # which it holds off a cycle with RDY while it stops the CPU's clock,
+    # and clears the counter.
+    REFRESH_COUNT = 20
+
+    # The segment BASIC keeps its program text in.
+    TEXT_SEGMENT = 1
+
+    # The editor's keyboard buffer in segment 15, KEYD at $03AB and NDX at
+    # $D1, the same in 901244-03b and -04a.
+    KEYBOARD_LAYOUT = Machine::KeyboardBuffer::Layout.new(address: 0x03ab, count: 0xd1, capacity: 10)
+
+    attr_reader :model, :bus, :cpu, :crtc, :sid, :cia, :acia, :tpi1, :tpi2, :keyboard, :ieee, :mains_hz, :kernal,
+                :cycles, :init_threshold
+
+    def ram = @bus.ram
+
+    # Whether the DRAM refresh takes its cycles from the CPU.
+    def refresh? = @refreshing
+
+    def family = :cbm2
+
+    # Reads and writes memory as the CPU sees it, in its execution segment.
+    def peek(addr) = @bus.peek(addr)
+
+    def poke(addr, value) = @bus.poke(addr, value)
+
+    def install_debug_register(&) = @bus.install_debug_register(&)
+
+    def keyboard_buffer = KEYBOARD_LAYOUT
+
+    def sound_source = @sid
+
+    # The Canvas a front end shows (CRTCVideo).
+    def video = @video.canvas
+
+    # What paints the picture.
+    def crtc_video = @video
+
+    # +model+ names one of Model::ALL, +kernal+ one of Model::KERNALS, and
+    # +mains_hz+ the mains, 50 or 60, which also sets a 600's jumper for
+    # the editor's 60 Hz CRTC table. +refresh+ false leaves out the DRAM
+    # refresh's stolen cycles.
+    def initialize(model: Model::DEFAULT, kernal: "04a", mains_hz: 50, refresh: true, debug: false)
+      @model = Model.named(model)
+      raise ArgumentError, "no CBM-II KERNAL named #{kernal}" unless Model::KERNALS.key?(kernal)
+      raise ArgumentError, "the mains is 50 or 60 Hz, not #{mains_hz}" unless [50, 60].include?(mains_hz)
+
+      @kernal = kernal
+      @mains_hz = mains_hz
+      @bus = Bus.new(basic: Model.basic(@model, kernal), kernal: Model::KERNALS.fetch(kernal),
+                     ram_segments: @model.ram_segments)
+      @ieee = IEEEPorts.new(Drives::IEEEBus.new)
+      @tpi1 = Chips::TPI.new(peripheral: @ieee)
+      registers = Array.new(Chips::CRTC::MASKS.length, 0)
+      @video = CRTCVideo.new(ROM.read(@model.characters), @bus.screen, @tpi1, registers,
+                             high_profile: @model.high_profile)
+      @crtc = Chips::CRTC.new(@video, registers:)
+      @sid = Chips::SID.new(model: :mos6581, at: 0xda00)
+      @cia = Chips::CIA.new(start: 0xdc00, peripheral: @ieee.data, region: Region::PAL.with(clock_hz: CLOCK_HZ),
+                            tod_hz: mains_hz)
+      @ieee.connect(@cia, @tpi1)
+      @acia = ACIA.new(self, CLOCK_HZ)
+      @keyboard = Input::Keyboard.new(matrix: KeyboardPorts::MATRIX)
+      keyboard_ports = KeyboardPorts.new(@keyboard, jumpers)
+      @tpi2 = Chips::TPI.new(peripheral: keyboard_ports)
+      keyboard_ports.connect(@tpi2)
+      map_io
+      @cpu = CPU.new(@bus, debug:)
+      @cycles = 0
+      @mains_half_period = CLOCK_HZ / (2 * mains_hz)
+      @mains_countdown = @mains_half_period
+      @mains_high = true
+      @refresh = 0
+      @refreshing = refresh
+      @acia_irq = false
+      @acia_due = Chips::ACIA::NEVER
+      @init_handlers = []
+      @pending_keys = nil
+      @dos = nil
+      @ieee_trap = nil
+      @capture_output = nil
+      init_ieee_drives
+      @init_threshold = boot_cycles
+    end
+
+    # The model, its RAM and its mains as the pause menu names them, such
+    # as "610, 128K RAM, 50 HZ".
+    def model_label = "#{@model.name}, #{@model.ram_kb}K RAM, #{@mains_hz} HZ"
+
+    # The 2 MHz clock and the frame of the editor's CRTC table, nominal,
+    # since a program can program the CRTC otherwise, and all of the
+    # Canvas, two dots to a window pixel.
+    def timing
+      cycles_per_line, lines_per_frame = crtc_frame
+      canvas = @video.canvas
+      Timing.new(clock_hz: CLOCK_HZ, cycles_per_line:, lines_per_frame:, crop: [0, 0, canvas.width, canvas.height],
+                 pixel_width: 1, dots: 2)
+    end
+
+    # The CRTC and the mains ahead of the chips, then TPI1's inputs from
+    # the CIA and the ACIA, and the CPU last.
+    def cycle!
+      handle_init if @cycles == @init_threshold
+      feed_keyboard if @pending_keys
+
+      @crtc.cycle!
+      tick_mains
+      @cia.cycle!
+      @sid.cycle!
+      @acia.run!(@cycles) if @cycles >= @acia_due
+      tpi1 = @tpi1
+      tpi1.interrupt_line(2, !@cia.interrupted?)
+      tpi1.interrupt_line(4, !@acia_irq)
+      @cpu.irq = tpi1.irq?
+      if @refreshing && @refresh >= REFRESH_COUNT && @cpu.boundary?
+        @refresh = 0
+        @cpu.stall!
+      else
+        @refresh += 1 if @refresh < REFRESH_COUNT
+        @cpu.cycle!
+      end
+      clock_ieee_drives
+
+      @cycles += 1
+    end
+
+    # The ACIA's IRQ line, and the cycle it next has something to do at.
+    def acia_changed(irq, due)
+      @acia_irq = irq
+      @acia_due = due
+    end
+
+    # The RES line reaches the CPU and its segment registers, the CRTC, the
+    # SID, the CIA, the ACIA and both TPIs.
+    def reset!
+      @crtc.reset!
+      @sid.reset!
+      @cia.reset!
+      @acia.reset!
+      @tpi1.reset!
+      @tpi2.reset!
+      @bus.reset!
+      @cpu.reset!
+      reset_ieee_drives
+    end
+
+    # Puts a program file's bytes where its first two say in BASIC's text
+    # segment, segment 1, and returns that address.
+    def load_prg(data)
+      load_addr = data[0] | (data[1] << 8)
+      bytes = data[2..] || []
+      bytes = bytes[0, 0x10000 - load_addr] if load_addr + bytes.length > 0x10000
+      bytes.each_with_index { |byte, i| @bus.poke_bank(TEXT_SEGMENT, load_addr + i, byte) }
+      load_addr
+    end
+
+    # Puts a cartridge's ROM chips in (Bus#attach_cartridge) and switches
+    # the machine off and on, for the KERNAL to find it as it starts.
+    def attach_cartridge(chips)
+      @bus.attach_cartridge(chips)
+      power_cycle!
+    end
+
+    # Switches the machine off and on: RAM starts cleared, and the RES
+    # line resets everything else.
+    def power_cycle!
+      @bus.power_on!
+      reset!
+    end
+
+    private
+
+    # PC6 and PC7 as the board's jumpers drive them.
+    def jumpers
+      return 0x80 if @model.high_profile
+
+      @mains_hz == 60 ? 0x40 : 0x00
+    end
+
+    def map_io
+      @bus.map_io(0xd8, @crtc)
+      @bus.map_io(0xda, SIDPage.new(@sid))
+      @bus.map_io(0xdc, @cia)
+      @bus.map_io(0xdd, @acia)
+      @bus.map_io(0xde, @tpi1)
+      @bus.map_io(0xdf, @tpi2)
+    end
+
+    # The mains, low for half its period and high for the other half, on
+    # TPI1's I0, whose falling edge latches the tick.
+    def tick_mains
+      @mains_countdown -= 1
+      return unless @mains_countdown.zero?
+
+      @mains_countdown = @mains_half_period
+      @mains_high = !@mains_high
+      @tpi1.interrupt_line(0, @mains_high)
+    end
+
+    # The characters a line and the lines a frame of the editor's table:
+    # the 700's, or the 600's 50 or 60 Hz one.
+    def crtc_frame
+      return [108, 367] if @model.high_profile
+
+      @mains_hz == 60 ? [127, 262] : [128, 313]
+    end
+
+    # The cycle by which the KERNAL has tested the RAM board, about 3.7
+    # million cycles a segment with the refresh, and BASIC printed READY, with a margin.
+    def boot_cycles = 1_000_000 + (3_800_000 * @model.ram_segments.length)
+  end
+end

data/lib/badline/{plus4 → chips}/acia/frames.rb

@@ -1,7 +1,7 @@
 # frozen_string_literal: true
 
 module Badline
-  class Plus4
+  module Chips
     class ACIA
       # A character's frame and how long it takes. A start bit, 5 to 8
       # data bits, a parity bit where the command enables one, and the stop

data/lib/badline/chips/acia/keyed_state.rb

@@ -0,0 +1,47 @@
+# frozen_string_literal: true
+
+module Badline
+  module Chips
+    class ACIA
+      # The registers, the status, the shift register and when the
+      # transmitter's character ends, in a keyed snapshot module (BL-ACIA).
+      # What the device on the line has still to send stays with the
+      # host, and the receiver starts on it again once loaded (#restored!).
+      # A snapshot from before the transmitter's timing was saved starts
+      # its character clock on load.
+      module KeyedState
+        def save_fields(out)
+          out.int("command", @command).int("control", @control).int("errors", @errors)
+          out.bool("receiver_full", @receiver_full).bool("transmitter_empty", @transmitter_empty).bool("irq", @irq)
+          out.int("receive_data", @receive_data).int("transmit_data", @transmit_data).int("shifting", @shifting)
+          out.int("transmit_at", @transmit_at).int("transmit_remainder", @transmit_remainder)
+        end
+
+        def load_fields(input)
+          @command = input.byte("command", @command)
+          @control = input.byte("control", @control)
+          @errors = input.masked("errors", 0, PARITY_ERROR | FRAMING_ERROR | OVERRUN)
+          @receiver_full = input.bool("receiver_full", false)
+          @transmitter_empty = input.bool("transmitter_empty", true)
+          @irq = input.bool("irq", false)
+          @receive_data = input.byte("receive_data", 0)
+          @transmit_data = input.byte("transmit_data", 0)
+          @shifting = input.int("shifting", IDLE)
+          @transmit_remainder = input.int("transmit_remainder", 0)
+          transmit_at = input.optional_int("transmit_at")
+          @transmit_at = transmit_at || NEVER
+          @clock_lost = transmit_at.nil?
+        end
+
+        def restored!
+          @receive_at = NEVER
+          @lines = modem_lines
+          start_transmitting if @clock_lost && transmitter_on?
+          @clock_lost = false
+          start_receiving
+          changed
+        end
+      end
+    end
+  end
+end

data/lib/badline/chips/acia.rb

@@ -0,0 +1,307 @@
+# frozen_string_literal: true
+
+require "badline/chips/acia/frames"
+require "badline/chips/acia/keyed_state"
+
+module Badline
+  module Chips
+    # The 6551 ACIA, its four registers repeated through the page it is
+    # decoded in:
+    #
+    # 0 - read the receiver's data, write the transmitter's
+    # 1 - read the status, write a programmed reset
+    # 2 - the command register
+    # 3 - the control register
+    #
+    # Status: bit 0 a parity error, 1 a framing error, 2 an overrun, 3 the
+    # receiver full, 4 the transmitter empty, 5 DCD and 6 DSR as their pins
+    # read (1 high, not asserted), 7 an interrupt. Reading it clears bit 7.
+    #
+    # Command: bit 0 DTR, which also enables the receiver and every
+    # interrupt, bit 1 set disables the receiver's interrupt, bits 2-3 the
+    # transmitter (00 off with RTS high, 01 on with its interrupt, 10 on
+    # without, 11 sending a break), bit 4 echoes what is received, bits 5-7
+    # the parity.
+    #
+    # Control: bits 0-3 the baud rate from the 1.8432 MHz crystal (0, the
+    # 16x external clock, runs straight from the crystal, 115,200 baud),
+    # bit 4 the receiver's clock (0 the RxC pin, which nothing drives, so
+    # the receiver hears nothing), bits 5-6 the word length (8 down to 5
+    # bits) and bit 7 the stop bits (Frames).
+    #
+    # The transmitter runs in whole characters while it is on: at the end
+    # of each it hands the character it shifted out to the line, moves a
+    # waiting byte from the data register into the shift register and sets
+    # the transmitter empty, and with its interrupt on interrupts while the
+    # register is empty, every character until a byte comes. The first
+    # character ends a character's time after the transmitter comes on.
+    # The receiver takes a character's time for each byte the line sends,
+    # and a byte that arrives while the last is unread is lost to an
+    # overrun. The receiver full, and DCD or DSR changing, interrupt unless
+    # bit 1 disables it. CTS is held asserted, so the transmitter is always
+    # clear to send.
+    #
+    # What is on the other end of the line (#plug): nothing, where DCD and
+    # DSR read high and what is sent goes nowhere; a terminal, which
+    # asserts DCD and DSR, sends what the host feeds it (#feed) while DTR is
+    # asserted and keeps what it receives for the host to drain (#drain);
+    # or a loopback plug, which returns TxD to RxD and DTR to DSR and DCD.
+    #
+    # The machine runs the ACIA at the cycle it next has something to do
+    # (#due) through #run!, and learns its IRQ line and that cycle from
+    # `clock`'s #acia_changed, whose #cycles is the time, counted at
+    # `clock_hz`. Each machine has a subclass of its own, so `clock` keeps
+    # one type in each.
+    class ACIA
+      include Frames
+      include KeyedState
+
+      PARITY_ERROR = 0x01
+      FRAMING_ERROR = 0x02
+      OVERRUN = 0x04
+      RECEIVER_FULL = 0x08
+      TRANSMITTER_EMPTY = 0x10
+      DCD = 0x20
+      DSR = 0x40
+      IRQ = 0x80
+
+      NOTHING = 0
+      TERMINAL = 1
+      LOOPBACK = 2
+
+      # No shift in progress.
+      IDLE = -1
+
+      # Far enough ahead that it never comes.
+      NEVER = 1 << 60
+
+      attr_reader :command, :control, :device, :due
+
+      def initialize(clock, clock_hz)
+        @clock = clock
+        @clock_hz = clock_hz
+        @device = NOTHING
+        @incoming = []
+        @received = []
+        reset!
+      end
+
+      # The RES line: every register cleared, the transmitter empty and
+      # both shift registers stopped.
+      def reset!
+        @command = 0
+        @control = 0
+        @errors = 0
+        @receiver_full = false
+        @transmitter_empty = true
+        @irq = false
+        @receive_data = 0
+        @transmit_data = 0
+        @shifting = IDLE
+        @transmit_at = NEVER
+        @transmit_remainder = 0
+        @receive_at = NEVER
+        @receive_remainder = 0
+        @clock_lost = false
+        @lines = modem_lines
+        changed
+      end
+
+      def irq? = @irq
+
+      # DTR and RTS as asserted, low on the pins.
+      def dtr? = @command.anybits?(0x01)
+
+      def rts? = @command.anybits?(0x0c)
+
+      # Whether the transmitter sends a break, holding TxD low.
+      def break? = @command & 0x0c == 0x0c
+
+      # Plugs NOTHING, a TERMINAL or a LOOPBACK plug into the user port.
+      def plug(device)
+        @device = device
+        @incoming.clear
+        lines_changed
+        start_receiving
+        changed
+      end
+
+      # Bytes the terminal sends, one a character's time while DTR is
+      # asserted.
+      def feed(bytes)
+        return unless @device == TERMINAL
+
+        @incoming.concat(bytes)
+        start_receiving
+        changed
+      end
+
+      # What the terminal has received since the last drain.
+      def drain
+        received = @received
+        @received = []
+        received
+      end
+
+      # Runs what falls due up to cycle `now`: the transmitter's character
+      # ends, then the receiver's.
+      def run!(now)
+        end_character while @transmit_at <= now
+        receive_character while @receive_at <= now
+        changed
+      end
+
+      def peek(addr)
+        case addr & 0x03
+        when 0
+          @receiver_full = false
+          @receive_data
+        when 1 then read_status
+        when 2 then @command
+        else @control
+        end
+      end
+
+      def poke(addr, value)
+        case addr & 0x03
+        when 0 then write_data(value)
+        when 1 then write_command(@command & 0xe0, clear_overrun: true)
+        when 2 then write_command(value)
+        else @control = value
+        end
+        changed
+      end
+
+      # The status as a read finds it, without clearing the interrupt.
+      def status
+        status = @errors | (@lines & (DCD | DSR))
+        status |= RECEIVER_FULL if @receiver_full
+        status |= TRANSMITTER_EMPTY if @transmitter_empty
+        @irq ? status | IRQ : status
+      end
+
+      private
+
+      def read_status
+        value = status
+        @irq = false
+        changed
+        value
+      end
+
+      def write_data(value)
+        @transmit_data = value
+        @transmitter_empty = false
+      end
+
+      def write_command(value, clear_overrun: false)
+        was_on = transmitter_on?
+        @command = value
+        @errors &= ~OVERRUN if clear_overrun
+        start_transmitting if transmitter_on? && !was_on
+        stop_transmitting unless transmitter_on? || @shifting != IDLE
+        lines_changed
+        start_receiving
+      end
+
+      def transmitter_on?
+        control = @command & 0x0c
+        control != 0 && control != 0x0c
+      end
+
+      def interrupts? = @command.anybits?(0x01)
+
+      def receiver_interrupts? = @command & 0x03 == 0x01
+
+      def transmitter_interrupts? = @command & 0x0d == 0x05
+
+      def receiving? = dtr? && @control.anybits?(0x10)
+
+      def start_transmitting
+        @transmit_remainder = 0
+        @transmit_at = after(@clock.cycles, true)
+      end
+
+      def stop_transmitting
+        @transmit_at = NEVER
+      end
+
+      # A character's end: the character shifted out goes to the line, and
+      # the transmitter takes the next byte or interrupts while it has none.
+      def end_character
+        sent = @shifting
+        @shifting = IDLE
+        deliver(sent) unless sent == IDLE
+        on = transmitter_on?
+        if on && !@transmitter_empty
+          @shifting = @transmit_data & word_mask
+          @transmitter_empty = true
+        end
+        @irq = true if on && @transmitter_empty && transmitter_interrupts?
+        if on || @shifting != IDLE
+          @transmit_at = after(@transmit_at, true)
+        else
+          stop_transmitting
+        end
+      end
+
+      def deliver(byte)
+        case @device
+        when TERMINAL then @received << byte
+        when LOOPBACK then take(byte) if receiving?
+        end
+      end
+
+      def start_receiving
+        return unless @receive_at == NEVER && !@incoming.empty? && receiving?
+
+        @receive_remainder = 0
+        @receive_at = after(@clock.cycles, false)
+      end
+
+      def receive_character
+        byte = @incoming[0]
+        @incoming.delete_at(0)
+        take(byte)
+        @receive_at = !@incoming.empty? && receiving? ? after(@receive_at, false) : NEVER
+      end
+
+      # A whole character in from RxD: into the data register, or lost to
+      # an overrun while the last is unread. In echo mode it goes back out
+      # to the terminal.
+      def take(byte)
+        if @receiver_full
+          @errors |= OVERRUN
+        else
+          @receive_data = byte & word_mask
+          @receiver_full = true
+          @errors = 0
+        end
+        @received << byte if @device == TERMINAL && @command & 0x1c == 0x10
+        @irq = true if receiver_interrupts?
+      end
+
+      # DCD and DSR as the device drives them, interrupting on a change.
+      def lines_changed
+        lines = modem_lines
+        return if lines == @lines
+
+        @lines = lines
+        @irq = true if receiver_interrupts?
+      end
+
+      def modem_lines
+        case @device
+        when TERMINAL then 0
+        when LOOPBACK then dtr? ? 0 : DCD | DSR
+        else DCD | DSR
+        end
+      end
+
+      def changed
+        @due = [@transmit_at, @receive_at].min
+        @clock.acia_changed(@irq && interrupts?, @due)
+      end
+    end
+  end
+end

data/lib/badline/chips/crtc.rb

@@ -23,7 +23,8 @@ module Badline
     #   row ends after the line where it equals R9; past R9 it runs on to
     #   31 and wraps.
     # - The row counter (seven bits) counts rows to R4. R5 more lines of
-    #   vertical adjust follow, then the frame starts again. The display
+    #   vertical adjust follow, then the frame starts again. The line
+    #   counter counts them, and they end no row, past R9 or not. The display
     #   stops at the start of the row the counter equals R6, and comes back
     #   at the next frame; vertical sync starts with row R7 and lasts
     #   VSYNC_LINES lines.
@@ -91,7 +92,7 @@ module Badline
         column = @column
         if column == regs[1]
           @column_display = false
-          @row_start = @address if @line == regs[9]
+          @row_start = @address if @line == regs[9] && !@adjusting
         end
         @output.character(@address, @line, @since_hsync) if @column_display && @row_display
         if column == regs[2]