badline 0.13.0 → 0.14.0

data/lib/badline/chips/ted.rb

@@ -0,0 +1,143 @@
+# frozen_string_literal: true
+
+require "badline/chips/ted/timers"
+require "badline/chips/ted/beam"
+
+module Badline
+  module Chips
+    # The TED of the Commodore 264 series, the 7360 and 8360: its registers
+    # at $FF00-$FF1F, the raster, the three timers, the interrupt, the
+    # keyboard latch and the clock it gives the CPU (Beam). It paints no
+    # picture and plays no sound yet: those registers keep what is written
+    # to them.
+    #
+    # The machine clocks it once a single clock cycle, 57 to a line, and
+    # asks it then how many cycles the CPU runs in that one (#cpu_slots)
+    # and whether BA is low (#ba_low?).
+    #
+    # $FF08 is the keyboard latch: a write latches the K0-K7 inputs, which
+    # the keyboard port answers for the byte written (KeyboardPort#latch),
+    # and a read returns them. $FF09 holds the interrupt flags, each
+    # cleared by writing a 1 to it, with bit 7 set while the interrupt
+    # line is pulled. $FF0A holds the mask and bit 8 of the raster compare,
+    # and $FF0B the compare's low byte. $FF13 bit 0 reads whether the CPU
+    # sees ROM at $8000-$FFFF (#rom_selected=). $FF1C and $FF1D read and
+    # set the raster line, and $FF1E reads the horizontal position's top 8
+    # bits.
+    class TED
+      include Timers
+      include Beam
+
+      # The clock a TED is fed, its single clock: the crystal divided by 20
+      # on PAL machines and by 16 on NTSC ones (the Plus/4 hardware manual's
+      # TED datasheet).
+      Profile = Data.define(:name, :clock_hz)
+
+      PAL = Profile.new(name: :pal, clock_hz: 886_724)
+      NTSC = Profile.new(name: :ntsc, clock_hz: 894_886)
+
+      RASTER_FLAG = 0x02
+
+      # The interrupt sources a mask bit can enable: the raster, the light
+      # pen and the three timers.
+      SOURCES = 0x5e
+
+      attr_reader :profile, :interrupt_flags, :interrupt_mask
+
+      # What answers the keyboard latch: an object with #latch(value).
+      attr_writer :keyboard_port
+
+      # Whether the CPU sees ROM at $8000-$FFFF, which $FF13 bit 0 reads.
+      attr_writer :rom_selected
+
+      def initialize(profile = PAL)
+        @profile = profile
+        @keyboard_port = nil
+        @rom_selected = true
+        power_on!
+      end
+
+      def power_on!
+        @registers = Array.new(0x20, 0)
+        @interrupt_flags = 0
+        @interrupt_mask = 0
+        @raster_compare = 0
+        @key_latch = 0xff
+        reset_timers
+        reset_beam
+      end
+
+      # Counts the timers and moves the beam on a cycle, unless $FF07's
+      # freeze bit holds them, then decides the CPU's clock for the cycle.
+      def cycle!
+        unless frozen?
+          count_timers
+          move_beam
+        end
+        decide_clock
+      end
+
+      # Whether the interrupt line is pulled: a flag raised whose mask bit
+      # is set.
+      def irq? = @interrupt_flags.anybits?(@interrupt_mask & SOURCES)
+
+      def peek(addr)
+        register = addr & 0x3f
+        return 0xff if register >= 0x20
+
+        case register
+        when 0x00..0x05 then read_timer(register)
+        when 0x08 then @key_latch
+        when 0x09 then read_interrupt_flags
+        when 0x0a then @interrupt_mask | 0xa0
+        when 0x0b then @raster_compare & 0xff
+        when 0x13 then (@registers[0x13] & 0xfe) | (@rom_selected ? 1 : 0)
+        when 0x1c then 0xfe | (@line >> 8)
+        when 0x1d then @line & 0xff
+        when 0x1e then @column << 2
+        else @registers[register]
+        end
+      end
+
+      def poke(addr, value)
+        register = addr & 0x3f
+        return if register >= 0x20
+
+        @registers[register] = value
+        case register
+        when 0x00..0x05 then write_timer(register, value)
+        when 0x08 then @key_latch = @keyboard_port ? @keyboard_port.latch(value) : 0xff
+        when 0x09 then @interrupt_flags &= ~value
+        when 0x0a then write_interrupt_mask(value)
+        when 0x0b then @raster_compare = (@raster_compare & 0x100) | value
+        when 0x1c then self.line = (@line & 0xff) | ((value & 0x01) << 8)
+        when 0x1d then self.line = (@line & 0x100) | value
+        end
+      end
+
+      private
+
+      # $FF07 bit 5 stops the beam and the timers.
+      def frozen? = @registers[0x07].anybits?(0x20)
+
+      def read_interrupt_flags
+        value = @interrupt_flags | 0x21
+        irq? ? value | 0x80 : value
+      end
+
+      def write_interrupt_mask(value)
+        @interrupt_mask = value & 0x5f
+        @raster_compare = (@raster_compare & 0xff) | ((value & 0x01) << 8)
+      end
+
+      def line=(value)
+        @line = value
+        raster_reached
+      end
+
+      def raster_reached
+        @interrupt_flags |= RASTER_FLAG if @line == @raster_compare
+      end
+    end
+  end
+end

data/lib/badline/chips/tia.rb

@@ -0,0 +1,49 @@
+# frozen_string_literal: true
+
+module Badline
+  module Chips
+    # The 6523 TIA, a tri-port interface adapter: three 8-bit ports, A, B
+    # and C at registers 0-2, each with its direction register at 3-5, a 1
+    # making the pin an output. Its three address lines repeat the
+    # registers every 8 bytes, and registers 6 and 7 read $FF.
+    #
+    # A pin read as an output returns what the port drives, and one read as
+    # an input returns what the other side drives, #inputs, per port.
+    class TIA
+      attr_reader :ports, :directions
+
+      # What the other side drives onto each port's pins.
+      attr_reader :inputs
+
+      def initialize
+        @inputs = [0, 0, 0]
+        reset!
+      end
+
+      def reset!
+        @ports = [0, 0, 0]
+        @directions = [0, 0, 0]
+      end
+
+      def peek(addr)
+        register = addr & 0x07
+        return 0xff if register > 5
+        return @directions[register - 3] if register >= 3
+
+        direction = @directions[register]
+        (@ports[register] & direction) | (@inputs[register] & ~direction & 0xff)
+      end
+
+      def poke(addr, value)
+        register = addr & 0x07
+        return if register > 5
+
+        if register >= 3
+          @directions[register - 3] = value
+        else
+          @ports[register] = value
+        end
+      end
+    end
+  end
+end

data/lib/badline/chips/vdc/keyed_parts.rb

@@ -0,0 +1,105 @@
+# frozen_string_literal: true
+
+module Badline
+  module Chips
+    class VDC
+      class Raster
+        # The raster's fields in a keyed snapshot module, under `prefix`:
+        # the frame count, where the beam is in the character rows and the
+        # frame, and the frame's size and sync as it latched them.
+        module KeyedState
+          def save_fields(out, prefix)
+            out.int("#{prefix}frame", @frame).int("#{prefix}row", @row).int("#{prefix}row_line", @row_line)
+            out.bool("#{prefix}adjusting", @adjusting).int("#{prefix}frame_line", @frame_line)
+            out.int("#{prefix}frame_lines", @frame_lines).int("#{prefix}sync_start", @sync_start)
+            out.int("#{prefix}sync_lines", @sync_lines)
+          end
+
+          def load_fields(input, prefix)
+            @frame = input.int("#{prefix}frame", @frame)
+            @row = input.int("#{prefix}row", @row)
+            @row_line = input.int("#{prefix}row_line", @row_line)
+            @adjusting = input.bool("#{prefix}adjusting", @adjusting)
+            @frame_line = input.int("#{prefix}frame_line", @frame_line)
+            @frame_lines = input.int("#{prefix}frame_lines", @frame_lines)
+            @sync_start = input.int("#{prefix}sync_start", @sync_start)
+            @sync_lines = input.int("#{prefix}sync_lines", @sync_lines)
+          end
+        end
+
+        include KeyedState
+      end
+
+      class Window
+        # The start addresses the frame latched, under `prefix`.
+        module KeyedState
+          def save_fields(out, prefix)
+            out.int("#{prefix}display_start", @display_start).int("#{prefix}attribute_start", @attribute_start)
+          end
+
+          def load_fields(input, prefix)
+            @display_start = input.word("#{prefix}display_start", @display_start)
+            @attribute_start = input.word("#{prefix}attribute_start", @attribute_start)
+          end
+        end
+
+        include KeyedState
+      end
+
+      class Painter
+        # The display's size, as the frame latched it, and the window's
+        # start addresses. The picture is painted again.
+        module KeyedState
+          def save_fields(out)
+            out.int("display.width", @width).int("display.height", @height)
+            @window.save_fields(out, "window.")
+          end
+
+          def load_fields(input)
+            resize(input.int("display.width", @width), input.int("display.height", @height))
+            @window.load_fields(input, "window.")
+          end
+        end
+
+        include KeyedState
+      end
+
+      # The VDC's fields in a keyed snapshot module (Snapshot::Keyed): the
+      # registers, the RAM, the register selected, the data latches, the
+      # dot clock's phase and the line's length in the same units
+      # (dots·Hz, the line latched at its start), how long an access or
+      # block operation stays busy from now, the raster under raster.* and
+      # the display's size and window under display.* and window.*. The
+      # RAM's layout comes from R28 on load.
+      module KeyedState
+        def save_fields(out)
+          out.bytes("registers", @registers).bytes("ram", @memory.ram).int("selected", @selected)
+          out.int("read_latch", @read_latch).int("write_data", @write_data).int("phase", @phase)
+          out.int("line_units", @line_units).int("busy_for", @busy_until - @phase)
+          @raster.save_fields(out, "raster.")
+          @painter.save_fields(out)
+          out
+        end
+
+        def load_fields(input)
+          input.bytes_into("registers", @registers)
+          input.bytes_into("ram", @memory.ram)
+          @selected = input.masked("selected", @selected, 0x3f)
+          @read_latch = input.byte("read_latch", @read_latch)
+          @write_data = input.byte("write_data", @write_data)
+          @phase = input.int("phase", @phase)
+          @line_units = input.int("line_units", @line_units)
+          @busy_until = @phase + input.int("busy_for", @busy_until - @phase)
+          @raster.load_fields(input, "raster.")
+          @painter.load_fields(input)
+        end
+
+        def restored!
+          @memory.mode64 = @registers[28].anybits?(0x10)
+        end
+      end
+
+      include KeyedState
+    end
+  end
+end

data/lib/badline/chips/vdc/painter.rb

@@ -56,18 +56,6 @@ module Badline
           [0, 0, shown.clamp(1, @width), (frame_lines - sync_lines).clamp(1, @height)]
         end
 
-        # The display's size and the window's start addresses. The display
-        # starts again cleared, to be painted while the VDC renders.
-        def save_state(out)
-          out.int(@width).int(@height)
-          @window.save_state(out)
-        end
-
-        def load_state(input)
-          resize(input.int, input.int)
-          @window.load_state(input)
-        end
-
         def clear_dirty_lines!
           @dirty_lines.fill(false)
         end

data/lib/badline/chips/vdc/raster.rb

@@ -30,22 +30,6 @@ module Badline
         # Outside the displayed rows, as status bit 5 reads.
         def vertical_blank? = @adjusting || @row >= @registers[6]
 
-        def save_state(out)
-          out.int(@frame).int(@row).int(@row_line).boolean(@adjusting).int(@frame_line).int(@frame_lines)
-          out.int(@sync_start).int(@sync_lines)
-        end
-
-        def load_state(input)
-          @frame = input.int
-          @row = input.int
-          @row_line = input.int
-          @adjusting = input.boolean?
-          @frame_line = input.int
-          @frame_lines = input.int
-          @sync_start = input.int
-          @sync_lines = input.int
-        end
-
         def end_line(render)
           paint_line if render
           @frame_line += 1

data/lib/badline/chips/vdc/window.rb

@@ -57,15 +57,6 @@ module Badline
           @attribute_start = (regs[20] << 8) | regs[21]
         end
 
-        def save_state(out)
-          out.int(@display_start).int(@attribute_start)
-        end
-
-        def load_state(input)
-          @display_start = input.int
-          @attribute_start = input.int
-        end
-
         def paint(line, row, row_line, frame)
           regs = @registers
           lay_out_cell

data/lib/badline/chips/vdc.rb

@@ -4,7 +4,7 @@ require "badline/chips/vdc/memory"
 require "badline/chips/vdc/window"
 require "badline/chips/vdc/painter"
 require "badline/chips/vdc/raster"
-require "badline/chips/vdc/saved_state"
+require "badline/chips/vdc/keyed_parts"
 
 module Badline
   module Chips
@@ -34,7 +34,6 @@ module Badline
     # fills or two per byte it copies.
     class VDC
       include Addressable
-      include SavedState
 
       STATUS_READY = 0x80
       STATUS_VBLANK = 0x20

data/lib/badline/chips/via/control_lines.rb

@@ -56,21 +56,6 @@ module Badline
 
         def active_c1_edge?(high) = high == @control.anybits?(0x01)
 
-        # The lines' levels and mode. Which flags they set, and whether reads
-        # handshake, are the port's wiring.
-        def save_state(out)
-          out.int(@control).boolean(@c1_high).boolean(@c2_high).boolean(@handshake_low).int(@pulse).boolean(@c2_output)
-        end
-
-        def load_state(input)
-          @control = input.int
-          @c1_high = input.boolean?
-          @c2_high = input.boolean?
-          @handshake_low = input.boolean?
-          @pulse = input.int
-          @c2_output = input.boolean?
-        end
-
         # Everything the lines hold, for comparing them at two points.
         def state = [@control, @c1_high, @c2_high, @handshake_low, @pulse, @c2_output]
 

data/lib/badline/chips/via/interrupt_register.rb

@@ -25,15 +25,6 @@ module Badline
           @enable = 0x00
         end
 
-        def save_state(out)
-          out.int(@flags).int(@enable)
-        end
-
-        def load_state(input)
-          @flags = input.int
-          @enable = input.int
-        end
-
         def set(bits)
           @flags |= bits
         end

data/lib/badline/chips/via/keyed_parts.rb

@@ -0,0 +1,163 @@
+# frozen_string_literal: true
+
+module Badline
+  module Chips
+    class VIA
+      class Timer1
+        # Timer 1's fields in a keyed snapshot module, under `prefix`.
+        module KeyedState
+          def save_fields(out, prefix)
+            out.int("#{prefix}counter", @counter).int("#{prefix}latch", @latch).bool("#{prefix}hold", @hold)
+            out.bool("#{prefix}reload", @reload).bool("#{prefix}armed", @armed).bool("#{prefix}pb7", @pb7)
+          end
+
+          def load_fields(input, prefix)
+            @counter = input.word("#{prefix}counter", @counter)
+            @latch = input.word("#{prefix}latch", @latch)
+            @hold = input.bool("#{prefix}hold", @hold)
+            @reload = input.bool("#{prefix}reload", @reload)
+            @armed = input.bool("#{prefix}armed", @armed)
+            @pb7 = input.bool("#{prefix}pb7", @pb7)
+          end
+        end
+
+        include KeyedState
+      end
+
+      class Timer2
+        # Timer 2's fields in a keyed snapshot module, under `prefix`.
+        module KeyedState
+          def save_fields(out, prefix)
+            out.int("#{prefix}counter", @counter).int("#{prefix}latch_low", @latch_low).bool("#{prefix}hold", @hold)
+            out.bool("#{prefix}low_reload", @low_reload).bool("#{prefix}armed", @armed)
+            out.bool("#{prefix}low_underflowed", @low_underflowed).bool("#{prefix}count_pulses", @count_pulses)
+            out.bool("#{prefix}counting_pulses", @counting_pulses)
+          end
+
+          def load_fields(input, prefix)
+            @counter = input.word("#{prefix}counter", @counter)
+            @latch_low = input.byte("#{prefix}latch_low", @latch_low)
+            @hold = input.bool("#{prefix}hold", @hold)
+            @low_reload = input.bool("#{prefix}low_reload", @low_reload)
+            @armed = input.bool("#{prefix}armed", @armed)
+            @low_underflowed = input.bool("#{prefix}low_underflowed", @low_underflowed)
+            @count_pulses = input.bool("#{prefix}count_pulses", @count_pulses)
+            @counting_pulses = input.bool("#{prefix}counting_pulses", @counting_pulses)
+          end
+        end
+
+        include KeyedState
+      end
+
+      class ShiftRegister
+        # The shift register's fields in a keyed snapshot module, under
+        # `prefix`.
+        module KeyedState
+          def save_fields(out, prefix)
+            out.int("#{prefix}mode", @mode).int("#{prefix}data", @data).int("#{prefix}bits", @bits)
+            out.int("#{prefix}delay", @delay).bool("#{prefix}clock", @clock).bool("#{prefix}cb2", @cb2)
+            out.bool("#{prefix}cb2_input", @cb2_input)
+          end
+
+          def load_fields(input, prefix)
+            @mode = input.masked("#{prefix}mode", @mode, 0x07)
+            @data = input.byte("#{prefix}data", @data)
+            @bits = input.int("#{prefix}bits", @bits)
+            @delay = input.int("#{prefix}delay", @delay)
+            @clock = input.bool("#{prefix}clock", @clock)
+            @cb2 = input.bool("#{prefix}cb2", @cb2)
+            @cb2_input = input.bool("#{prefix}cb2_input", @cb2_input)
+          end
+        end
+
+        include KeyedState
+      end
+
+      class InterruptRegister
+        # The flags and the enable mask, under `prefix`.
+        module KeyedState
+          def save_fields(out, prefix)
+            out.int("#{prefix}flags", @flags).int("#{prefix}enable", @enable)
+          end
+
+          def load_fields(input, prefix)
+            @flags = input.masked("#{prefix}flags", @flags, 0x7f)
+            @enable = input.masked("#{prefix}enable", @enable, 0x7f)
+          end
+        end
+
+        include KeyedState
+      end
+
+      class ControlLines
+        # A pair of control lines' fields, under `prefix`.
+        module KeyedState
+          def save_fields(out, prefix)
+            out.int("#{prefix}control", @control).bool("#{prefix}c1_high", @c1_high).bool("#{prefix}c2_high", @c2_high)
+            out.bool("#{prefix}handshake_low", @handshake_low).int("#{prefix}pulse", @pulse)
+            out.bool("#{prefix}c2_output", @c2_output)
+          end
+
+          def load_fields(input, prefix)
+            @control = input.masked("#{prefix}control", @control, 0x0f)
+            @c1_high = input.bool("#{prefix}c1_high", @c1_high)
+            @c2_high = input.bool("#{prefix}c2_high", @c2_high)
+            @handshake_low = input.bool("#{prefix}handshake_low", @handshake_low)
+            @pulse = input.int("#{prefix}pulse", @pulse)
+            @c2_output = input.bool("#{prefix}c2_output", @c2_output)
+          end
+        end
+
+        include KeyedState
+      end
+
+      # The VIA's fields in a keyed snapshot module (Snapshot::Keyed): the
+      # registers and PB6, and its parts under t1., t2., sr., ifr., ca. and
+      # cb. Whether the shift register clocks off timer 2 comes from the
+      # ACR on load. The peripheral restores its own state.
+      module KeyedState
+        def save_fields(out)
+          out.int("ora", @ora).int("orb", @orb).int("ddra", @ddra).int("ddrb", @ddrb).int("latch_a", @latch_a)
+          out.int("latch_b", @latch_b).int("acr", @acr).int("pcr", @pcr).bool("pb6_high", @pb6_high)
+          @t1.save_fields(out, "t1.")
+          @t2.save_fields(out, "t2.")
+          @shift_register.save_fields(out, "sr.")
+          @ifr.save_fields(out, "ifr.")
+          @ca.save_fields(out, "ca.")
+          @cb.save_fields(out, "cb.")
+          out
+        end
+
+        def load_fields(input)
+          @ora = input.byte("ora", @ora)
+          @orb = input.byte("orb", @orb)
+          @ddra = input.byte("ddra", @ddra)
+          @ddrb = input.byte("ddrb", @ddrb)
+          @latch_a = input.byte("latch_a", @latch_a)
+          @latch_b = input.byte("latch_b", @latch_b)
+          @acr = input.byte("acr", @acr)
+          @pcr = input.byte("pcr", @pcr)
+          @pb6_high = input.bool("pb6_high", @pb6_high)
+          load_part_fields(input)
+        end
+
+        def restored!
+          @sr_uses_t2 = [1, 4, 5].include?((@acr >> 2) & 0x07)
+        end
+
+        private
+
+        def load_part_fields(input)
+          @t1.load_fields(input, "t1.")
+          @t2.load_fields(input, "t2.")
+          @shift_register.load_fields(input, "sr.")
+          @ifr.load_fields(input, "ifr.")
+          @ca.load_fields(input, "ca.")
+          @cb.load_fields(input, "cb.")
+        end
+      end
+
+      include KeyedState
+    end
+  end
+end

data/lib/badline/chips/via/shift_register.rb

@@ -81,20 +81,6 @@ module Badline
         # changes it from cycle to cycle.
         def clocking? = @bits.nonzero? && internal_clock?
 
-        def save_state(out)
-          out.int(@mode).int(@data).int(@bits).int(@delay).boolean(@clock).boolean(@cb2).boolean(@cb2_input)
-        end
-
-        def load_state(input)
-          @mode = input.int
-          @data = input.int
-          @bits = input.int
-          @delay = input.int
-          @clock = input.boolean?
-          @cb2 = input.boolean?
-          @cb2_input = input.boolean?
-        end
-
         # Everything the register holds, for comparing it at two points.
         def state = [@mode, @data, @bits, @delay, @clock, @cb2, @cb2_input]
 

data/lib/badline/chips/via/timer1.rb

@@ -93,19 +93,6 @@ module Badline
           @counter = @reload ? 0xffff : @latch - phase + 1
         end
 
-        def save_state(out)
-          out.int(@counter).int(@latch).boolean(@hold).boolean(@reload).boolean(@armed).boolean(@pb7)
-        end
-
-        def load_state(input)
-          @counter = input.int
-          @latch = input.int
-          @hold = input.boolean?
-          @reload = input.boolean?
-          @armed = input.boolean?
-          @pb7 = input.boolean?
-        end
-
         # What the counter and PB7 don't hold, for comparing the timer at two
         # points.
         def state = [@latch, @armed]

data/lib/badline/chips/via/timer2.rb

@@ -85,24 +85,6 @@ module Badline
           @low_underflowed = @counter.allbits?(0xff)
         end
 
-        def save_state(out)
-          out.int(@counter).int(@latch_low)
-          [@hold, @low_reload, @armed, @low_underflowed, @count_pulses, @counting_pulses].each do |flag|
-            out.boolean(flag)
-          end
-        end
-
-        def load_state(input)
-          @counter = input.int
-          @latch_low = input.int
-          @hold = input.boolean?
-          @low_reload = input.boolean?
-          @armed = input.boolean?
-          @low_underflowed = input.boolean?
-          @count_pulses = input.boolean?
-          @counting_pulses = input.boolean?
-        end
-
         # What the counter and the low byte's underflow don't hold, for
         # comparing the timer at two points.
         def state = [@latch_low, @armed, @hold, @low_reload, @count_pulses, @counting_pulses]

data/lib/badline/chips/via.rb

@@ -4,9 +4,9 @@ require "badline/chips/via/control_lines"
 require "badline/chips/via/fast_forward"
 require "badline/chips/via/interrupt_register"
 require "badline/chips/via/shift_register"
-require "badline/chips/via/saved_state"
 require "badline/chips/via/timer1"
 require "badline/chips/via/timer2"
+require "badline/chips/via/keyed_parts"
 
 module Badline
   module Chips
@@ -20,7 +20,6 @@ module Badline
     class VIA
       include Addressable
       include FastForward
-      include SavedState
 
       attr_reader :start, :peripheral, :shift_register, :acr, :pcr
 

data/lib/badline/chips/vic/border_mask.rb

@@ -28,16 +28,6 @@ module Badline
           @groups.fill(FULL)
         end
 
-        def save_state(out)
-          out.ints(@groups).booleans(@mask).blob(@snapshot)
-        end
-
-        def load_state(input)
-          input.ints_into(@groups)
-          input.booleans_into(@mask)
-          input.blob_into(@snapshot)
-        end
-
         def at?(pixel_x)
           case @groups[pixel_x >> 3]
           when FULL then true