badline 0.13.0 → 0.14.0

data/lib/badline/chips/cpu/saved_state.rb

@@ -1,117 +0,0 @@
-# frozen_string_literal: true
-
-module Badline
-  module Chips
-    class CPU
-      # The CPU's state for a snapshot: the registers, the interrupt lines and
-      # their pipeline, and the step of the instruction in flight, named by
-      # where its plan comes from.
-      module SavedState
-        # Writes everything the CPU holds, down to the step of the instruction
-        # it is in, for load_state to put back. The interrupt lines, BA stalls
-        # and SO are state too; the traps and the debug flag belong to the host.
-        def save_state(out)
-          out.marker("CPU")
-          out.int(@program_counter).int(@stack_pointer).int(@a).int(@x).int(@y).int(@status.value)
-          [@irq, @nmi, @irq_sample, @irq_pending, @nmi_sample, @nmi_pending, @skip_poll, @boundary_irq,
-           @boundary_nmi, @boundary_crossed, @brk, @pending_write, @so_high, @optional_dummy,
-           @branch_taken].each { |flag| out.boolean(flag) }
-          out.optional_int(@interrupt).optional_int(@stalled_at).int(@cycles).int(@instructions)
-          out.int(plan_source).int(@index).int(OPERATIONS.index(@operation) || -1)
-          [@address, @dummy_address, @value, @rmw_result, @pointer].each { |register| out.optional_int(register) }
-        end
-
-        def load_state(input)
-          input.marker("CPU")
-          @program_counter = input.int
-          @stack_pointer = input.int
-          @a = input.int
-          @x = input.int
-          @y = input.int
-          @status.value = input.int
-          load_flags(input)
-          @interrupt = input.optional_int
-          @stalled_at = input.optional_int
-          @cycles = input.int
-          @instructions = input.int
-          load_plan(input.int)
-          @index = input.int
-          operation = input.int
-          @operation = operation.negative? ? nil : OPERATIONS.fetch(operation)
-          load_working_registers(input)
-        end
-
-        # Drops the instruction or interrupt sequence in flight and the
-        # interrupt lines' pipeline, so the next cycle fetches an opcode at the
-        # program counter, and sets the cycle count. A snapshot taken between
-        # instructions, as VICE's are, restores through here.
-        def resume(cycles)
-          @irq_sample = @irq_pending = false
-          @nmi_sample = @nmi_pending = false
-          @skip_poll = false
-          @interrupt = nil
-          @brk = false
-          @stalled_at = nil
-          @cycles = cycles
-          end_sequence
-          @pending_write = false
-        end
-
-        private
-
-        # Where the plan running comes from: an opcode's microcode, or FETCH,
-        # INTERRUPT or JAMMED below it.
-        def plan_source
-          return FETCH if @plan.equal?(FETCH_PLAN)
-          return INTERRUPT if @plan.equal?(INTERRUPT_PLAN)
-          return JAMMED if @plan.equal?(JAMMED_PLAN)
-
-          MICROCODE.index { |micro| micro.plan.equal?(@plan) && micro.operation == @operation } ||
-            MICROCODE.index { |micro| micro.plan.equal?(@plan) }
-        end
-
-        def load_plan(source)
-          case source
-          when FETCH then use_plan(FETCH_PLAN, FETCH_WRITES)
-          when INTERRUPT then use_plan(INTERRUPT_PLAN, INTERRUPT_WRITES)
-          when JAMMED then use_plan(JAMMED_PLAN, JAMMED_WRITES)
-          else
-            micro = MICROCODE.fetch(source)
-            use_plan(micro.plan, micro.writes)
-          end
-        end
-
-        def use_plan(plan, writes)
-          @plan = plan
-          @writes = writes
-        end
-
-        def load_flags(input)
-          @irq = input.boolean?
-          @nmi = input.boolean?
-          @irq_sample = input.boolean?
-          @irq_pending = input.boolean?
-          @nmi_sample = input.boolean?
-          @nmi_pending = input.boolean?
-          @skip_poll = input.boolean?
-          @boundary_irq = input.boolean?
-          @boundary_nmi = input.boolean?
-          @boundary_crossed = input.boolean?
-          @brk = input.boolean?
-          @pending_write = input.boolean?
-          @so_high = input.boolean?
-          @optional_dummy = input.boolean?
-          @branch_taken = input.boolean?
-        end
-
-        def load_working_registers(input)
-          @address = input.optional_int
-          @dummy_address = input.optional_int
-          @value = input.optional_int
-          @rmw_result = input.optional_int
-          @pointer = input.optional_int
-        end
-      end
-    end
-  end
-end

data/lib/badline/chips/sid/envelope/saved_state.rb

@@ -1,70 +0,0 @@
-# frozen_string_literal: true
-
-module Badline
-  module Chips
-    class SID
-      class Envelope
-        # A snapshot of an envelope: its rates, the gate, the state and the
-        # counters and pipelines between them, and the same fields as reSID
-        # keeps them, for VICE's SIDEXTENDED module.
-        module SavedState
-          # The fields reSID keeps for an envelope between cycles: the rate and
-          # exponential counters, the level, the state as an index into STATES,
-          # whether it holds at zero, the two periods and the pipeline.
-          def resid_fields
-            [@rate_counter, @exponential_counter, @counter, STATES.index(@state).to_i, @hold_zero ? 1 : 0,
-             @rate_period, @exponential_period, @envelope_pipeline]
-          end
-
-          # Takes the fields resid_fields gives from `fields`, from `at` on.
-          def restore_resid_fields(fields, at)
-            @rate_counter = fields[at]
-            @exponential_counter = fields[at + 1]
-            @counter = @env3 = fields[at + 2]
-            state = fields[at + 3]
-            @state = @next_state = STATES.fetch(state.clamp(0, STATES.length - 1)).to_sym
-            @hold_zero = fields[at + 4] != 0
-            @rate_period = fields[at + 5]
-            @exponential_period = fields[at + 6]
-            @envelope_pipeline = fields[at + 7]
-          end
-
-          def save_state(out)
-            [@attack, @decay, @sustain, @release].each { |rate| out.int(rate) }
-            out.boolean(@gate).int(STATES.index(@state)).int(STATES.index(@next_state))
-            out.int(@counter).int(@env3).int(@rate_counter).int(@rate_period).boolean(@reset_rate_counter)
-            out.int(@exponential_counter).int(@exponential_period)
-            out.int(@state_pipeline).int(@envelope_pipeline).int(@exponential_pipeline).boolean(@hold_zero)
-          end
-
-          def load_state(input)
-            @attack = input.int
-            @decay = input.int
-            @sustain = input.int
-            @release = input.int
-            @gate = input.boolean?
-            @state = STATES.fetch(input.int).to_sym
-            @next_state = STATES.fetch(input.int).to_sym
-            load_counters(input)
-          end
-
-          private
-
-          def load_counters(input)
-            @counter = input.int
-            @env3 = input.int
-            @rate_counter = input.int
-            @rate_period = input.int
-            @reset_rate_counter = input.boolean?
-            @exponential_counter = input.int
-            @exponential_period = input.int
-            @state_pipeline = input.int
-            @envelope_pipeline = input.int
-            @exponential_pipeline = input.int
-            @hold_zero = input.boolean?
-          end
-        end
-      end
-    end
-  end
-end

data/lib/badline/chips/sid/filter/saved_state.rb

@@ -1,42 +0,0 @@
-# frozen_string_literal: true
-
-module Badline
-  module Chips
-    class SID
-      class Filter
-        # The filter's state for a snapshot.
-        module SavedState
-          # The registers as the filter decoded them and its integrators. The
-          # W0 table is the model's.
-          def save_state(out)
-            out.int(@cutoff).int(@routing).int(@mode).int(@volume).boolean(@voice3_off).int(@w0).int(@resonance)
-            [@highpass, @bandpass, @lowpass, @unfiltered, @input].each { |value| out.int(value) }
-            @external.save_state(out)
-          end
-
-          def load_state(input)
-            @cutoff = input.int
-            @routing = input.int
-            @mode = input.int
-            @volume = input.int
-            @voice3_off = input.boolean?
-            @w0 = input.int
-            @resonance = input.int
-            load_integrators(input)
-          end
-
-          private
-
-          def load_integrators(input)
-            @highpass = input.int
-            @bandpass = input.int
-            @lowpass = input.int
-            @unfiltered = input.int
-            @input = input.int
-            @external.load_state(input)
-          end
-        end
-      end
-    end
-  end
-end

data/lib/badline/chips/sid/saved_state.rb

@@ -1,52 +0,0 @@
-# frozen_string_literal: true
-
-module Badline
-  module Chips
-    class SID
-      # The SID's state for a snapshot.
-      module SavedState
-        # How far the recording has got into the sample it is averaging, for
-        # a host that carries on recording from a saved state: it calls
-        # #record, then #load_recording.
-        def save_recording(out)
-          decimator = @decimator
-          raise ArgumentError, "the SID isn't recording" if decimator.nil?
-
-          out.marker("RECORDING")
-          decimator.save_state(out)
-        end
-
-        def load_recording(input)
-          decimator = @decimator
-          raise ArgumentError, "the SID isn't recording" if decimator.nil?
-
-          input.marker("RECORDING")
-          decimator.load_state(input)
-        end
-
-        # The registers, the data bus, the voices and the filter, and the span
-        # the DSP has yet to catch up on, as it stands: saving leaves the SID
-        # as it was. Whether it synthesizes or records is the host's.
-        def save_state(out)
-          out.marker("SID")
-          @registers.save_state(out)
-          out.int(@bus_value).int(@bus_ttl).int(@pending_cycles).ints(@deferred_writes)
-          @voices.each { |voice| voice.save_state(out) }
-          @filter.save_state(out)
-        end
-
-        def load_state(input)
-          input.marker("SID")
-          @registers.load_state(input)
-          @bus_value = input.int
-          @bus_ttl = input.int
-          @pending_cycles = input.int
-          input.ints_into(@deferred_writes)
-          @voices.each { |voice| voice.load_state(input) }
-          @filter.load_state(input)
-          update_span_rules
-        end
-      end
-    end
-  end
-end

data/lib/badline/chips/sid/waveform/saved_state.rb

@@ -1,68 +0,0 @@
-# frozen_string_literal: true
-
-module Badline
-  module Chips
-    class SID
-      class Waveform
-        # A snapshot of an oscillator: its phase, the noise register and the
-        # output latch, and the same fields as reSID keeps them, for VICE's
-        # SIDEXTENDED module. The model's tables and the voices it syncs with
-        # are the SID's wiring.
-        module SavedState
-          # The fields reSID keeps for an oscillator between cycles: the phase,
-          # the noise register, its shift pipeline and reset countdown, the
-          # floating output's countdown and the pulse level.
-          def resid_fields
-            [@accumulator, @shift_register, @shift_pipeline, @shift_register_reset, @floating_ttl, @pulse]
-          end
-
-          # Takes the fields resid_fields gives from `fields`, from `at` on.
-          def restore_resid_fields(fields, at)
-            @accumulator = fields[at]
-            @shift_register = fields[at + 1]
-            @shift_pipeline = fields[at + 2]
-            @shift_register_reset = fields[at + 3]
-            @floating_ttl = fields[at + 4]
-            @pulse = fields[at + 5]
-            @stale = true
-          end
-
-          def save_state(out)
-            out.int(@accumulator).int(@delayed_triangle).int(@delayed_sawtooth)
-            out.int(@shift_register).int(@shift_register_reset).int(@shift_pipeline)
-            out.int(@frequency).int(@pulse_width).int(@selected)
-            [@test, @ring, @sync, @msb_rising].each { |flag| out.boolean(flag) }
-            out.int(@floating).int(@floating_ttl).int(@pulse).int(@output).boolean(@stale)
-          end
-
-          def load_state(input)
-            @accumulator = input.int
-            @delayed_triangle = input.int
-            @delayed_sawtooth = input.int
-            @shift_register = input.int
-            @shift_register_reset = input.int
-            @shift_pipeline = input.int
-            @frequency = input.int
-            @pulse_width = input.int
-            @selected = input.int
-            load_latches(input)
-          end
-
-          private
-
-          def load_latches(input)
-            @test = input.boolean?
-            @ring = input.boolean?
-            @sync = input.boolean?
-            @msb_rising = input.boolean?
-            @floating = input.int
-            @floating_ttl = input.int
-            @pulse = input.int
-            @output = input.int
-            @stale = input.boolean?
-          end
-        end
-      end
-    end
-  end
-end

data/lib/badline/chips/vdc/saved_state.rb

@@ -1,36 +0,0 @@
-# frozen_string_literal: true
-
-module Badline
-  module Chips
-    class VDC
-      # The VDC's state for a snapshot.
-      module SavedState
-        # Everything the VDC holds but its display, which it paints again
-        # while it renders: the registers, the RAM, the data port and the
-        # raster. Whether it renders is the host's.
-        def save_state(out)
-          out.marker("VDC")
-          out.ints(@registers).blob(@memory.ram)
-          out.int(@selected).int(@read_latch).int(@write_data).int(@busy_until).int(@phase).int(@line_units)
-          @raster.save_state(out)
-          @painter.save_state(out)
-        end
-
-        def load_state(input)
-          input.marker("VDC")
-          input.ints_into(@registers)
-          input.blob_into(@memory.ram)
-          @memory.mode64 = @registers[28].anybits?(0x10)
-          @selected = input.int
-          @read_latch = input.int
-          @write_data = input.int
-          @busy_until = input.int
-          @phase = input.int
-          @line_units = input.int
-          @raster.load_state(input)
-          @painter.load_state(input)
-        end
-      end
-    end
-  end
-end

data/lib/badline/chips/via/saved_state.rb

@@ -1,44 +0,0 @@
-# frozen_string_literal: true
-
-module Badline
-  module Chips
-    class VIA
-      # Saving and restoring a VIA for a snapshot.
-      module SavedState
-        # The registers, the timers, the shift register, the interrupt flags
-        # and the control lines. The peripheral is the drive's wiring.
-        def save_state(out)
-          out.int(@ora).int(@orb).int(@ddra).int(@ddrb).int(@latch_a).int(@latch_b).int(@acr).int(@pcr)
-          out.boolean(@pb6_high).boolean(@sr_uses_t2)
-          @t1.save_state(out)
-          @t2.save_state(out)
-          @shift_register.save_state(out)
-          @ifr.save_state(out)
-          @ca.save_state(out)
-          @cb.save_state(out)
-        end
-
-        # Puts the state back without telling the peripheral, which restores
-        # its own.
-        def load_state(input)
-          @ora = input.int
-          @orb = input.int
-          @ddra = input.int
-          @ddrb = input.int
-          @latch_a = input.int
-          @latch_b = input.int
-          @acr = input.int
-          @pcr = input.int
-          @pb6_high = input.boolean?
-          @sr_uses_t2 = input.boolean?
-          @t1.load_state(input)
-          @t2.load_state(input)
-          @shift_register.load_state(input)
-          @ifr.load_state(input)
-          @ca.load_state(input)
-          @cb.load_state(input)
-        end
-      end
-    end
-  end
-end

data/lib/badline/chips/vic/graphics_shifter/saved_state.rb

@@ -1,40 +0,0 @@
-# frozen_string_literal: true
-
-module Badline
-  module Chips
-    class VIC
-      class GraphicsShifter
-        # The shifter's state for a snapshot.
-        module SavedState
-          def save_state(out)
-            out.int(@next_ecm_bmm).int(@black_below).ints(@colors).booleans(@fg)
-            out.int(@gbuf).int(@vbuf).int(@cbuf).int(@flop).int(@pixel)
-            out.int(@mode_lookup).int(@mode_read).boolean(@late_mcm).boolean(@late_read)
-          end
-
-          def load_state(input)
-            @next_ecm_bmm = input.int
-            @black_below = input.int
-            input.ints_into(@colors)
-            input.booleans_into(@fg)
-            load_buffers(input)
-            @mode_lookup = input.int
-            @mode_read = input.int
-            @late_mcm = input.boolean?
-            @late_read = input.boolean?
-          end
-
-          private
-
-          def load_buffers(input)
-            @gbuf = input.int
-            @vbuf = input.int
-            @cbuf = input.int
-            @flop = input.int
-            @pixel = input.int
-          end
-        end
-      end
-    end
-  end
-end

data/lib/badline/chips/vic/saved_state.rb

@@ -1,82 +0,0 @@
-# frozen_string_literal: true
-
-module Badline
-  module Chips
-    class VIC
-      # The VIC's state for a snapshot.
-      module SavedState
-        # Everything the VIC holds between cycles: the beam, the fetch and
-        # g-access pipeline, the light pen and raster latches, the finished
-        # lines, on the VIC-IIe the display line and the TEST bit's wrap, the
-        # registers and the display, sequencer and sprite logic.
-        # Whether it renders is the host's, and every line comes back dirty so
-        # a front end repaints.
-        def save_state(out)
-          out.marker("VIC")
-          out.int(@column).int(@rasterline)
-          out.int(@g_tick).ints(@g_kind).int(@g_kept_char).int(@g_kept_color).boolean(@g_display)
-          out.int(@fetch_d011).boolean(@lp_triggered).boolean(@lp_low).boolean(@raster_match)
-          out.int(@vic_bank.lines)
-          out.blob(@character_buffer).blob(@color_buffer).booleans(@sprite_ba)
-          @lines.each { |line| out.blob(line) }
-          out.int(@output_line).boolean(@test_wrap) if @iie
-          @registers.save_state(out)
-          @display_state.save_state(out)
-          @sequencer.save_state(out)
-          @sprites.save_state(out)
-        end
-
-        def load_state(input)
-          input.marker("VIC")
-          load_beam(input)
-          load_buffers(input)
-          load_lines(input)
-          load_test_state(input) if @iie
-          @registers.load_state(input)
-          @display_state.load_state(input)
-          @sequencer.load_state(input)
-          @sprites.load_state(input)
-        end
-
-        private
-
-        def load_beam(input)
-          @column = input.int
-          @rasterline = @output_line = input.int
-          @g_tick = input.int
-          input.ints_into(@g_kind)
-          @g_kept_char = input.int
-          @g_kept_color = input.int
-          @g_display = input.boolean?
-          @fetch_d011 = input.int
-          @lp_triggered = input.boolean?
-          @lp_low = input.boolean?
-          @raster_match = input.boolean?
-          @vic_bank.lines = input.int
-        end
-
-        def load_buffers(input)
-          input.blob_into(@character_buffer)
-          input.blob_into(@color_buffer)
-          input.booleans_into(@sprite_ba)
-        end
-
-        # The VIC-IIe's display line and TEST wrap, which only its TEST bit
-        # moves off the raster line.
-        def load_test_state(input)
-          @output_line = input.int
-          @test_wrap = input.boolean?
-        end
-
-        # The display is the finished lines one after another.
-        def load_lines(input)
-          @lines.each_with_index do |line, number|
-            input.blob_into(line)
-            @display[number * @width, @width] = line
-          end
-          @dirty_lines.fill(true)
-        end
-      end
-    end
-  end
-end

data/lib/badline/chips/vic/sequencer/saved_state.rb

@@ -1,91 +0,0 @@
-# frozen_string_literal: true
-
-module Badline
-  module Chips
-    class VIC
-      class Sequencer
-        # The sequencer's save_state and load_state.
-        module SavedState
-          FG_SHIFTER = -1
-          PAIR_CODES = 256
-
-          # The line buffers, the border flip-flops, the g-access ring and the
-          # pixel pipeline. The foreground masks the groups point at go as
-          # FG_SHIFTER for the shift register's, or their data byte in
-          # GraphicsMode's HIRES_FG, or that plus 256 in its PAIR_FG. The left
-          # vertical border compare goes as -1 before it has run.
-          def save_state(out)
-            out.int(@line).boolean(@first_csel).int(@left_vertical_border.nil? ? -1 : bit(@left_vertical_border))
-            out.blob(@colors).booleans(@fg)
-            @border_mask.save_state(out)
-            out.ints(@cur_colors).int(fg_code(@cur_fg)).ints(@prev_colors).int(fg_code(@prev_fg))
-            out.boolean(@vertical_border).boolean(@vertical_armed).boolean(@main_border)
-            @color_patches.save_state(out)
-            @shifter.save_state(out)
-            out.int(@xscroll).int(@last_shift).int(@last_mode).boolean(@settling).boolean(@prev_fresh).boolean(@check)
-            out.ints(@ring_data).ints(@ring_char).ints(@ring_color)
-          end
-
-          def load_state(input)
-            load_line(input)
-            @border_mask.load_state(input)
-            input.ints_into(@cur_colors)
-            @cur_fg = fg_pattern(input.int)
-            input.ints_into(@prev_colors)
-            @prev_fg = fg_pattern(input.int)
-            @vertical_border = input.boolean?
-            @vertical_armed = input.boolean?
-            @main_border = input.boolean?
-            @color_patches.load_state(input)
-            @shifter.load_state(input)
-            load_pipeline(input)
-          end
-
-          private
-
-          def bit(flag) = flag ? 1 : 0
-
-          def load_line(input)
-            @line = input.int
-            @first_csel = input.boolean?
-            left = input.int
-            @left_vertical_border = left.negative? ? nil : left == 1
-            input.blob_into(@colors)
-            input.booleans_into(@fg)
-          end
-
-          def load_pipeline(input)
-            @xscroll = input.int
-            @last_shift = input.int
-            @last_mode = input.int
-            @settling = input.boolean?
-            @prev_fresh = input.boolean?
-            @check = input.boolean?
-            input.ints_into(@ring_data)
-            input.ints_into(@ring_char)
-            input.ints_into(@ring_color)
-          end
-
-          def fg_code(pattern)
-            return FG_SHIFTER if pattern.equal?(@shifter.fg)
-
-            hires = GraphicsMode::HIRES_FG.index { |fg| fg.equal?(pattern) }
-            return hires if hires
-
-            pair = GraphicsMode::PAIR_FG.index { |fg| fg.equal?(pattern) }
-            raise ArgumentError, "a foreground mask the sequencer doesn't know" unless pair
-
-            PAIR_CODES + pair
-          end
-
-          def fg_pattern(code)
-            return @shifter.fg if code == FG_SHIFTER
-            return GraphicsMode::HIRES_FG.fetch(code) if code < PAIR_CODES
-
-            GraphicsMode::PAIR_FG.fetch(code - PAIR_CODES)
-          end
-        end
-      end
-    end
-  end
-end