badline 0.13.0 → 0.14.0

data/lib/badline/options.rb

@@ -14,7 +14,7 @@ module Badline
   # first, plays .sid tunes and directories of them in the terminal.
   # `c64`, `vic20` or `c128`, given first, names the machine family, and
   # without one the family is the C64, or the C128 for a program that loads
-  # where C128 BASIC starts. The native build adds --no-sound and
+  # where C128 BASIC starts. `plus4` is refused until the Plus/4 runs. The native build adds --no-sound and
   # --version, and badline-ruby adds --disable-jit.
   #
   # TABLE lists the options, and both the parser and the help read it. It
@@ -94,6 +94,7 @@ module Badline
       @true_drive = false
       @screenshot = ""
       @save_snapshot = ""
+      @vice = false
       @timeline = []
       @jit = true
       @help = false
@@ -171,6 +172,9 @@ module Badline
 
     def true_drive? = @true_drive
 
+    # Whether --save-snapshot adds VICE's modules, so x64sc opens it.
+    def vice? = @vice
+
     def jit? = @jit
 
     # The name of the model to build: a C64 Badline::Model names, a VIC-20
@@ -272,6 +276,7 @@ module Badline
       when "--no-vsync" then @vsync = false
       when "--verbose" then @verbose = true
       when "--true-drive" then @true_drive = true
+      when "--vice" then @vice = true
       when "--ntsc" then @models << "ntsc"
       when "--c64" then @c64_mode = true
       when "--unpaced" then @paced = false

data/lib/badline/plus4/acia.rb

@@ -0,0 +1,45 @@
+# frozen_string_literal: true
+
+module Badline
+  class Plus4
+    # The Plus/4's 6551 ACIA at $FD00-$FD0F, its four registers repeated,
+    # as a stub with nothing on the line: it never receives, its
+    # transmitter is always empty, and it never interrupts. The command and
+    # control registers keep what is written to them, and a write to the
+    # status register, a programmed reset, clears the command register's
+    # low five bits.
+    class ACIA
+      STATUS = 0x10
+
+      attr_reader :command, :control
+
+      def initialize
+        reset!
+      end
+
+      def reset!
+        @command = 0
+        @control = 0
+      end
+
+      def irq? = false
+
+      def peek(addr)
+        case addr & 0x03
+        when 1 then STATUS
+        when 2 then @command
+        when 3 then @control
+        else 0
+        end
+      end
+
+      def poke(addr, value)
+        case addr & 0x03
+        when 1 then @command &= 0xe0
+        when 2 then @command = value
+        when 3 then @control = value
+        end
+      end
+    end
+  end
+end

data/lib/badline/plus4/bus.rb

@@ -0,0 +1,312 @@
+# frozen_string_literal: true
+
+module Badline
+  class Plus4
+    # The CPU's bus:
+    #
+    # $0000-$0001 - the 7501's port (CPUPort), over RAM
+    # $0002-$7FFF - RAM
+    # $8000-$BFFF - the low ROM bank, or RAM
+    # $C000-$FCFF - the high ROM bank, or RAM; $FC00-$FCFF is always the
+    #               KERNAL's while ROM is selected
+    # $FD00-$FD0F - the 6551 ACIA (Plus/4 only)
+    # $FD10-$FD1F - the user port's 6529 (Plus/4 only)
+    # $FD30-$FD3F - the keyboard's 6529 (KeyboardPort)
+    # $FDD0-$FDDF - the ROM bank latch
+    # $FF00-$FF1F - the TED
+    # $FF3E/$FF3F - a write selects ROM or RAM at $8000-$FFFF
+    # $FF40-$FFFF - the high ROM bank, or RAM
+    #
+    # A write to $FF3E selects ROM and one to $FF3F RAM, everywhere in
+    # $8000-$FFFF but $FD00-$FF3F, which holds I/O either way. ROM is
+    # selected at power-on and reset. A write to ROM goes to the RAM under
+    # it. The ROM bank latch takes the address written to, not the byte:
+    # bits 0-1 pick the low bank and bits 2-3 the high bank, 0 for BASIC
+    # and the KERNAL, 1 for the Plus/4's function ROMs, 2 and 3 for the two
+    # cartridges.
+    #
+    # RAM smaller than 64K repeats through the 64K, as the C16's 16K does
+    # without A14 and A15. Where nothing answers, a read finds the last byte
+    # on the bus.
+    class Bus
+      include Addressable
+
+      RAM_POWER_ON = 0x00
+
+      # RAM through a size it repeats at.
+      class MirroredRAM
+        def initialize(ram, mask)
+          @ram = ram
+          @mask = mask
+        end
+
+        def peek(addr) = @ram.peek(addr & @mask)
+
+        def poke(addr, value)
+          @ram.poke(addr & @mask, value)
+        end
+      end
+
+      # The last byte the CPU moved, which an empty spot reads back.
+      class OpenBus
+        def initialize(bus)
+          @bus = bus
+        end
+
+        def peek(_addr) = @bus.data
+        def poke(_addr, _value); end
+      end
+
+      # Page 0: the port at $00 and $01, RAM above it.
+      class ZeroPage
+        def initialize(port, ram)
+          @port = port
+          @ram = ram
+        end
+
+        def peek(addr) = addr < 2 ? @port.peek(addr) : @ram.peek(addr)
+
+        def poke(addr, value)
+          return @port.poke(addr, value) if addr < 2
+
+          @ram.poke(addr, value)
+        end
+      end
+
+      # Page $FD: the ACIA, the user port, the keyboard port and the ROM
+      # bank latch, by the address's bits 4-7. +acia+ and +user_port+ are
+      # nil where the machine has none.
+      class IOPage
+        def initialize(keyboard_port:, acia: nil, user_port: nil)
+          @bus = nil
+          @acia = acia
+          @user_port = user_port
+          @keyboard_port = keyboard_port
+        end
+
+        # The bus whose last byte an empty spot reads and whose bank latch
+        # a write to $FDD0-$FDDF sets.
+        def connect(bus)
+          @bus = bus
+        end
+
+        def peek(addr)
+          case addr & 0xf0
+          when 0x00 then @acia ? @acia.peek(addr) : @bus.data
+          when 0x10 then @user_port ? @user_port.peek(addr) : @bus.data
+          when 0x30 then @keyboard_port.peek(addr)
+          else @bus.data
+          end
+        end
+
+        def poke(addr, value)
+          case addr & 0xf0
+          when 0x00 then @acia&.poke(addr, value)
+          when 0x10 then @user_port&.poke(addr, value)
+          when 0x30 then @keyboard_port.poke(addr, value)
+          when 0xd0 then @bus.select_banks(addr)
+          end
+        end
+      end
+
+      # VICE's debug cartridge register at $FDCF, a spot in the I/O page
+      # that nothing answers (plus4world forum post 31417). A write there
+      # calls the handler with the byte, the exit code the VICE testprogs
+      # report. Every other access falls through to the I/O page.
+      class DebugRegister
+        ADDRESS = 0xfdcf
+
+        def initialize(io, &handler)
+          @io = io
+          @handler = handler
+        end
+
+        def peek(addr) = @io.peek(addr)
+
+        def poke(addr, value)
+          return @handler.call(value) if addr == ADDRESS
+
+          @io.poke(addr, value)
+        end
+      end
+
+      # Page $FE with a 1551's TCBM interface plugged in: the 6523 TIA
+      # that talks to drive 9 at $FEC0-$FEDF and drive 8's at $FEE0-$FEFF.
+      # The rest of the page is open.
+      class TCBMPage
+        def initialize(bus, drive8:, drive9:)
+          @bus = bus
+          @drive8 = drive8
+          @drive9 = drive9
+        end
+
+        def peek(addr)
+          return @bus.data if addr < 0xfec0
+
+          addr < 0xfee0 ? @drive9.peek(addr) : @drive8.peek(addr)
+        end
+
+        def poke(addr, value)
+          return if addr < 0xfec0
+
+          addr < 0xfee0 ? @drive9.poke(addr, value) : @drive8.poke(addr, value)
+        end
+      end
+
+      # Page $FF: the TED in $FF00-$FF3F, its two phantom registers, and
+      # ROM or RAM above.
+      class TopPage
+        def initialize(bus, ted)
+          @bus = bus
+          @ted = ted
+        end
+
+        def peek(addr)
+          return @ted.peek(addr) if addr < 0xff40
+
+          @bus.top_memory.peek(addr)
+        end
+
+        def poke(addr, value)
+          return @bus.ram_view.poke(addr, value) if addr >= 0xff40
+
+          case addr
+          when 0xff3e then @bus.rom_selected = true
+          when 0xff3f then @bus.rom_selected = false
+          else @ted.poke(addr, value)
+          end
+        end
+      end
+
+      attr_reader :ram, :ram_view, :data, :low_bank, :high_bank
+
+      # What the top page reads above $FF3F: the high ROM bank or RAM.
+      attr_reader :top_memory
+
+      # The CPU sees ROM at $8000-$FFFF.
+      attr_reader :rom_selected
+
+      # +io+ is the IOPage, +model+ a Model profile, whose KERNAL it maps
+      # and whose function ROMs it maps where the model has them, and
+      # +ram_kb+ the RAM fitted.
+      def initialize(ted:, port:, io:, model: Model::PLUS4, ram_kb: model.ram_kb)
+        addressable_at(0, length: 2**16)
+        size = ram_kb * 1024
+        @ram = Memory.new(Array.new(size, RAM_POWER_ON), length: size, start: 0)
+        @ram_view = MirroredRAM.new(@ram, size - 1)
+        @ted = ted
+        @open_bus = OpenBus.new(self)
+        @low_roms = [ROM.load("plus4/basic.rom", 0x8000), nil, nil, nil]
+        @high_roms = [ROM.load(model.kernal, 0xc000), nil, nil, nil]
+        if model.plus4_parts
+          @low_roms[1] = ROM.load("plus4/function-low.rom", 0x8000)
+          @high_roms[1] = ROM.load("plus4/function-high.rom", 0xc000)
+        end
+        @zero_page = ZeroPage.new(port, @ram_view)
+        @io_page = io
+        io.connect(self)
+        @top_page = TopPage.new(self, ted)
+        @tcbm_page = @open_bus
+        @debug_register = nil
+        @data = 0
+        @read_pages = Array.new(256, @open_bus)
+        @write_pages = Array.new(256, @ram_view)
+        @low_bank = @high_bank = 0
+        @rom_selected = true
+        @top_memory = @ram_view
+        map_writes
+        map_reads
+      end
+
+      def power_on!
+        @ram.clear!(Array.new(@ram.length, RAM_POWER_ON))
+        reset!
+      end
+
+      # The RESET line selects ROM and the first bank of each.
+      def reset!
+        @low_bank = @high_bank = 0
+        self.rom_selected = true
+      end
+
+      def rom_selected=(selected)
+        @rom_selected = selected
+        @ted.rom_selected = selected
+        map_reads
+      end
+
+      # Whether the CPU reads the KERNAL at $C000-$FFFF: ROM selected, with
+      # the KERNAL's bank, high bank 0.
+      def kernal_selected? = @rom_selected && @high_bank.zero?
+
+      # A write to the ROM bank latch at +addr+.
+      def select_banks(addr)
+        @low_bank = addr & 0x03
+        @high_bank = (addr >> 2) & 0x03
+        map_reads
+      end
+
+      # Calls the block with each byte written to $FDCF (DebugRegister).
+      def install_debug_register(&)
+        @debug_register = DebugRegister.new(@io_page, &)
+        map_writes
+      end
+
+      # Plugs in a 1551's TCBM interface, the TIAs at $FEC0-$FEFF.
+      def plug_tcbm(drive8:, drive9:)
+        @tcbm_page = TCBMPage.new(self, drive8:, drive9:)
+        map_writes
+        map_reads
+      end
+
+      # Puts a cartridge's ROM chips in the slots of cartridge 1: a chip at
+      # $8000 in low bank 2 and one at $C000 in high bank 2, each repeated
+      # through the bank's 16K.
+      def attach_cartridge(chips)
+        chips.each do |chip|
+          data = chip.data * (0x4000 / chip.data.length)
+          if chip.address < 0xc000
+            @low_roms[2] = ROM.new(data, length: 0x4000, start: 0x8000)
+          else
+            @high_roms[2] = ROM.new(data, length: 0x4000, start: 0xc000)
+          end
+        end
+        map_reads
+      end
+
+      def peek(addr)
+        @data = @read_pages[addr >> 8].peek(addr)
+      end
+
+      def poke(addr, value)
+        @data = value
+        @write_pages[addr >> 8].poke(addr, value)
+      end
+
+      private
+
+      def map_writes
+        @write_pages[0x00] = @zero_page
+        @write_pages[0xfd] = @debug_register || @io_page
+        @write_pages[0xfe] = @tcbm_page
+        @write_pages[0xff] = @top_page
+      end
+
+      def map_reads
+        @read_pages.fill(@ram_view, 0x00, 0xfd)
+        @read_pages[0x00] = @zero_page
+        map_roms if @rom_selected
+        @top_memory = @rom_selected ? @high_roms[@high_bank] || @open_bus : @ram_view
+        @read_pages[0xfd] = @io_page
+        @read_pages[0xfe] = @tcbm_page
+        @read_pages[0xff] = @top_page
+      end
+
+      def map_roms
+        @read_pages.fill(@low_roms[@low_bank] || @open_bus, 0x80, 0x40)
+        @read_pages.fill(@high_roms[@high_bank] || @open_bus, 0xc0, 0x3c)
+        @read_pages[0xfc] = @high_roms[0]
+      end
+    end
+  end
+end

data/lib/badline/plus4/cpu.rb

@@ -0,0 +1,10 @@
+# frozen_string_literal: true
+
+module Badline
+  class Plus4
+    # The 7501 or 8501, a 6510 core without an NMI pin, on the Plus4::Bus.
+    class CPU
+      include Badline::Chips::CPU::Core
+    end
+  end
+end

data/lib/badline/plus4/cpu_port.rb

@@ -0,0 +1,93 @@
+# frozen_string_literal: true
+
+module Badline
+  class Plus4
+    # The 7501's I/O port at $00 (direction) and $01 (data). Its seven
+    # pins carry the serial bus and the cassette port, and none of them
+    # banks memory:
+    #
+    # - P0, P1 and P2 drive the serial bus's DATA, CLK and ATN through
+    #   inverters, so a 1 pulls the line low, and P1 is the cassette write
+    #   line too.
+    # - P3 runs the cassette motor while it is low.
+    # - P4 reads the cassette read line, P6 the serial CLK line and P7 the
+    #   DATA line, 1 while the line is high.
+    # - P5 has no pin and reads 1.
+    #
+    # An output pin reads back what it drives. A pin left as an input reads
+    # what drives it from outside, and the serial outputs, P0-P2, float high
+    # there, so they pull their lines, as an output of 1 does.
+    class CPUPort
+      DATA_OUT = 0x01
+      CLK_OUT = 0x02
+      ATN_OUT = 0x04
+      MOTOR = 0x08
+      TAPE_READ = 0x10
+      CLK_IN = 0x40
+      DATA_IN = 0x80
+
+      attr_reader :ddr, :data
+
+      def initialize(serial_bus:, datasette:)
+        @serial_bus = serial_bus
+        @datasette = datasette
+        @ddr = 0
+        @data = 0
+      end
+
+      def reset!
+        @ddr = 0
+        @data = 0
+        changed
+      end
+
+      def peek(addr)
+        return @ddr if addr.zero?
+
+        (@data & @ddr) | (inputs & ~@ddr & 0xff)
+      end
+
+      def poke(addr, value)
+        if addr.zero?
+          @ddr = value
+        else
+          @data = value
+        end
+        changed
+      end
+
+      # The pins' levels as they leave the chip, inputs floating high.
+      def levels = (@data & @ddr) | (~@ddr & 0xff)
+
+      # The serial bus lines the port pulls low, as Drives::SerialBus host
+      # lines.
+      def serial_lines
+        out = levels
+        lines = 0
+        lines |= Drives::SerialBus::HOST_ATN_OUT if out.anybits?(ATN_OUT)
+        lines |= Drives::SerialBus::HOST_CLK_OUT if out.anybits?(CLK_OUT)
+        lines |= Drives::SerialBus::HOST_DATA_OUT if out.anybits?(DATA_OUT)
+        lines
+      end
+
+      private
+
+      def inputs
+        value = 0x2f
+        value |= TAPE_READ if @datasette.read_high?
+        low = @serial_bus.low_lines
+        value |= CLK_IN unless low.anybits?(Drives::SerialBus::CLK)
+        value |= DATA_IN unless low.anybits?(Drives::SerialBus::DATA)
+        value
+      end
+
+      def changed
+        lines = serial_lines
+        @serial_bus.host_lines = lines unless lines == @serial_bus.host_lines
+        out = levels
+        @datasette.motor = out.nobits?(MOTOR)
+        @datasette.write_line = out.anybits?(CLK_OUT)
+      end
+    end
+  end
+end

data/lib/badline/plus4/keyboard_port.rb

@@ -0,0 +1,51 @@
+# frozen_string_literal: true
+
+module Badline
+  class Plus4
+    # The keyboard: the 6529 at $FD30-$FD3F, whose eight outputs drive the
+    # key matrix's lines, and the TED's K0-K7 inputs, which $FF08 latches
+    # (Chips::TED#keyboard_port=). The KERNAL's scan ($DB11) writes each
+    # line's mask to $FD30 and $FF08 and reads the keys back from $FF08,
+    # and its key table at $E026 puts each key at line times 8 plus input
+    # bit.
+    #
+    # The 6529 is a quasi-bidirectional latch: a read returns what was
+    # written to it.
+    class KeyboardPort
+      # One row of keys per 6529 output, in K0-K7 order, after the
+      # KERNAL's key table. HELP is the KERNAL's F7, and the two SHIFT keys
+      # share one place.
+      MATRIX = [
+        %i[delete return £ help f1 f2 f3 @],
+        %i[3 w a 4 z s e lshift],
+        %i[5 r d 6 c f t x],
+        %i[7 y g 8 b h u v],
+        %i[9 i j 0 m k o n],
+        %i[crsr_down p l crsr_up . : - ,],
+        %i[crsr_left * ; crsr_right esc = + /],
+        %i[1 clr_home control 2 space cbm q run_stop]
+      ].freeze
+
+      attr_reader :keyboard, :output
+
+      def initialize(keyboard)
+        @keyboard = keyboard
+        @output = 0xff
+      end
+
+      def reset!
+        @output = 0xff
+      end
+
+      def peek(_addr) = @output
+
+      def poke(_addr, value)
+        @output = value
+      end
+
+      # The K0-K7 inputs the TED latches on a write of +_value+ to $FF08:
+      # high but where a held key joins a line the 6529 pulls low.
+      def latch(_value) = @keyboard.scan(@output, 0xff).last
+    end
+  end
+end

data/lib/badline/plus4/model.rb

@@ -0,0 +1,38 @@
+# frozen_string_literal: true
+
+module Badline
+  class Plus4
+    # The 264 series machines badline builds by name, after xplus4's
+    # -model names, with the C116 as another name for the C16: one board
+    # design with its RAM, its video standard and KERNAL, and whether the
+    # Plus/4's own parts are fitted (the 3-plus-1 function ROMs, the 6551
+    # ACIA and the user port's 6529).
+    module Model
+      Profile = Data.define(:name, :ram_kb, :ted, :kernal, :plus4_parts)
+
+      PLUS4 = Profile.new(name: "plus4", ram_kb: 64, ted: Chips::TED::PAL, kernal: "plus4/kernal-pal.rom",
+                          plus4_parts: true)
+      PLUS4_NTSC = Profile.new(name: "plus4ntsc", ram_kb: 64, ted: Chips::TED::NTSC,
+                               kernal: "plus4/kernal-ntsc.rom", plus4_parts: true)
+      C16 = Profile.new(name: "c16", ram_kb: 16, ted: Chips::TED::PAL, kernal: "plus4/kernal-pal.rom",
+                        plus4_parts: false)
+      C16_NTSC = Profile.new(name: "c16ntsc", ram_kb: 16, ted: Chips::TED::NTSC, kernal: "plus4/kernal-ntsc.rom",
+                             plus4_parts: false)
+
+      ALL = [PLUS4, PLUS4_NTSC, C16, C16_NTSC].freeze
+
+      # Other names a model goes by.
+      ALIASES = { "c116" => "c16" }.freeze
+
+      # The RAM sizes a machine can have, in K.
+      RAM_SIZES = [16, 32, 64].freeze
+
+      def self.named(name)
+        model = ALL.find { |candidate| candidate.name == ALIASES.fetch(name, name) }
+        raise ArgumentError, "no Plus/4 model named #{name}" if model.nil?
+
+        model
+      end
+    end
+  end
+end

data/lib/badline/plus4/user_port.rb

@@ -0,0 +1,31 @@
+# frozen_string_literal: true
+
+module Badline
+  class Plus4
+    # The Plus/4's user port 6529 at $FD10-$FD1F, a quasi-bidirectional
+    # latch: a line reads low where the latch or the outside pulls it. With
+    # nothing plugged into the user port, the outside pulls only bit 2, the
+    # cassette sense switch, low while a key is down on the deck. The
+    # KERNAL's IRQ reads it there ($CFBF).
+    class UserPort
+      TAPE_SENSE = 0x04
+
+      attr_reader :output
+
+      def initialize(datasette)
+        @datasette = datasette
+        @output = 0xff
+      end
+
+      def reset!
+        @output = 0xff
+      end
+
+      def peek(_addr) = @datasette.sense_low? ? @output & ~TAPE_SENSE : @output
+
+      def poke(_addr, value)
+        @output = value
+      end
+    end
+  end
+end