axi_tdl 0.2.0 → 0.2.4

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Files changed (41) hide show
  1. checksums.yaml +4 -4
  2. data/.github/workflows/gem-push.yml +46 -28
  3. data/.github/workflows/ruby.yml +1 -1
  4. data/.gitignore +2 -1
  5. data/.travis.yml +1 -0
  6. data/axi_tdl.gemspec +1 -1
  7. data/lib/axi/AXI4/axi4_long_to_axi4_wide_B1.sv +5 -3
  8. data/lib/axi/AXI4/long_axis_to_axi4_wr.rb +1 -0
  9. data/lib/axi/AXI4/odata_pool_axi4_A4.sv +173 -0
  10. data/lib/axi/AXI4/packet_fifo/axi4_packet_fifo_B1.sv +66 -0
  11. data/lib/axi/AXI4/packet_fifo/axi4_rd_packet_fifo_A1.sv +260 -0
  12. data/lib/axi/AXI4/packet_fifo/axi4_wr_packet_fifo_A1.sv +192 -0
  13. data/lib/axi/AXI4/wide_axis_to_axi4_wr.sv +1 -1
  14. data/lib/axi/AXI_stream/axi_stream_split_channel.sv +21 -21
  15. data/lib/axi/AXI_stream/axi_streams_combin.sv +2 -1
  16. data/lib/axi/AXI_stream/axi_streams_combin_A1.sv +2 -1
  17. data/lib/axi/AXI_stream/axi_streams_scaler.sv +2 -1
  18. data/lib/axi/AXI_stream/axi_streams_scaler_A1.sv +2 -1
  19. data/lib/axi/AXI_stream/axis_combin_with_fifo.sv +2 -1
  20. data/lib/axi/AXI_stream/axis_head_cut_verc.rb +2 -0
  21. data/lib/axi/AXI_stream/gen_big_field_table.sv +3 -2
  22. data/lib/axi/AXI_stream/packet_fifo/axi_stream_packet_fifo_B1F.sv +129 -0
  23. data/lib/axi/AXI_stream/parse_big_field_table_main.sv +101 -0
  24. data/lib/axi/AXI_stream/parse_big_field_table_mirror.sv +94 -0
  25. data/lib/axi/axi4_to_xilinx_ddr_native/axi4_to_native_for_ddr_ip_C2.sv +75 -0
  26. data/lib/axi/axi4_to_xilinx_ddr_native/ddr_native_fifo_A2.sv +206 -0
  27. data/lib/axi/axi4_to_xilinx_ddr_native/ddr_native_fifo_B1.sv +297 -0
  28. data/lib/axi/axi4_to_xilinx_ddr_native/model_ddr_ip_app.sv +2 -2
  29. data/lib/axi/common/common_ram_wrapper.sv +1 -1
  30. data/lib/axi/data_interface/data_inf_c/data_c_pipe_sync_seam.sv +11 -11
  31. data/lib/axi/data_interface/data_inf_c/data_c_scaler.sv +2 -1
  32. data/lib/axi/data_interface/data_inf_c/data_c_scaler_A1.sv +2 -1
  33. data/lib/axi/data_interface/data_streams_combin.sv +2 -1
  34. data/lib/axi/data_interface/data_streams_combin_A1.sv +2 -1
  35. data/lib/axi/data_interface/data_streams_scaler.sv +2 -1
  36. data/lib/axi_tdl/version.rb +1 -1
  37. data/lib/tdl/axi4/axi4_interconnect_verb.rb +5 -1
  38. data/lib/tdl/examples/2_hdl_class/tmp/test_vcs_string.sv +1 -1
  39. data/lib/tdl/examples/8_top_module/test_top.sv +1 -1
  40. data/lib/tdl/rebuild_ele/ele_base.rb +14 -0
  41. metadata +13 -3
@@ -0,0 +1,75 @@
1
+ /**********************************************
2
+ _______________________________________
3
+ ___________ Cook Darwin __________
4
+ _______________________________________
5
+ descript:
6
+ author : Cook.Darwin
7
+ Version: VERA.0.1 2017/9/28
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+ user axi4 addr_step
9
+ Version: VERC.0.0 2018/11/23
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+ rebuild
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+ Version: VERC.1.0 ###### Fri Apr 24 10:14:28 CST 2020
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+ use ddr_native_fifo_verb
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+ Version: VERC.2.0
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+ 使用 ddr_native_fifo_B1 具有跨时钟功能
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+ creaded: 2016/10/12
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+ madified:
17
+ ***********************************************/
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+ `timescale 1ns / 1ps
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+ (* axi4 = "true" *)
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+ module axi4_to_native_for_ddr_ip_C2 #(
21
+ parameter ADDR_WIDTH = 27,
22
+ parameter DATA_WIDTH = 256
23
+ )(
24
+ axi_inf.slaver ddr3_axi4_inf,
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+ input ui_clock,
26
+ input ui_rstn,
27
+ output logic[ADDR_WIDTH-1:0] app_addr,
28
+ output logic[2:0] app_cmd,
29
+ output logic app_en,
30
+ output logic[DATA_WIDTH-1:0] app_wdf_data,
31
+ output logic app_wdf_end,
32
+ output logic[DATA_WIDTH/8-1:0] app_wdf_mask,
33
+ output logic app_wdf_wren,
34
+ input [DATA_WIDTH-1:0] app_rd_data,
35
+ input app_rd_data_end,
36
+ input app_rd_data_valid,
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+ input app_rdy,
38
+ input app_wdf_rdy,
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+ input logic init_calib_complete
40
+ );
41
+
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+ axi_stream_inf #(DATA_WIDTH + ADDR_WIDTH + 3) axis_inf (ddr3_axi4_inf.axi_aclk,ddr3_axi4_inf.axi_aresetn,1'b1);
43
+ axi_stream_inf #(DATA_WIDTH) axis_rd_inf (ddr3_axi4_inf.axi_aclk,ddr3_axi4_inf.axi_aresetn,1'b1);
44
+
45
+ ddr_axi4_to_axis ddr_axi4_to_axis_inst(
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+ /* axi4.slaver */ .axi4_inf (ddr3_axi4_inf ),
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+ /* axi_stream_inf.master */ .axis_inf (axis_inf ),
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+ /* axi_stream_inf.slaver */ .axis_rd_inf (axis_rd_inf) //DSIZE
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+ );
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+
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+ ddr_native_fifo_B1 #(
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+ .ADDR_WIDTH (ADDR_WIDTH ),
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+ .DATA_WIDTH (DATA_WIDTH )
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+ )ddr_native_fifo_B1_inst(
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+ /* axi_stream_inf.slaver */ .axis_inf (axis_inf ),
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+ /* axi_stream_inf.master */ .axis_rd_inf (axis_rd_inf ),
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+ /* //---DDR IP */
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+ /* input */ .ui_clock (ui_clock ),
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+ /* input */ .ui_rstn (ui_rstn ),
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+ /* output logic[ADDR_WIDTH-1:0] */ .app_addr (app_addr ),
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+ /* output logic[2:0] */ .app_cmd (app_cmd ),
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+ /* output logic */ .app_en (app_en ),
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+ /* output logic[DATA_WIDTH-1:0] */ .app_wdf_data (app_wdf_data ),
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+ /* output logic */ .app_wdf_end (app_wdf_end ),
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+ /* output logic[DATA_WIDTH/8-1:0]*/ .app_wdf_mask (app_wdf_mask ),
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+ /* output logic */ .app_wdf_wren (app_wdf_wren ),
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+ /* input [DATA_WIDTH-1:0] */ .app_rd_data (app_rd_data ),
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+ /* input */ .app_rd_data_end (app_rd_data_end ),
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+ /* input */ .app_rd_data_valid (app_rd_data_valid ),
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+ /* input */ .app_rdy (app_rdy ),
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+ /* input */ .app_wdf_rdy (app_wdf_rdy ),
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+ /* input logic */ .init_calib_complete (init_calib_complete )
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+ );
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+
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+ endmodule
@@ -0,0 +1,206 @@
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+ /**********************************************
2
+ _______________________________________
3
+ ___________ Cook Darwin __________
4
+ _______________________________________
5
+ descript:
6
+ author : Cook.Darwin
7
+ Version: VERA.1.0
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+ regenerate axis_rd_inf.axis_tlast
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+ creaded: 2018/11/26
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+ madified:
11
+ ***********************************************/
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+ `timescale 1ns / 1ps
13
+ module ddr_native_fifo_A2 #(
14
+ parameter ADDR_WIDTH = 27,
15
+ parameter DATA_WIDTH = 256
16
+ )(
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+ axi_stream_inf.slaver axis_inf,
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+ axi_stream_inf.master axis_rd_inf,
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+ //---DDR IP
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+ input ui_clock,
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+ input ui_rstn,
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+ output logic[ADDR_WIDTH-1:0] app_addr,
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+ output logic[2:0] app_cmd,
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+ output logic app_en,
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+ output logic[DATA_WIDTH-1:0] app_wdf_data,
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+ output logic app_wdf_end,
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+ output logic[DATA_WIDTH/8-1:0] app_wdf_mask,
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+ output logic app_wdf_wren,
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+ input [DATA_WIDTH-1:0] app_rd_data,
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+ input app_rd_data_end,
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+ input app_rd_data_valid,
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+ input app_rdy,
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+ input app_wdf_rdy,
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+ input logic init_calib_complete
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+ );
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+
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+ assign app_wdf_mask = '0;
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+ assign app_wdf_end = 1'b1;
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+
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+
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+ initial begin
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+ assert(axis_inf.DSIZE == (ADDR_WIDTH + DATA_WIDTH + 3))
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+ else begin
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+ $error("axis_inf.DSIZE#%0d != (3 + ADDR_WIDTH#%0d + DATA_WIDTH#%0d)",axis_inf.DSIZE,ADDR_WIDTH,DATA_WIDTH);
45
+ $stop;
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+ end
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+ end
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+
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+ logic clock,rst_n;
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+ assign clock = axis_inf.aclk;
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+ assign rst_n = axis_inf.aresetn;
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+
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+ logic aux_fifo_empty;
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+ logic aux_fifo_full;
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+ logic aux_fifo_wr_en;
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+ logic aux_fifo_rd_en;
57
+ logic [ADDR_WIDTH + 3 -1:0] aux_fifo_wdata,aux_fifo_rdata;
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+
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+ independent_clock_fifo #(
60
+ .DEPTH ( 8 ),
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+ .DSIZE (ADDR_WIDTH + 3 )
62
+ )common_fifo_addr_inst(
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+ // /* input */ .clock (clock ),
64
+ // /* input */ .rst_n (rst_n ),
65
+ /* input */ .wr_clk (clock ),
66
+ /* input */ .wr_rst_n (rst_n ),
67
+ /* input */ .rd_clk (ui_clock ),
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+ /* input */ .rd_rst_n (ui_rstn ),
69
+ /* input [DSIZE-1:0] */ .wdata (aux_fifo_wdata ),
70
+ /* input */ .wr_en (aux_fifo_wr_en ),
71
+ /* output logic[DSIZE-1:0] */ .rdata (aux_fifo_rdata ),
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+ /* input */ .rd_en (aux_fifo_rd_en ),
73
+ /* output logic[CSIZE-1:0] */ .count (),
74
+ /* output logic */ .empty (aux_fifo_empty ),
75
+ /* output logic */ .full (aux_fifo_full )
76
+ );
77
+
78
+ assign aux_fifo_wdata = axis_inf.axis_tdata[DATA_WIDTH +: (ADDR_WIDTH+3)];
79
+ assign aux_fifo_wr_en = axis_inf.axis_tvalid && axis_inf.axis_tready;
80
+
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+ //-->> DATA
82
+ logic w_fifo_empty;
83
+ logic w_fifo_full;
84
+ logic w_fifo_wr_en;
85
+ logic w_fifo_rd_en;
86
+ logic [DATA_WIDTH-1:0] w_fifo_wdata,w_fifo_rdata;
87
+
88
+ independent_clock_fifo #(
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+ .DEPTH ( 8 ),
90
+ .DSIZE (DATA_WIDTH )
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+ )common_fifo_data_inst(
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+ // /* input */ .clock (clock ),
93
+ // /* input */ .rst_n (rst_n ),
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+ /* input */ .wr_clk (clock ),
95
+ /* input */ .wr_rst_n (rst_n ),
96
+ /* input */ .rd_clk (ui_clock ),
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+ /* input */ .rd_rst_n (ui_rstn ),
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+ /* input [DSIZE-1:0] */ .wdata (w_fifo_wdata ),
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+ /* input */ .wr_en (w_fifo_wr_en ),
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+ /* output logic[DSIZE-1:0] */ .rdata (w_fifo_rdata ),
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+ /* input */ .rd_en (w_fifo_rd_en ),
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+ /* output logic[CSIZE-1:0] */ .count (),
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+ /* output logic */ .empty (w_fifo_empty ),
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+ /* output logic */ .full (w_fifo_full )
105
+ );
106
+
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+ assign axis_inf.axis_tready = !aux_fifo_full && !w_fifo_full;
108
+
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+ assign w_fifo_wdata = axis_inf.axis_tdata[DATA_WIDTH-1:0];
110
+ assign w_fifo_wr_en = aux_fifo_wr_en && axis_inf.axis_tdata[(DATA_WIDTH + ADDR_WIDTH) +: 3] == 3'b000;
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+ assign app_wdf_data = w_fifo_rdata;
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+ assign app_wdf_wren = !w_fifo_empty;
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+ assign w_fifo_rd_en = (app_wdf_wren && app_wdf_rdy);
114
+
115
+ //-- APP
116
+ assign app_en = !aux_fifo_empty;
117
+ assign aux_fifo_rd_en = app_rdy && app_en;
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+ assign app_cmd = aux_fifo_rdata[ADDR_WIDTH +: 3];
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+ assign app_addr = aux_fifo_rdata[ADDR_WIDTH-1:0];
120
+
121
+ //-->> STACK
122
+ logic rd_fifo_empty;
123
+ logic rd_fifo_full;
124
+ logic rd_fifo_wr_en;
125
+ logic rd_fifo_rd_en;
126
+ logic [8+2:0] rd_fifo_wdata,rd_fifo_rdata;
127
+
128
+ common_fifo #(
129
+ .DEPTH ( 8 ),
130
+ .DSIZE ( 9+2 )
131
+ )common_fifo_rd_last_inst(
132
+ /* input */ .clock (clock ),
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+ /* input */ .rst_n (rst_n ),
134
+ /* input [DSIZE-1:0] */ .wdata (rd_fifo_wdata ),
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+ /* input */ .wr_en (rd_fifo_wr_en ),
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+ /* output logic[DSIZE-1:0] */ .rdata (rd_fifo_rdata ),
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+ /* input */ .rd_en (rd_fifo_rd_en ),
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+ /* output logic[CSIZE-1:0] */ .count (),
139
+ /* output logic */ .empty (rd_fifo_empty ),
140
+ /* output logic */ .full (rd_fifo_full )
141
+ );
142
+
143
+ assign rd_fifo_wdata = {axis_inf.axis_tcnt[8:0]};
144
+ assign rd_fifo_wr_en = axis_inf.axis_tvalid && axis_inf.axis_tready && axis_inf.axis_tlast && axis_inf.axis_tdata[(DATA_WIDTH + ADDR_WIDTH) +: 3] == 3'b001;
145
+ assign rd_fifo_rd_en = axis_rd_inf.axis_tvalid && axis_rd_inf.axis_tlast;
146
+
147
+ // read valid conter
148
+ logic[8+2:0] rd_vld_cnt;
149
+ always@(posedge clock,negedge rst_n)
150
+ if(~rst_n) rd_vld_cnt <= '0;
151
+ else begin
152
+ if(axis_rd_inf.axis_tvalid && axis_rd_inf.axis_tlast)
153
+ rd_vld_cnt <= '0;
154
+ else if(axis_rd_inf.axis_tvalid)
155
+ rd_vld_cnt <= rd_vld_cnt + 1'b1;
156
+ else rd_vld_cnt <= rd_vld_cnt;
157
+ end
158
+
159
+ always@(posedge clock,negedge rst_n)
160
+ if(~rst_n) axis_rd_inf.axis_tlast <= 1'b0;
161
+ else begin
162
+ if(!rd_fifo_empty && rd_fifo_rdata == '0)
163
+ // if(axis_rd_inf.axis_tvalid && axis_rd_inf.axis_tready && axis_rd_inf.axis_tlast && axis_rd_inf.axis_tcnt == '0)
164
+ axis_rd_inf.axis_tlast <= 1'b1;
165
+ else if(axis_rd_inf.axis_tvalid && axis_rd_inf.axis_tready && axis_rd_inf.axis_tlast)
166
+ axis_rd_inf.axis_tlast <= 1'b0;
167
+ else if(axis_rd_inf.axis_tvalid && rd_vld_cnt >= (rd_fifo_rdata-9'd1) && !rd_fifo_empty)
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+ axis_rd_inf.axis_tlast <= 1'b1;
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+ else axis_rd_inf.axis_tlast <= axis_rd_inf.axis_tlast;
170
+ end
171
+
172
+ //-- APP
173
+ // assign axis_rd_inf.axis_tdata = app_rd_data;
174
+ // assign axis_rd_inf.axis_tvalid = app_rd_data_valid;
175
+ assign axis_rd_inf.axis_tkeep = '1;
176
+ assign axis_rd_inf.axis_tuser = '0;
177
+
178
+ wide_fifo #( //min 512 depth
179
+ .DSIZE (DATA_WIDTH )
180
+ )wide_fifo_inst(
181
+ /* input */ .wr_clk (ui_clock ),
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+ /* input */ .wr_rst (~ui_rstn ),
183
+ /* input */ .rd_clk (clock ),
184
+ /* input */ .rd_rst (~rst_n ),
185
+ /* input [DSIZE-1:0] */ .din (app_rd_data ),
186
+ /* input */ .wr_en (app_rd_data_valid ),
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+ /* input */ .rd_en (axis_rd_inf.axis_tvalid && axis_rd_inf.axis_tready ),
188
+ /* output [DSIZE-1:0] */ .dout (axis_rd_inf.axis_tdata ),
189
+ /* output */ .full (wide_fifo_full ),
190
+ /* output */ .empty (wide_fifo_empty )
191
+ );
192
+
193
+ assign axis_rd_inf.axis_tvalid = ~wide_fifo_empty;
194
+
195
+ // data overflow
196
+ (* dont_touch = "true" *)logic rd_data_overflow;
197
+
198
+ always@(posedge clock,negedge rst_n)
199
+ if(~rst_n) rd_data_overflow <= 1'b0;
200
+ else begin
201
+ if(axis_rd_inf.axis_tvalid && ~axis_rd_inf.axis_tready)
202
+ rd_data_overflow <= 1'b1;
203
+ else rd_data_overflow <= rd_data_overflow;
204
+ end
205
+
206
+ endmodule
@@ -0,0 +1,297 @@
1
+ /**********************************************
2
+ _______________________________________
3
+ ___________ Cook Darwin __________
4
+ _______________________________________
5
+ descript:
6
+ author : Cook.Darwin
7
+ Version: VERB.0.0 : ###### Fri Apr 24 10:02:44 CST 2020
8
+ add fifo buffer for read
9
+ creaded: 2018/11/26
10
+ madified: ###### Fri Apr 24 10:02:31 CST 2020
11
+ ***********************************************/
12
+ `timescale 1ns / 1ps
13
+ module ddr_native_fifo_B1 #(
14
+ parameter ADDR_WIDTH = 27,
15
+ parameter DATA_WIDTH = 256
16
+ )(
17
+ axi_stream_inf.slaver axis_inf,
18
+ axi_stream_inf.master axis_rd_inf, // 和 axis_inf一个时钟域
19
+ //---DDR IP
20
+ input ui_clock,
21
+ input ui_rstn,
22
+ output logic[ADDR_WIDTH-1:0] app_addr,
23
+ output logic[2:0] app_cmd,
24
+ output logic app_en,
25
+ output logic[DATA_WIDTH-1:0] app_wdf_data,
26
+ output logic app_wdf_end,
27
+ output logic[DATA_WIDTH/8-1:0] app_wdf_mask,
28
+ output logic app_wdf_wren,
29
+ input [DATA_WIDTH-1:0] app_rd_data,
30
+ input app_rd_data_end,
31
+ input app_rd_data_valid,
32
+ input app_rdy,
33
+ input app_wdf_rdy,
34
+ input logic init_calib_complete
35
+ );
36
+
37
+ assign app_wdf_mask = '0;
38
+ assign app_wdf_end = 1'b1;
39
+
40
+
41
+ initial begin
42
+ assert(axis_inf.DSIZE == (ADDR_WIDTH + DATA_WIDTH + 3))
43
+ else begin
44
+ $error("axis_inf.DSIZE#%0d != (3 + ADDR_WIDTH#%0d + DATA_WIDTH#%0d)",axis_inf.DSIZE,ADDR_WIDTH,DATA_WIDTH);
45
+ $stop;
46
+ end
47
+ end
48
+
49
+ logic clock,rst_n;
50
+ assign clock = axis_inf.aclk;
51
+ assign rst_n = axis_inf.aresetn;
52
+
53
+ logic aux_fifo_empty;
54
+ logic aux_fifo_full;
55
+ logic aux_fifo_wr_en;
56
+ logic aux_fifo_rd_en;
57
+ logic [ADDR_WIDTH + 3 -1:0] aux_fifo_wdata,aux_fifo_rdata;
58
+
59
+ independent_clock_fifo #(
60
+ .DEPTH ( 8 ),
61
+ .DSIZE (ADDR_WIDTH + 3 )
62
+ )independent_clock_fifo_addr_inst(
63
+ // /* input */ .clock (clock ),
64
+ // /* input */ .rst_n (rst_n ),
65
+ /* input */ .wr_clk (clock ),
66
+ /* input */ .wr_rst_n (rst_n ),
67
+ /* input */ .rd_clk (ui_clock ),
68
+ /* input */ .rd_rst_n (ui_rstn ),
69
+ /* input [DSIZE-1:0] */ .wdata (aux_fifo_wdata ),
70
+ /* input */ .wr_en (aux_fifo_wr_en ),
71
+ /* output logic[DSIZE-1:0] */ .rdata (aux_fifo_rdata ),
72
+ /* input */ .rd_en (aux_fifo_rd_en ),
73
+ /* output logic */ .empty (aux_fifo_empty ),
74
+ /* output logic */ .full (aux_fifo_full )
75
+ );
76
+
77
+ assign aux_fifo_wdata = axis_inf.axis_tdata[DATA_WIDTH +: (ADDR_WIDTH+3)];
78
+ assign aux_fifo_wr_en = axis_inf.axis_tvalid && axis_inf.axis_tready;
79
+
80
+ //-->> DATA
81
+ logic w_fifo_empty;
82
+ logic w_fifo_full;
83
+ logic w_fifo_wr_en;
84
+ logic w_fifo_rd_en;
85
+ logic [DATA_WIDTH-1:0] w_fifo_wdata,w_fifo_rdata;
86
+
87
+ logic rd_atom_fifo_full;
88
+
89
+ independent_clock_fifo #(
90
+ .DEPTH ( 8 ),
91
+ .DSIZE (DATA_WIDTH )
92
+ )independent_clock_fifo_data_inst(
93
+ // /* input */ .clock (clock ),
94
+ // /* input */ .rst_n (rst_n ),
95
+ /* input */ .wr_clk (clock ),
96
+ /* input */ .wr_rst_n (rst_n ),
97
+ /* input */ .rd_clk (ui_clock ),
98
+ /* input */ .rd_rst_n (ui_rstn ),
99
+ /* input [DSIZE-1:0] */ .wdata (w_fifo_wdata ),
100
+ /* input */ .wr_en (w_fifo_wr_en ),
101
+ /* output logic[DSIZE-1:0] */ .rdata (w_fifo_rdata ),
102
+ /* input */ .rd_en (w_fifo_rd_en ),
103
+ /* output logic */ .empty (w_fifo_empty ),
104
+ /* output logic */ .full (w_fifo_full )
105
+ );
106
+
107
+ assign axis_inf.axis_tready = !aux_fifo_full && !w_fifo_full && !rd_atom_fifo_full;
108
+
109
+ assign w_fifo_wdata = axis_inf.axis_tdata[DATA_WIDTH-1:0];
110
+ assign w_fifo_wr_en = aux_fifo_wr_en && axis_inf.axis_tdata[(DATA_WIDTH + ADDR_WIDTH) +: 3] == 3'b000;
111
+ assign app_wdf_data = w_fifo_rdata;
112
+ assign app_wdf_wren = !w_fifo_empty;
113
+ assign w_fifo_rd_en = (app_wdf_wren && app_wdf_rdy);
114
+
115
+ //-- APP
116
+ assign app_en = !aux_fifo_empty;
117
+ assign aux_fifo_rd_en = app_rdy && app_en;
118
+ assign app_cmd = aux_fifo_rdata[ADDR_WIDTH +: 3];
119
+ assign app_addr = aux_fifo_rdata[ADDR_WIDTH-1:0];
120
+
121
+ //-->> STACK
122
+ logic rd_fifo_empty;
123
+ // (* dont_touch="true" *)(* mark_debug="true" *)
124
+ logic rd_fifo_full_error; // when rd_fifo_full high meet that error raising
125
+ logic rd_fifo_wr_en;
126
+ logic rd_fifo_rd_en;
127
+ logic [15:0] rd_fifo_wdata,rd_fifo_rdata;
128
+ // (* dont_touch="true" *)(* mark_debug="true" *)
129
+ logic [16:0] rd_fifo_count;
130
+
131
+ common_fifo #(
132
+ .DEPTH ( 8 ),
133
+ .DSIZE ( 16 )
134
+ )common_fifo_rd_last_inst(
135
+ /* input */ .clock (clock ),
136
+ /* input */ .rst_n (rst_n ),
137
+ // /* input */ .wr_clk (clock ),
138
+ // /* input */ .wr_rst_n (rst_n ),
139
+ // /* input */ .rd_clk (ui_clock ),
140
+ // /* input */ .rd_rst_n (ui_rstn ),
141
+ /* input [DSIZE-1:0] */ .wdata (rd_fifo_wdata ),
142
+ /* input */ .wr_en (rd_fifo_wr_en ),
143
+ /* output logic[DSIZE-1:0] */ .rdata (rd_fifo_rdata ),
144
+ /* input */ .rd_en (rd_fifo_rd_en ),
145
+ /* output logic[CSIZE-1:0] */ .count (rd_fifo_count ),
146
+ /* output logic */ .empty (rd_fifo_empty ),
147
+ /* output logic */ .full (rd_fifo_full_error )
148
+ );
149
+
150
+ assign rd_fifo_wdata = {axis_inf.axis_tcnt[15:0]};
151
+ assign rd_fifo_wr_en = axis_inf.axis_tvalid && axis_inf.axis_tready && axis_inf.axis_tlast && axis_inf.axis_tdata[(DATA_WIDTH + ADDR_WIDTH) +: 3] == 3'b001;
152
+ assign rd_fifo_rd_en = axis_rd_inf.axis_tvalid && axis_rd_inf.axis_tready && axis_rd_inf.axis_tlast;
153
+
154
+ always@(posedge clock,negedge rst_n)
155
+ if(~rst_n) axis_rd_inf.axis_tlast <= 1'b0;
156
+ else begin
157
+ if(!rd_fifo_empty && rd_fifo_rdata == '0)
158
+ // if(axis_rd_inf.axis_tvalid && axis_rd_inf.axis_tready && axis_rd_inf.axis_tlast && axis_rd_inf.axis_tcnt == '0)
159
+ axis_rd_inf.axis_tlast <= 1'b1;
160
+ else if(axis_rd_inf.axis_tvalid && axis_rd_inf.axis_tready && axis_rd_inf.axis_tcnt == (rd_fifo_rdata-9'd1) && !rd_fifo_empty)
161
+ axis_rd_inf.axis_tlast <= 1'b1;
162
+ else if(axis_rd_inf.axis_tvalid && axis_rd_inf.axis_tready && axis_rd_inf.axis_tlast)
163
+ axis_rd_inf.axis_tlast <= 1'b0;
164
+ else axis_rd_inf.axis_tlast <= axis_rd_inf.axis_tlast;
165
+ end
166
+
167
+ //-- APP
168
+ //-- >> READ BUFFER
169
+ // assign axis_rd_inf.axis_tdata = app_rd_data;
170
+ // assign axis_rd_inf.axis_tvalid = app_rd_data_valid;
171
+ // assign axis_rd_inf.axis_tkeep = '1;
172
+ // assign axis_rd_inf.axis_tuser = '0;
173
+
174
+ // contrl cmd exec
175
+ // logic rd_atom_fifo_wdata
176
+ logic rd_atom_fifo_wr_en;
177
+ // logic rd_atom_fifo_rdata
178
+ logic rd_atom_fifo_rd_en;
179
+ // logic rd_atom_fifo_count
180
+ logic rd_atom_fifo_empty;
181
+ // logic rd_atom_fifo_full
182
+
183
+ common_fifo #(
184
+ .DEPTH ( 256 ),
185
+ .DSIZE ( 1 )
186
+ )common_fifo_rd_cmd_inst(
187
+ /* input */ .clock (clock ),
188
+ /* input */ .rst_n (rst_n ),
189
+ /* input [DSIZE-1:0] */ .wdata (1'b0 ),
190
+ /* input */ .wr_en (rd_atom_fifo_wr_en ),
191
+ /* output logic[DSIZE-1:0] */ .rdata ( ),
192
+ /* input */ .rd_en (rd_atom_fifo_rd_en ),
193
+ /* output logic[CSIZE-1:0] */ .count ( ),
194
+ /* output logic */ .empty (rd_atom_fifo_empty ),
195
+ /* output logic */ .full (rd_atom_fifo_full )
196
+ );
197
+
198
+ assign rd_atom_fifo_wr_en = axis_inf.axis_tvalid && axis_inf.axis_tready && axis_inf.axis_tdata[(DATA_WIDTH + ADDR_WIDTH) +: 3] == 3'b001;
199
+ assign rd_atom_fifo_rd_en = axis_rd_inf.axis_tvalid && axis_rd_inf.axis_tready;
200
+
201
+ // (* dont_touch="true" *)(* mark_debug="true" *)
202
+ logic wide_fifo_full;
203
+ logic wide_fifo_empty;
204
+
205
+ // wide_fifo #( //min 512 depth
206
+ // .DSIZE (DATA_WIDTH )
207
+ // )wide_fifo_inst(
208
+ // /* input */ .wr_clk (ui_clock ),
209
+ // /* input */ .wr_rst (~ui_rstn ),
210
+ // /* input */ .rd_clk (clock ),
211
+ // /* input */ .rd_rst (~rst_n ),
212
+ // /* input [DSIZE-1:0] */ .din (app_rd_data ),
213
+ // /* input */ .wr_en (app_rd_data_valid ),
214
+ // /* input */ .rd_en (axis_rd_inf.axis_tvalid && axis_rd_inf.axis_tready ),
215
+ // /* output [DSIZE-1:0] */ .dout (axis_rd_inf.axis_tdata ),
216
+ // /* output */ .full (wide_fifo_full ),
217
+ // /* output */ .empty (wide_fifo_empty )
218
+ // );
219
+
220
+ long_fifo_verb #(
221
+ .DSIZE (DATA_WIDTH),
222
+ .LENGTH (1024*2)
223
+ )long_fifo_verb_inst(
224
+ /* input */ .wr_clk (ui_clock ),
225
+ /* input */ .wr_rst (~ui_rstn ),
226
+ /* input */ .rd_clk (clock ),
227
+ /* input */ .rd_rst (~rst_n ),
228
+ /* input [DSIZE-1:0] */ .din (app_rd_data ),
229
+ /* input */ .wr_en (app_rd_data_valid ),
230
+ /* input */ .rd_en (axis_rd_inf.axis_tvalid && axis_rd_inf.axis_tready ),
231
+ /* output [DSIZE-1:0] */ .dout (axis_rd_inf.axis_tdata ),
232
+ /* output */ .full (wide_fifo_full ),
233
+ /* output */ .empty (wide_fifo_empty )
234
+ );
235
+
236
+ assign axis_rd_inf.axis_tvalid = ~wide_fifo_empty;
237
+
238
+ // TRACK
239
+ `ifdef TRACK_DDR3_STREAM
240
+ (* dont_touch="true" *)(* mark_debug="true" *)
241
+ logic[10:0] track_native_rd_cnt;
242
+ always_ff@(posedge clock,negedge rst_n)begin
243
+ if(~rst_n) track_native_rd_cnt <= '0;
244
+ else begin
245
+ if(app_en && app_cmd==3'b001 && app_rdy && app_rd_data_valid)
246
+ track_native_rd_cnt <= track_native_rd_cnt;
247
+ else if(app_en && app_cmd==3'b001 && app_rdy)
248
+ track_native_rd_cnt <= track_native_rd_cnt + 1'b1;
249
+ else if(app_rd_data_valid)
250
+ track_native_rd_cnt <= track_native_rd_cnt - 1'b1;
251
+ else track_native_rd_cnt <= track_native_rd_cnt;
252
+ end
253
+ end
254
+
255
+ (* dont_touch="true" *)(* mark_debug="true" *)
256
+ logic[10:0] track_axis_rd_cnt;
257
+ always_ff@(posedge clock,negedge rst_n)begin
258
+ if(~rst_n) track_axis_rd_cnt <= '0;
259
+ else begin
260
+ if(axis_rd_inf.axis_tvalid && axis_rd_inf.axis_tready && app_rd_data_valid)
261
+ track_axis_rd_cnt <= track_axis_rd_cnt;
262
+ else if(axis_rd_inf.axis_tvalid && axis_rd_inf.axis_tready)
263
+ track_axis_rd_cnt <= track_axis_rd_cnt - 1'b1;
264
+ else if(app_rd_data_valid)
265
+ track_axis_rd_cnt <= track_axis_rd_cnt + 1'b1;
266
+ else track_axis_rd_cnt <= track_axis_rd_cnt;
267
+ end
268
+ end
269
+ `endif
270
+
271
+ // `define TRACK_DDR3_APP
272
+ `ifdef TRACK_DDR3_APP
273
+ (* dont_touch="true" *)(* mark_debug="true" *)
274
+ logic [9:0] app_en_wr_cnt;
275
+ (* dont_touch="true" *)(* mark_debug="true" *)
276
+ logic [9:0] app_wdf_wren_cnt;
277
+
278
+ always_ff@(posedge clock,negedge rst_n)begin
279
+ if(~rst_n) app_en_wr_cnt <= '0;
280
+ else begin
281
+ if(app_en && app_cmd==3'b000 && app_rdy)
282
+ app_en_wr_cnt <= app_en_wr_cnt + 1'b1 ;
283
+ else app_en_wr_cnt <= app_en_wr_cnt;
284
+ end
285
+ end
286
+
287
+ always_ff@(posedge clock,negedge rst_n)begin
288
+ if(~rst_n) app_wdf_wren_cnt <= '0;
289
+ else begin
290
+ if(app_wdf_rdy && app_wdf_wren)
291
+ app_wdf_wren_cnt <= app_wdf_wren_cnt + 1'b1;
292
+ else app_wdf_wren_cnt <= app_wdf_wren_cnt;
293
+ end
294
+ end
295
+ `endif
296
+
297
+ endmodule
@@ -115,8 +115,8 @@ task automatic write_cmd ();
115
115
  endtask:write_cmd
116
116
 
117
117
  task automatic write_data ();
118
- logic [ADDR_WIDTH-1:0] addr;
119
- logic [DATA_WIDTH-1:0] data;
118
+ bit [ADDR_WIDTH-1:0] addr;
119
+ bit [DATA_WIDTH-1:0] data;
120
120
  fork
121
121
  forever begin
122
122
  forever begin
@@ -4,7 +4,7 @@ ___________ Cook Darwin __________
4
4
  _______________________________________
5
5
  descript:
6
6
  author : Cook.Darwin
7
- Version: VERA.0.0
7
+ Version:
8
8
  creaded: XXXX.XX.XX
9
9
  madified:
10
10
  ***********************************************/
@@ -4,7 +4,7 @@ ___________ Cook Darwin __________
4
4
  _______________________________________
5
5
  descript:
6
6
  author : Cook.Darwin
7
- Version: VERA.0.0
7
+ Version:
8
8
  creaded: XXXX.XX.XX
9
9
  madified:
10
10
  ***********************************************/
@@ -48,22 +48,22 @@ for(genvar KK0=0;KK0 < LAT;KK0++)begin
48
48
  endgenerate
49
49
  //-------- CLOCKs Total 2 ----------------------
50
50
  //--->> CheckClock <<----------------
51
- logic cc_done_9,cc_same_9;
52
- integer cc_afreq_9,cc_bfreq_9;
53
- ClockSameDomain CheckPClock_inst_9(
51
+ logic cc_done_10,cc_same_10;
52
+ integer cc_afreq_10,cc_bfreq_10;
53
+ ClockSameDomain CheckPClock_inst_10(
54
54
  /* input */ .aclk (in_inf.clock ),
55
55
  /* input */ .bclk (out_inf.clock ),
56
- /* output logic */ .done (cc_done_9),
57
- /* output logic */ .same (cc_same_9),
58
- /* output integer */ .aFreqK (cc_afreq_9),
59
- /* output integer */ .bFreqK (cc_bfreq_9)
56
+ /* output logic */ .done (cc_done_10),
57
+ /* output logic */ .same (cc_same_10),
58
+ /* output integer */ .aFreqK (cc_afreq_10),
59
+ /* output integer */ .bFreqK (cc_bfreq_10)
60
60
  );
61
61
 
62
62
  initial begin
63
- wait(cc_done_9);
64
- assert(cc_same_9)
63
+ wait(cc_done_10);
64
+ assert(cc_same_10)
65
65
  else begin
66
- $error("--- Error : `data_c_pipe_sync_seam` clock is not same, in_inf.clock< %0f M> != out_inf.clock<%0f M>",1000000.0/cc_afreq_9, 1000000.0/cc_bfreq_9);
66
+ $error("--- Error : `data_c_pipe_sync_seam` clock is not same, in_inf.clock< %0f M> != out_inf.clock<%0f M>",1000000.0/cc_afreq_10, 1000000.0/cc_bfreq_10);
67
67
  repeat(10)begin
68
68
  @(posedge in_inf.clock);
69
69
  end
@@ -1,7 +1,8 @@
1
1
  /**********************************************
2
2
  _______________________________________
3
3
  ___________ Cook Darwin __________
4
- _______________________________________descript:
4
+ _______________________________________
5
+ descript:
5
6
  author : Cook.Darwin
6
7
  Version: VERA.0.0
7
8
  creaded: 2018-4-13 12:39:59
@@ -1,7 +1,8 @@
1
1
  /**********************************************
2
2
  _______________________________________
3
3
  ___________ Cook Darwin __________
4
- _______________________________________descript:
4
+ _______________________________________
5
+ descript:
5
6
  author : Cook.Darwin
6
7
  Version: VERA.1.0 2018-4-16 12:04:47
7
8
  add trigger
@@ -1,7 +1,8 @@
1
1
  /**********************************************
2
2
  _______________________________________
3
3
  ___________ Cook Darwin __________
4
- _______________________________________descript:
4
+ _______________________________________
5
+ descript:
5
6
  author : Cook.Darwin
6
7
  Version: VERA.0.0
7
8
  build from data_streams_scaler VA.0.1