axi_tdl 0.2.0 → 0.2.4
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- checksums.yaml +4 -4
- data/.github/workflows/gem-push.yml +46 -28
- data/.github/workflows/ruby.yml +1 -1
- data/.gitignore +2 -1
- data/.travis.yml +1 -0
- data/axi_tdl.gemspec +1 -1
- data/lib/axi/AXI4/axi4_long_to_axi4_wide_B1.sv +5 -3
- data/lib/axi/AXI4/long_axis_to_axi4_wr.rb +1 -0
- data/lib/axi/AXI4/odata_pool_axi4_A4.sv +173 -0
- data/lib/axi/AXI4/packet_fifo/axi4_packet_fifo_B1.sv +66 -0
- data/lib/axi/AXI4/packet_fifo/axi4_rd_packet_fifo_A1.sv +260 -0
- data/lib/axi/AXI4/packet_fifo/axi4_wr_packet_fifo_A1.sv +192 -0
- data/lib/axi/AXI4/wide_axis_to_axi4_wr.sv +1 -1
- data/lib/axi/AXI_stream/axi_stream_split_channel.sv +21 -21
- data/lib/axi/AXI_stream/axi_streams_combin.sv +2 -1
- data/lib/axi/AXI_stream/axi_streams_combin_A1.sv +2 -1
- data/lib/axi/AXI_stream/axi_streams_scaler.sv +2 -1
- data/lib/axi/AXI_stream/axi_streams_scaler_A1.sv +2 -1
- data/lib/axi/AXI_stream/axis_combin_with_fifo.sv +2 -1
- data/lib/axi/AXI_stream/axis_head_cut_verc.rb +2 -0
- data/lib/axi/AXI_stream/gen_big_field_table.sv +3 -2
- data/lib/axi/AXI_stream/packet_fifo/axi_stream_packet_fifo_B1F.sv +129 -0
- data/lib/axi/AXI_stream/parse_big_field_table_main.sv +101 -0
- data/lib/axi/AXI_stream/parse_big_field_table_mirror.sv +94 -0
- data/lib/axi/axi4_to_xilinx_ddr_native/axi4_to_native_for_ddr_ip_C2.sv +75 -0
- data/lib/axi/axi4_to_xilinx_ddr_native/ddr_native_fifo_A2.sv +206 -0
- data/lib/axi/axi4_to_xilinx_ddr_native/ddr_native_fifo_B1.sv +297 -0
- data/lib/axi/axi4_to_xilinx_ddr_native/model_ddr_ip_app.sv +2 -2
- data/lib/axi/common/common_ram_wrapper.sv +1 -1
- data/lib/axi/data_interface/data_inf_c/data_c_pipe_sync_seam.sv +11 -11
- data/lib/axi/data_interface/data_inf_c/data_c_scaler.sv +2 -1
- data/lib/axi/data_interface/data_inf_c/data_c_scaler_A1.sv +2 -1
- data/lib/axi/data_interface/data_streams_combin.sv +2 -1
- data/lib/axi/data_interface/data_streams_combin_A1.sv +2 -1
- data/lib/axi/data_interface/data_streams_scaler.sv +2 -1
- data/lib/axi_tdl/version.rb +1 -1
- data/lib/tdl/axi4/axi4_interconnect_verb.rb +5 -1
- data/lib/tdl/examples/2_hdl_class/tmp/test_vcs_string.sv +1 -1
- data/lib/tdl/examples/8_top_module/test_top.sv +1 -1
- data/lib/tdl/rebuild_ele/ele_base.rb +14 -0
- metadata +13 -3
checksums.yaml
CHANGED
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@@ -1,7 +1,7 @@
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---
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SHA256:
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-
metadata.gz:
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data.tar.gz:
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metadata.gz: 8dd62863539fff2708246a09927e479738b03d047133e734cc55f4e1829d6b54
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data.tar.gz: ceb59ee036e1cefc3a21556a332e66b65f0c0dc57fab062614557546ca718b3f
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SHA512:
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metadata.gz:
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data.tar.gz:
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metadata.gz: ecd12a65dc60bb8fb9eb2566df28cef78903c4660dd14606c08f9cd7192b5b4a0f51d7c2aa9c7ff95db88087b5f0123a0c5de66152ddd512f845e5f78d114377
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data.tar.gz: 889d28213cbdc3bfc5179bb347902828af30008573030725e309bd227ee013e34906b2b967de83bb52480a04091c328a1ed42ae9d805bcf4e6d3f96816f19bd5
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# This workflow uses actions that are not certified by GitHub.
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# They are provided by a third-party and are governed by
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# separate terms of service, privacy policy, and support
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# documentation.
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# GitHub recommends pinning actions to a commit SHA.
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# To get a newer version, you will need to update the SHA.
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# You can also reference a tag or branch, but the action may change without warning.
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name: Ruby Gem
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on:
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# Manually publish
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workflow_dispatch:
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# Alternatively, publish whenever changes are merged to the `main` branch.
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push:
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branches: [ main ]
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pull_request:
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@@ -10,35 +22,41 @@ jobs:
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build:
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name: Build + Publish
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runs-on: ubuntu-latest
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permissions:
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packages: write
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contents: read
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- uses: actions/checkout@v3
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- name: Set up Ruby 2.6
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uses: ruby/setup-ruby@477b21f02be01bcb8030d50f37cfec92bfa615b6
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with:
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ruby-version: 2.6
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- run: bundle install
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- name: Publish to GPR
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run: |
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mkdir -p $HOME/.gem
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touch $HOME/.gem/credentials
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chmod 0600 $HOME/.gem/credentials
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printf -- "---\n:github: ${GEM_HOST_API_KEY}\n" > $HOME/.gem/credentials
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gem build *.gemspec
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gem push --KEY github --host https://rubygems.pkg.github.com/${OWNER} *.gem
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env:
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GEM_HOST_API_KEY: "Bearer ${{secrets.GITHUB_TOKEN}}"
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OWNER: ${{ github.repository_owner }}
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- name: Publish to RubyGems
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run: |
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mkdir -p $HOME/.gem
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touch $HOME/.gem/credentials
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chmod 0600 $HOME/.gem/credentials
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printf -- "---\n:rubygems_api_key: ${RUBYGEMS_API_KEY}\n" > $HOME/.gem/credentials
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gem build *.gemspec
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gem push *.gem
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env:
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GEM_HOST_API_KEY: "${{secrets.RUBYGEMS_AUTH_TOKEN}}"
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GITHUB_TOKEN: ${{secrets.GITHUB_TOKEN}}
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RUBYGEMS_API_KEY: ${{secrets.RUBYGEMS_API_KEY}}
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data/.github/workflows/ruby.yml
CHANGED
data/.gitignore
CHANGED
data/.travis.yml
CHANGED
data/axi_tdl.gemspec
CHANGED
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@@ -15,7 +15,7 @@ Gem::Specification.new do |spec|
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spec.license = "LGPL-2.1"
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spec.files = Dir['lib/**/*']
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spec.require_paths = ["lib"]
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spec.required_ruby_version = '>= 2.
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spec.required_ruby_version = '>= 2.6.0'
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# Prevent pushing this gem to RubyGems.org. To allow pushes either set the 'allowed_push_host'
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# to allow pushing to a single host or delete this section to allow pushing to any host.
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if spec.respond_to?(:metadata)
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@@ -109,8 +109,8 @@ axi4_partition_OD #(
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// .ADDR_STEP (slaver_inf.DSIZE/(master_inf.DSIZE/8.0) )
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// .ADDR_STEP (4*slaver_inf.DSIZE/16.0 )
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)axi4_partition_inst(
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/* axi_inf.slaver_inf */ .
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/* axi_inf.master_inf */ .
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/* axi_inf.slaver_inf */ .slaver (axi_inf_first_wc ),
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/* axi_inf.master_inf */ .master (axi_inf_pout )
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);
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axi4_data_convert_verb #(
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endgenerate
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axi4_packet_fifo_verb #( //512
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// axi4_packet_fifo_verb #( //512
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axi4_packet_fifo_B1 #( //
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.PIPE (PIPE ),
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.DEPTH (4 ),
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.MAX_DATA_LEN (1024*2),
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.SLAVER_MODE (SLAVER_MODE ), //
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.MASTER_MODE (MASTER_MODE ) //
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)axi4_packet_fifo_inst(
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require_hdl "axis_length_split_with_addr.sv"
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require_hdl 'axi_stream_long_fifo_verb.sv'
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require_shdl 'axi4_wr_auxiliary_gen_without_resp','axis_valve_with_pipe'
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require_shdl 'independent_clock_fifo'
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TdlBuild.long_axis_to_axi4_wr(__dir__) do
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parameter.BYTE_DEPTH 8192*2
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@@ -0,0 +1,173 @@
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/**********************************************
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_______________________________________
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___________ Cook Darwin __________
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_______________________________________
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descript:
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author : Cook.Darwin
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Version: VERA.1.0 2017/9/18
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use axis out
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Version: VERA.2.0 ###### Tue Jan 7 09:47:51 CST 2020
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data_inf_c replace valid ready
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Version: VERA.4.0
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Vision AXI PARAMETER
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creaded: 2017/3/1
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madified:
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***********************************************/
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`timescale 1ns/1ps
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(* axi4 = "true" *)
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module odata_pool_axi4_A4 #(
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parameter IDSIZE = 2,
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parameter ASIZE = 32,
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parameter LSIZE = 16
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)(
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axi_stream_inf.master out_axis,
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data_inf_c.slaver addr_size_inf, //ADDR: 32 SIZE: 32
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axi_inf.master_rd axi_master
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);
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`include "define_macro.sv"
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logic fifo_empty;
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logic fifo_full;
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logic [31:0] fifo_addr;
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logic [31:0] fifo_size;
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logic fifo_rd_en;
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independent_clock_fifo #(
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.DEPTH (4 ),
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.DSIZE (64 )
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)independent_clock_fifo_inst_req(
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/* input */ .wr_clk (addr_size_inf.clock ),
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/* input */ .wr_rst_n (addr_size_inf.rst_n ),
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/* input */ .rd_clk (axi_master.axi_aclk ),
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/* input */ .rd_rst_n (axi_master.axi_aresetn ),
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/* input [DSIZE-1:0] */ .wdata (addr_size_inf.data ),
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/* input */ .wr_en (addr_size_inf.valid && addr_size_inf.ready ),
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/* output logic[DSIZE-1:0] */ .rdata ({fifo_addr,fifo_size} ),
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/* input */ .rd_en ((fifo_rd_en && !fifo_empty) ),
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/* output logic */ .empty (fifo_empty ),
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/* output logic */ .full (fifo_full )
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);
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assign addr_size_inf.ready = !fifo_full;
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initial begin
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if(out_axis.DSIZE != axi_master.DSIZE)begin
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$error("DATA POOL AXI4 DATA WIDTH ERROR DSIZE[%d]--axi_master.DSIZE[%d]",out_axis.DSIZE,axi_master.DSIZE);
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$finish;
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end
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assert (axi_master.IDSIZE==IDSIZE)
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else $error("axi_master.IDSIZE==IDSIZE");
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+
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assert (axi_master.ASIZE==ASIZE)
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else $error("axi_master.ASIZE==ASIZE");
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assert (axi_master.LSIZE==LSIZE)
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else $error("axi_master.LSIZE==LSIZE");
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end
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axi_stream_inf #(.DSIZE(IDSIZE+ASIZE+LSIZE)) addr_len_inf (.aclk(axi_master.axi_aclk),.aresetn(axi_master.axi_aresetn),.aclken(1'b1));
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+
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logic [IDSIZE-1:0] id;
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logic [ASIZE-1:0] addr;
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logic [LSIZE-1:0] length;
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logic force_align_status;
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assign id = '0;
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assign addr = fifo_addr[ASIZE-1:0];
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assign length = fifo_size[LSIZE:0];
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+
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assign addr_len_inf.axis_tdata = {id,addr,length};
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`VCS_AXI4_CPT_LT(axi_master,master_rd,master_rd_aux,)
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axi4_rd_auxiliary_gen_A1 axi4_rd_auxiliary_gen_inst(
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/* axi_stream_inf.slaver */ .id_add_len_in (addr_len_inf ), //tlast is not necessary
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/* axi_inf.master_rd_aux */ .axi_rd_aux (`axi_master_vcs_cpt )
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);
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+
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assign addr_len_inf.axis_tvalid = !fifo_empty && (fifo_size[LSIZE:0]!='0);
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assign fifo_rd_en = addr_len_inf.axis_tready;
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+
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//--->> FIFO
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+
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logic axis_fifo_empty;
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logic axis_fifo_full;
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logic axis_fifo_rd_en;
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logic [out_axis.DSIZE+1-1:0] axis_fifo_rd_data;
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+
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//--->> forece rd_en <<---------------------------
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+
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logic force_rd_en;
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logic cmded_empty;
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independent_clock_fifo #(
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.DEPTH (4 ),
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.DSIZE (1 )
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)independent_clock_fifo_inst(
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/* input */ .wr_clk (axi_master.axi_aclk ),
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/* input */ .wr_rst_n (axi_master.axi_aresetn ),
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110
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/* input */ .rd_clk (out_axis.aclk ),
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111
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/* input */ .rd_rst_n (out_axis.aresetn ),
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/* input [DSIZE-1:0] */ .wdata (1'b1),
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/* input */ .wr_en (axi_master.axi_arready && axi_master.axi_arvalid),
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/* output logic[DSIZE-1:0] */ .rdata (),
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/* input */ .rd_en (out_axis.axis_tvalid && out_axis.axis_tready && out_axis.axis_tlast),
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/* output logic */ .empty (cmded_empty ),
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/* output logic */ .full ()
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);
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120
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+
assign force_rd_en = cmded_empty && !axis_fifo_empty;
|
|
121
|
+
//---<< forece rd_en >>---------------------------
|
|
122
|
+
|
|
123
|
+
xilinx_fifo_verb #(
|
|
124
|
+
//xilinx_fifo #(
|
|
125
|
+
.DSIZE (out_axis.DSIZE+1 )
|
|
126
|
+
)xilinx_fifo_inst(
|
|
127
|
+
/* input */ .wr_clk (axi_master.axi_aclk ),
|
|
128
|
+
/* input */ .wr_rst (!axi_master.axi_aresetn),
|
|
129
|
+
/* input */ .rd_clk (out_axis.aclk ),
|
|
130
|
+
/* input */ .rd_rst (!out_axis.aresetn ),
|
|
131
|
+
/* input [DSIZE-1:0] */ .din ({axi_master.axi_rlast,axi_master.axi_rdata} ),
|
|
132
|
+
/* input */ .wr_en ((axi_master.axi_rvalid && axi_master.axi_rready) ),
|
|
133
|
+
/* input */ .rd_en (axis_fifo_rd_en || force_rd_en ),
|
|
134
|
+
/* output [DSIZE-1:0] */ .dout (axis_fifo_rd_data ),
|
|
135
|
+
/* output */ .full (axis_fifo_full ),
|
|
136
|
+
/* output */ .empty (axis_fifo_empty ),
|
|
137
|
+
/* output [LSIZE-1:0] */ .rdcount (),
|
|
138
|
+
/* output [LSIZE-1:0] */ .wrcount ()
|
|
139
|
+
);
|
|
140
|
+
|
|
141
|
+
|
|
142
|
+
assign axi_master.axi_rready = !axis_fifo_full;
|
|
143
|
+
|
|
144
|
+
assign out_axis.axis_tdata = axis_fifo_rd_data[out_axis.DSIZE-1:0];
|
|
145
|
+
assign out_axis.axis_tlast = axis_fifo_rd_data[out_axis.DSIZE];
|
|
146
|
+
assign out_axis.axis_tvalid = !axis_fifo_empty;
|
|
147
|
+
assign out_axis.axis_tkeep = '1;
|
|
148
|
+
assign axis_fifo_rd_en = out_axis.axis_tvalid && out_axis.axis_tready;
|
|
149
|
+
|
|
150
|
+
|
|
151
|
+
//--->> force_align_status <<---------------------
|
|
152
|
+
|
|
153
|
+
// (* dont_touch = "true" *)
|
|
154
|
+
logic [23:0] axi4_rd_cnt;
|
|
155
|
+
|
|
156
|
+
always@(posedge axi_master.axi_aclk)
|
|
157
|
+
if(axi_master.axi_rvalid && axi_master.axi_rready && axi_master.axi_rlast)
|
|
158
|
+
axi4_rd_cnt <= '0;
|
|
159
|
+
else if(axi_master.axi_rvalid && axi_master.axi_rready)
|
|
160
|
+
axi4_rd_cnt <= axi4_rd_cnt + 1'b1;
|
|
161
|
+
else axi4_rd_cnt <= axi4_rd_cnt;
|
|
162
|
+
|
|
163
|
+
always@(posedge axi_master.axi_aclk ,negedge axi_master.axi_aresetn)
|
|
164
|
+
if(!axi_master.axi_aresetn)
|
|
165
|
+
force_align_status <= 1'b0;
|
|
166
|
+
else if(axi_master.axi_rvalid && axi_master.axi_rready && axi_master.axi_rlast)
|
|
167
|
+
force_align_status <= axi_master.axi_rcnt != axi4_rd_cnt;
|
|
168
|
+
else if(axis_fifo_empty && cmded_empty)
|
|
169
|
+
force_align_status <= 1'b0;
|
|
170
|
+
else force_align_status <= force_align_status;
|
|
171
|
+
|
|
172
|
+
//---<< force_align_status >>---------------------
|
|
173
|
+
endmodule
|
|
@@ -0,0 +1,66 @@
|
|
|
1
|
+
/**********************************************
|
|
2
|
+
_______________________________________
|
|
3
|
+
___________ Cook Darwin __________
|
|
4
|
+
_______________________________________
|
|
5
|
+
descript:
|
|
6
|
+
author : Cook.Darwin
|
|
7
|
+
Version: VERB.1.0
|
|
8
|
+
longer fifo
|
|
9
|
+
creaded: 2017/2/28
|
|
10
|
+
madified:
|
|
11
|
+
***********************************************/
|
|
12
|
+
`timescale 1ns/1ps
|
|
13
|
+
`include "define_macro.sv"
|
|
14
|
+
module axi4_packet_fifo_B1 #(
|
|
15
|
+
parameter PIPE = "OFF",
|
|
16
|
+
parameter DEPTH = 4,
|
|
17
|
+
parameter MAX_DATA_LEN = 1024*16,
|
|
18
|
+
`parameter_string MODE = "BOTH", //ONLY_WRITE ONLY_READ BOTH
|
|
19
|
+
`parameter_string SLAVER_MODE = "BOTH", //
|
|
20
|
+
`parameter_string MASTER_MODE = "BOTH" //
|
|
21
|
+
)(
|
|
22
|
+
axi_inf.slaver axi_in,
|
|
23
|
+
axi_inf.master axi_out
|
|
24
|
+
);
|
|
25
|
+
|
|
26
|
+
import SystemPkg::*;
|
|
27
|
+
|
|
28
|
+
initial begin
|
|
29
|
+
assert(SLAVER_MODE == MASTER_MODE)
|
|
30
|
+
else begin
|
|
31
|
+
$error("SLAVER AXIS MODE != MASTER AXIS MODE");
|
|
32
|
+
$stop;
|
|
33
|
+
end
|
|
34
|
+
end
|
|
35
|
+
|
|
36
|
+
|
|
37
|
+
`VCS_AXI4_CPT(axi_in,slaver,slaver_rd,Read)
|
|
38
|
+
`VCS_AXI4_CPT(axi_in,slaver,slaver_wr,Write)
|
|
39
|
+
`VCS_AXI4_CPT_LT(axi_out,master_rd,master,Read)
|
|
40
|
+
`VCS_AXI4_CPT_LT(axi_out,master_wr,master,Write)
|
|
41
|
+
|
|
42
|
+
|
|
43
|
+
generate
|
|
44
|
+
if(SLAVER_MODE=="BOTH" || SLAVER_MODE=="ONLY_WRITE")
|
|
45
|
+
axi4_wr_packet_fifo_A1 #(
|
|
46
|
+
.PIPE (PIPE ),
|
|
47
|
+
.DEPTH (DEPTH ),
|
|
48
|
+
.MAX_DATA_LEN (MAX_DATA_LEN )
|
|
49
|
+
)axi4_wr_packet_fifo_inst(
|
|
50
|
+
/* axi_inf.slaver_wr */ .axi_in (`axi_in_vcs_cptWrite ),
|
|
51
|
+
/* axi_inf.master_wr */ .axi_out (`axi_out_vcs_cptWrite )
|
|
52
|
+
);
|
|
53
|
+
endgenerate
|
|
54
|
+
|
|
55
|
+
generate
|
|
56
|
+
if(SLAVER_MODE=="BOTH" || SLAVER_MODE=="ONLY_READ")
|
|
57
|
+
axi4_rd_packet_fifo_A1 #(
|
|
58
|
+
.DEPTH (DEPTH ),
|
|
59
|
+
.MAX_DATA_LEN (MAX_DATA_LEN )
|
|
60
|
+
)axi4_rd_packet_fifo_inst(
|
|
61
|
+
/* axi_inf.slaver_rd */ .slaver (`axi_in_vcs_cptRead ),
|
|
62
|
+
/* axi_inf.master_rd */ .master (`axi_out_vcs_cptRead )
|
|
63
|
+
);
|
|
64
|
+
endgenerate
|
|
65
|
+
|
|
66
|
+
endmodule
|
|
@@ -0,0 +1,260 @@
|
|
|
1
|
+
/**********************************************
|
|
2
|
+
_______________________________________
|
|
3
|
+
___________ Cook Darwin __________
|
|
4
|
+
_______________________________________
|
|
5
|
+
descript:
|
|
6
|
+
author : Cook.Darwin
|
|
7
|
+
Version: VERA.1.0
|
|
8
|
+
longer fifo
|
|
9
|
+
creaded: 2017/2/28
|
|
10
|
+
madified:
|
|
11
|
+
***********************************************/
|
|
12
|
+
`timescale 1ns/1ps
|
|
13
|
+
module axi4_rd_packet_fifo_A1 #(
|
|
14
|
+
parameter PIPE = "OFF",
|
|
15
|
+
parameter DEPTH = 4,
|
|
16
|
+
parameter MAX_DATA_LEN = 1024*16
|
|
17
|
+
)(
|
|
18
|
+
axi_inf.slaver_rd slaver,
|
|
19
|
+
axi_inf.master_rd master
|
|
20
|
+
);
|
|
21
|
+
|
|
22
|
+
logic stream_fifo_full;
|
|
23
|
+
//--->> AUXILIARY <<------------------
|
|
24
|
+
logic auxiliary_fifo_empty;
|
|
25
|
+
logic auxiliary_fifo_full;
|
|
26
|
+
logic auxiliary_fifo_rd_en;
|
|
27
|
+
logic auxiliary_fifo_wr_en;
|
|
28
|
+
|
|
29
|
+
independent_clock_fifo #( //fifo can stack DEPTH+1 "DATA"
|
|
30
|
+
.DEPTH (DEPTH-1 ),
|
|
31
|
+
.DSIZE (slaver.ASIZE+slaver.LSIZE+slaver.IDSIZE)
|
|
32
|
+
)auxiliary_independent_clock_fifo_inst(
|
|
33
|
+
/* input */ .wr_clk (slaver.axi_aclk ),
|
|
34
|
+
/* input */ .wr_rst_n (slaver.axi_aresetn ),
|
|
35
|
+
/* input */ .rd_clk (master.axi_aclk ),
|
|
36
|
+
/* input */ .rd_rst_n (master.axi_aresetn ),
|
|
37
|
+
/* input [DSIZE-1:0] */ .wdata ({slaver.axi_araddr,slaver.axi_arlen,slaver.axi_arid}),
|
|
38
|
+
/* input */ .wr_en (auxiliary_fifo_wr_en ),
|
|
39
|
+
/* output logic[DSIZE-1:0] */ .rdata ({master.axi_araddr,master.axi_arlen,master.axi_arid}),
|
|
40
|
+
/* input */ .rd_en (auxiliary_fifo_rd_en ),
|
|
41
|
+
/* output logic */ .empty (auxiliary_fifo_empty ),
|
|
42
|
+
/* output logic */ .full (auxiliary_fifo_full )
|
|
43
|
+
);
|
|
44
|
+
|
|
45
|
+
//--->> SLAVER SIDE <<-------------------------------------
|
|
46
|
+
logic sctrl_fifo_empty;
|
|
47
|
+
logic sctrl_fifo_full;
|
|
48
|
+
logic sctrl_fifo_rd_en;
|
|
49
|
+
logic sctrl_fifo_wr_en;
|
|
50
|
+
|
|
51
|
+
(* dont_touch="true" *)
|
|
52
|
+
logic [slaver.IDSIZE-1:0] sctrl_fifo_id;
|
|
53
|
+
|
|
54
|
+
independent_clock_fifo #(
|
|
55
|
+
.DEPTH (DEPTH-1 ),
|
|
56
|
+
.DSIZE (slaver.IDSIZE)
|
|
57
|
+
)slaver_last_independent_clock_fifo_inst(
|
|
58
|
+
/* input */ .wr_clk (slaver.axi_aclk ),
|
|
59
|
+
/* input */ .wr_rst_n (slaver.axi_aresetn && master.axi_aresetn ),
|
|
60
|
+
/* input */ .rd_clk (slaver.axi_aclk ),
|
|
61
|
+
/* input */ .rd_rst_n (slaver.axi_aresetn && master.axi_aresetn ),
|
|
62
|
+
/* input [DSIZE-1:0] */ .wdata (slaver.axi_arid ),
|
|
63
|
+
/* input */ .wr_en (sctrl_fifo_wr_en ),
|
|
64
|
+
/* output logic[DSIZE-1:0] */ .rdata (sctrl_fifo_id ),
|
|
65
|
+
/* input */ .rd_en (sctrl_fifo_rd_en ),
|
|
66
|
+
/* output logic */ .empty (sctrl_fifo_empty ),
|
|
67
|
+
/* output logic */ .full (sctrl_fifo_full )
|
|
68
|
+
);
|
|
69
|
+
|
|
70
|
+
assign sctrl_fifo_wr_en = slaver.axi_arvalid && slaver.axi_arready;
|
|
71
|
+
assign sctrl_fifo_rd_en = (slaver.axi_rvalid && slaver.axi_rready && slaver.axi_rlast);
|
|
72
|
+
//---<< SLAVER SIDE >>-------------------------------------
|
|
73
|
+
//--->> MASTER SIDE <<---------------------------------
|
|
74
|
+
logic mctrl_fifo_empty;
|
|
75
|
+
logic mctrl_fifo_full;
|
|
76
|
+
logic mctrl_fifo_rd_en;
|
|
77
|
+
logic mctrl_fifo_wr_en;
|
|
78
|
+
|
|
79
|
+
(* dont_touch="true" *)
|
|
80
|
+
logic [master.IDSIZE-1:0] mctrl_fifo_id;
|
|
81
|
+
|
|
82
|
+
independent_clock_fifo #(
|
|
83
|
+
.DEPTH (DEPTH-1 ),
|
|
84
|
+
.DSIZE (master.IDSIZE)
|
|
85
|
+
// .DSIZE (1)
|
|
86
|
+
)master_last_independent_clock_fifo_inst(
|
|
87
|
+
/* input */ .wr_clk (master.axi_aclk ),
|
|
88
|
+
/* input */ .wr_rst_n (master.axi_aresetn && slaver.axi_aresetn ),
|
|
89
|
+
/* input */ .rd_clk (master.axi_aclk ),
|
|
90
|
+
/* input */ .rd_rst_n (master.axi_aresetn && slaver.axi_aresetn ),
|
|
91
|
+
/* input [DSIZE-1:0] */ .wdata (master.axi_arid ),
|
|
92
|
+
/* input */ .wr_en (mctrl_fifo_wr_en ),
|
|
93
|
+
/* output logic[DSIZE-1:0] */ .rdata (mctrl_fifo_id ),
|
|
94
|
+
/* input */ .rd_en (mctrl_fifo_rd_en ),
|
|
95
|
+
/* output logic */ .empty (mctrl_fifo_empty ),
|
|
96
|
+
/* output logic */ .full (mctrl_fifo_full )
|
|
97
|
+
);
|
|
98
|
+
|
|
99
|
+
assign mctrl_fifo_wr_en = master.axi_arvalid && master.axi_arready;
|
|
100
|
+
assign mctrl_fifo_rd_en = (master.axi_rvalid && master.axi_rready && master.axi_rlast);
|
|
101
|
+
|
|
102
|
+
//---<< MASTER SIDE >>---------------------------------
|
|
103
|
+
//--->> VLD RDY PAIR slaver
|
|
104
|
+
assign slaver.axi_arready = !sctrl_fifo_full;
|
|
105
|
+
assign auxiliary_fifo_wr_en = slaver.axi_arvalid && !sctrl_fifo_full;
|
|
106
|
+
//=====================
|
|
107
|
+
//--->> VLD RDY PAIR master
|
|
108
|
+
assign auxiliary_fifo_rd_en = master.axi_arready && !mctrl_fifo_full;
|
|
109
|
+
assign master.axi_arvalid = !auxiliary_fifo_empty && !mctrl_fifo_full;
|
|
110
|
+
//=====================
|
|
111
|
+
//---<< AUXILIARY >>------------------
|
|
112
|
+
//--->> DEPTH CTRL <<-----------------
|
|
113
|
+
//---<< DEPTH CTRL >>-----------------
|
|
114
|
+
//--->> DATA <<-----------------------
|
|
115
|
+
axi_stream_inf #(
|
|
116
|
+
.DSIZE(slaver.DSIZE)
|
|
117
|
+
)axis_out(
|
|
118
|
+
.aclk (slaver.axi_aclk ),
|
|
119
|
+
.aresetn (slaver.axi_aresetn ),
|
|
120
|
+
.aclken (1'b1 )
|
|
121
|
+
);
|
|
122
|
+
|
|
123
|
+
axi_stream_inf #(
|
|
124
|
+
.DSIZE(slaver.DSIZE)
|
|
125
|
+
)post_axis_in(
|
|
126
|
+
.aclk (master.axi_aclk ),
|
|
127
|
+
.aresetn (master.axi_aresetn ),
|
|
128
|
+
.aclken (1'b1 )
|
|
129
|
+
);
|
|
130
|
+
|
|
131
|
+
axi_stream_inf #(
|
|
132
|
+
.DSIZE(master.DSIZE)
|
|
133
|
+
)axis_in(
|
|
134
|
+
.aclk (master.axi_aclk ),
|
|
135
|
+
.aresetn (master.axi_aresetn ),
|
|
136
|
+
.aclken (1'b1 )
|
|
137
|
+
);
|
|
138
|
+
|
|
139
|
+
|
|
140
|
+
|
|
141
|
+
`ifdef VCS_ENV
|
|
142
|
+
localparam CSIZE = $bits(slaver.axi_rid);
|
|
143
|
+
`else
|
|
144
|
+
localparam CSIZE = slaver.IDSIZE;
|
|
145
|
+
`endif
|
|
146
|
+
|
|
147
|
+
axi_stream_packet_fifo_B1F #(
|
|
148
|
+
.DEPTH (DEPTH), //2-4
|
|
149
|
+
.CSIZE (CSIZE ),
|
|
150
|
+
.DSIZE (slaver.DSIZE ),
|
|
151
|
+
.MAX_DATA_LEN(MAX_DATA_LEN)
|
|
152
|
+
)axi_stream_packet_fifo_inst(
|
|
153
|
+
/* input [CSIZE-1:0] */ .in_cdata (master.axi_rid ),
|
|
154
|
+
/* output[CSIZE-1:0] */ .out_cdata (slaver.axi_rid ),
|
|
155
|
+
/* axi_stream_inf.slaver */.slaver_inf (post_axis_in ),
|
|
156
|
+
/* axi_stream_inf.slaver */.master_inf (axis_out )
|
|
157
|
+
);
|
|
158
|
+
|
|
159
|
+
generate
|
|
160
|
+
if(PIPE == "ON")
|
|
161
|
+
axis_connect_pipe in_axis_connect_pipe_inst(
|
|
162
|
+
/* axi_stream_inf.slaver */ .axis_in (axis_in ),
|
|
163
|
+
/* axi_stream_inf.master */ .axis_out (post_axis_in )
|
|
164
|
+
);
|
|
165
|
+
else
|
|
166
|
+
axis_direct axis_direct_inst(
|
|
167
|
+
/* axi_stream_inf.slaver */ .slaver (axis_in ),
|
|
168
|
+
/* axi_stream_inf.master */ .master (post_axis_in )
|
|
169
|
+
);
|
|
170
|
+
endgenerate
|
|
171
|
+
|
|
172
|
+
//--->> AXIS FIFO SPACE CHK <<--------------
|
|
173
|
+
//---<< AXIS FIFO SPACE CHK >>--------------
|
|
174
|
+
|
|
175
|
+
assign axis_in.axis_tvalid = master.axi_rvalid;
|
|
176
|
+
assign axis_in.axis_tdata = master.axi_rdata;
|
|
177
|
+
assign axis_in.axis_tlast = master.axi_rlast;
|
|
178
|
+
assign axis_in.axis_tkeep = '1;
|
|
179
|
+
assign axis_in.axis_tuser = '0;
|
|
180
|
+
assign master.axi_rready = axis_in.axis_tready;
|
|
181
|
+
|
|
182
|
+
assign slaver.axi_rvalid = axis_out.axis_tvalid;
|
|
183
|
+
assign slaver.axi_rdata = axis_out.axis_tdata;
|
|
184
|
+
assign slaver.axi_rlast = axis_out.axis_tlast;
|
|
185
|
+
assign axis_out.axis_tready= slaver.axi_rready;
|
|
186
|
+
|
|
187
|
+
assign stream_fifo_full = !axis_in.axis_tready;
|
|
188
|
+
//---<< DATA >>-----------------------
|
|
189
|
+
//--->> ID TRACK <<-------------------
|
|
190
|
+
// (* dont_touch="true" *)
|
|
191
|
+
// logic id_err;
|
|
192
|
+
// (* dont_touch="true" *)
|
|
193
|
+
// logic [slaver.IDSIZE-1:0] slaver_post_id;
|
|
194
|
+
// always@(posedge slaver.axi_aclk,negedge slaver.axi_aresetn)begin:ID_ERR_BLOCK
|
|
195
|
+
// if(~slaver.axi_aresetn) begin
|
|
196
|
+
// id_err <= 1'b0;
|
|
197
|
+
// slaver_post_id <= '0;
|
|
198
|
+
// end else begin
|
|
199
|
+
// slaver_post_id <= (slaver.axi_rvalid && slaver.axi_rready)? slaver.axi_rid : slaver_post_id;
|
|
200
|
+
// if(slaver.axi_rvalid && slaver.axi_rready)begin
|
|
201
|
+
// if(slaver_post_id=='1)begin
|
|
202
|
+
// if(slaver.axi_rid != '0 && (slaver_post_id != slaver.axi_rid))
|
|
203
|
+
// id_err <= 1'b1;
|
|
204
|
+
// else id_err <= id_err;
|
|
205
|
+
// end else begin
|
|
206
|
+
// id_err <= (slaver_post_id+1 != slaver.axi_rid) && (slaver_post_id != slaver.axi_rid);
|
|
207
|
+
// end
|
|
208
|
+
// end else slaver_post_id <= slaver_post_id;
|
|
209
|
+
// end
|
|
210
|
+
// end
|
|
211
|
+
//
|
|
212
|
+
// initial begin
|
|
213
|
+
// wait(id_err);
|
|
214
|
+
// #(100us);
|
|
215
|
+
// $stop;
|
|
216
|
+
// end
|
|
217
|
+
//
|
|
218
|
+
// (* dont_touch="true" *)
|
|
219
|
+
// logic master_id_err;
|
|
220
|
+
// (* dont_touch="true" *)
|
|
221
|
+
// logic [slaver.IDSIZE-1:0] master_post_id;
|
|
222
|
+
// always@(posedge master.axi_aclk,negedge master.axi_aresetn)begin:MASTER_ID_ERR_BLOCK
|
|
223
|
+
// if(~master.axi_aresetn) begin
|
|
224
|
+
// master_id_err <= 1'b0;
|
|
225
|
+
// master_id_err <= '0;
|
|
226
|
+
// end else begin
|
|
227
|
+
// master_post_id <= (master.axi_rvalid && master.axi_rready)? master.axi_rid : master_post_id;
|
|
228
|
+
// if(master.axi_rvalid && master.axi_rready)begin
|
|
229
|
+
// if(master_post_id=='1)begin
|
|
230
|
+
// if(master.axi_rid != '0 && (master_post_id != master.axi_rid))
|
|
231
|
+
// master_id_err <= 1'b1;
|
|
232
|
+
// else master_id_err <= master_id_err;
|
|
233
|
+
// end else begin
|
|
234
|
+
// master_id_err <= (master_post_id+1 != master.axi_rid) && (master_post_id != master.axi_rid);
|
|
235
|
+
// end
|
|
236
|
+
// end else master_id_err <= master_id_err;
|
|
237
|
+
// end
|
|
238
|
+
// end
|
|
239
|
+
//
|
|
240
|
+
// initial begin
|
|
241
|
+
// wait(master_id_err);
|
|
242
|
+
// #(100us);
|
|
243
|
+
// $stop;
|
|
244
|
+
// end
|
|
245
|
+
//---<< ID TRACK >>-------------------
|
|
246
|
+
`include "define_macro.sv"
|
|
247
|
+
`VCS_AXI4_CPT(master,master,mirror_rd,)
|
|
248
|
+
import SystemPkg::*;
|
|
249
|
+
generate
|
|
250
|
+
if(SIM=="ON" || SIM=="TRUE")begin
|
|
251
|
+
axi4_rd_burst_track #(
|
|
252
|
+
.MAX_LEN (16 ),
|
|
253
|
+
.MAX_CYCLE (1000 )
|
|
254
|
+
)axi4_rd_burst_track_inst(
|
|
255
|
+
/* axi_inf.mirror_rd */ .axi4_mirror (`master_vcs_cpt )
|
|
256
|
+
);
|
|
257
|
+
end
|
|
258
|
+
endgenerate
|
|
259
|
+
|
|
260
|
+
endmodule
|