axi_tdl 0.2.0 → 0.2.4
This diff represents the content of publicly available package versions that have been released to one of the supported registries. The information contained in this diff is provided for informational purposes only and reflects changes between package versions as they appear in their respective public registries.
- checksums.yaml +4 -4
- data/.github/workflows/gem-push.yml +46 -28
- data/.github/workflows/ruby.yml +1 -1
- data/.gitignore +2 -1
- data/.travis.yml +1 -0
- data/axi_tdl.gemspec +1 -1
- data/lib/axi/AXI4/axi4_long_to_axi4_wide_B1.sv +5 -3
- data/lib/axi/AXI4/long_axis_to_axi4_wr.rb +1 -0
- data/lib/axi/AXI4/odata_pool_axi4_A4.sv +173 -0
- data/lib/axi/AXI4/packet_fifo/axi4_packet_fifo_B1.sv +66 -0
- data/lib/axi/AXI4/packet_fifo/axi4_rd_packet_fifo_A1.sv +260 -0
- data/lib/axi/AXI4/packet_fifo/axi4_wr_packet_fifo_A1.sv +192 -0
- data/lib/axi/AXI4/wide_axis_to_axi4_wr.sv +1 -1
- data/lib/axi/AXI_stream/axi_stream_split_channel.sv +21 -21
- data/lib/axi/AXI_stream/axi_streams_combin.sv +2 -1
- data/lib/axi/AXI_stream/axi_streams_combin_A1.sv +2 -1
- data/lib/axi/AXI_stream/axi_streams_scaler.sv +2 -1
- data/lib/axi/AXI_stream/axi_streams_scaler_A1.sv +2 -1
- data/lib/axi/AXI_stream/axis_combin_with_fifo.sv +2 -1
- data/lib/axi/AXI_stream/axis_head_cut_verc.rb +2 -0
- data/lib/axi/AXI_stream/gen_big_field_table.sv +3 -2
- data/lib/axi/AXI_stream/packet_fifo/axi_stream_packet_fifo_B1F.sv +129 -0
- data/lib/axi/AXI_stream/parse_big_field_table_main.sv +101 -0
- data/lib/axi/AXI_stream/parse_big_field_table_mirror.sv +94 -0
- data/lib/axi/axi4_to_xilinx_ddr_native/axi4_to_native_for_ddr_ip_C2.sv +75 -0
- data/lib/axi/axi4_to_xilinx_ddr_native/ddr_native_fifo_A2.sv +206 -0
- data/lib/axi/axi4_to_xilinx_ddr_native/ddr_native_fifo_B1.sv +297 -0
- data/lib/axi/axi4_to_xilinx_ddr_native/model_ddr_ip_app.sv +2 -2
- data/lib/axi/common/common_ram_wrapper.sv +1 -1
- data/lib/axi/data_interface/data_inf_c/data_c_pipe_sync_seam.sv +11 -11
- data/lib/axi/data_interface/data_inf_c/data_c_scaler.sv +2 -1
- data/lib/axi/data_interface/data_inf_c/data_c_scaler_A1.sv +2 -1
- data/lib/axi/data_interface/data_streams_combin.sv +2 -1
- data/lib/axi/data_interface/data_streams_combin_A1.sv +2 -1
- data/lib/axi/data_interface/data_streams_scaler.sv +2 -1
- data/lib/axi_tdl/version.rb +1 -1
- data/lib/tdl/axi4/axi4_interconnect_verb.rb +5 -1
- data/lib/tdl/examples/2_hdl_class/tmp/test_vcs_string.sv +1 -1
- data/lib/tdl/examples/8_top_module/test_top.sv +1 -1
- data/lib/tdl/rebuild_ele/ele_base.rb +14 -0
- metadata +13 -3
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/**********************************************
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_______________________________________
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___________ Cook Darwin __________
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_______________________________________
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descript:
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author : Cook.Darwin
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Version: VERA.1.0
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longer fifo
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creaded: 2017/2/28
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madified:
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***********************************************/
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`timescale 1ns/1ps
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module axi4_wr_packet_fifo_A1 #(
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parameter PIPE = "OFF",
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parameter DEPTH = 4,
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parameter MAX_DATA_LEN = 1024*16
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)(
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axi_inf.slaver_wr axi_in,
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axi_inf.master_wr axi_out
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);
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//--->> AUXILIARY <<------------------
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logic auxiliary_fifo_empty;
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logic auxiliary_fifo_full;
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logic auxiliary_fifo_wr_en;
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logic auxiliary_fifo_rd_en;
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logic [axi_in.ASIZE+axi_in.LSIZE+axi_in.IDSIZE-1:0] auxiliary_fifo_rd_data;
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independent_clock_fifo #(
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.DEPTH (DEPTH ),
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.DSIZE (axi_in.ASIZE+axi_in.LSIZE+axi_in.IDSIZE)
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)auxiliary_independent_clock_fifo_inst(
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/* input */ .wr_clk (axi_in.axi_aclk ),
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/* input */ .wr_rst_n (axi_in.axi_aresetn ),
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/* input */ .rd_clk (axi_out.axi_aclk ),
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/* input */ .rd_rst_n (axi_out.axi_aresetn ),
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/* input [DSIZE-1:0] */ .wdata ({axi_in.axi_awid,axi_in.axi_awaddr,axi_in.axi_awlen}),
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/* input */ .wr_en (axi_in.axi_awvalid ),
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/* output logic[DSIZE-1:0] */ .rdata (auxiliary_fifo_rd_data ),
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/* input */ .rd_en ((auxiliary_fifo_rd_en && !auxiliary_fifo_empty) ),
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/* output logic */ .empty (auxiliary_fifo_empty ),
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/* output logic */ .full (auxiliary_fifo_full )
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);
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assign axi_in.axi_awready = !auxiliary_fifo_full;
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// assign axi_out.axi_awvalid = !auxiliary_fifo_empty && axi_out.axi_wvalid;
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// assign auxiliary_fifo_rd_en = axi_out.axi_awready && axi_out.axi_awvalid;
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logic stream_fifo_empty;
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axi_stream_inf #(.DSIZE(axi_in.ASIZE+axi_in.LSIZE+axi_in.IDSIZE)) id_add_len_in(.aclk(axi_out.axi_aclk),.aresetn(axi_out.axi_aresetn),.aclken(1'b1));
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assign id_add_len_in.axis_tdata = auxiliary_fifo_rd_data;
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assign id_add_len_in.axis_tvalid = !auxiliary_fifo_empty && !stream_fifo_empty;
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assign id_add_len_in.axis_tlast = 1'b1;
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assign auxiliary_fifo_rd_en = id_add_len_in.axis_tready && !stream_fifo_empty;
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logic axi_stream_en;
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`VCS_AXI4_CPT_LT(axi_out,master_wr_aux_no_resp,master_wr,Aux_Write)
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axi4_wr_auxiliary_gen_without_resp axi4_wr_auxiliary_gen_without_resp_inst(
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/* axi_stream_inf.slaver */ .id_add_len_in (id_add_len_in ), //tlast is not necessary
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// /* axi_inf.master_wr_aux_no_resp */ .axi_wr_aux (axi_out ),
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/* axi_inf.master_wr_aux_no_resp */ .axi_wr_aux (`axi_out_vcs_cptAux_Write ),
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/* output logic */ .stream_en (axi_stream_en )
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);
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//---<< AUXILIARY >>------------------
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//--->> BRESP<<------------------
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logic resp_fifo_empty;
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logic resp_fifo_full;
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independent_clock_fifo #(
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.DEPTH (DEPTH ),
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.DSIZE (2+axi_in.IDSIZE)
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)bresp_independent_clock_fifo_inst(
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/* input */ .wr_clk (axi_out.axi_aclk ),
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/* input */ .wr_rst_n (axi_out.axi_aresetn ),
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/* input */ .rd_clk (axi_in.axi_aclk ),
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/* input */ .rd_rst_n (axi_in.axi_aresetn ),
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/* input [DSIZE-1:0] */ .wdata ({axi_out.axi_bresp,axi_out.axi_bid} ),
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/* input */ .wr_en (axi_out.axi_bvalid ),
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/* output logic[DSIZE-1:0] */ .rdata ({axi_in.axi_bresp,axi_in.axi_bid} ),
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/* input */ .rd_en (axi_in.axi_bready ),
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/* output logic */ .empty (resp_fifo_empty ),
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/* output logic */ .full (resp_fifo_full )
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);
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assign axi_out.axi_bready = !resp_fifo_full;
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assign axi_in.axi_bvalid = !resp_fifo_empty;
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//---<< BRESP >>------------------
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//--->> DATA <<-----------------------
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axi_stream_inf #(
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.DSIZE(axi_in.DSIZE)
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)axis_in(
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.aclk (axi_in.axi_aclk ),
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.aresetn (axi_in.axi_aresetn ),
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.aclken (1'b1 )
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);
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axi_stream_inf #(
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.DSIZE(axi_out.DSIZE)
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)axis_valve_slaver(
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.aclk (axi_out.axi_aclk ),
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.aresetn (axi_out.axi_aresetn ),
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.aclken (1'b1 )
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);
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axi_stream_inf #(
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.DSIZE(axi_out.DSIZE)
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)axis_out(
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.aclk (axi_out.axi_aclk ),
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.aresetn (axi_out.axi_aresetn ),
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.aclken (1'b1 )
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);
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data_inf_c #(axi_out.DSIZE+1) axis_out_master_inf (axi_out.axi_aclk,axi_out.axi_aresetn);
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data_inf_c #(axi_out.DSIZE+1) axis_out_slaver_inf (axi_out.axi_aclk,axi_out.axi_aresetn);
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axi_stream_inf #(
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.DSIZE(axi_out.DSIZE)
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)pre_axis_out(
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.aclk (axi_out.axi_aclk ),
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.aresetn (axi_out.axi_aresetn ),
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.aclken (1'b1 )
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);
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// axi_stream_packet_fifo #(
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// .DEPTH (DEPTH) //2-4
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// )axi_stream_packet_fifo_inst(
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// /* axi_stream_inf.slaver */ .axis_in (axis_in ),
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// /* axi_stream_inf.master */ .axis_out (axis_valve_slaver )
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// );
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axi_stream_packet_long_fifo #(
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.DEPTH (DEPTH), //2-4
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.BYTE_DEPTH (MAX_DATA_LEN)
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)axi_stream_packet_fifo_inst(
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/* axi_stream_inf.slaver */ .axis_in (axis_in ),
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/* axi_stream_inf.master */ .axis_out (axis_valve_slaver )
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);
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assign stream_fifo_empty = !axis_valve_slaver.axis_tvalid;
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generate
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if(PIPE == "ON")begin
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axis_valve_with_pipe axis_valve_inst(
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// axis_valve axis_valve_inst(
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/* input */ .button (axi_stream_en ), //[1] OPEN ; [0] CLOSE
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/* axi_stream_inf.slaver */ .axis_in (axis_valve_slaver ),
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/* axi_stream_inf.master */ .axis_out (pre_axis_out )
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);
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assign axis_out_slaver_inf.valid = pre_axis_out.axis_tvalid;
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assign axis_out_slaver_inf.data = {pre_axis_out.axis_tdata,pre_axis_out.axis_tlast};
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assign pre_axis_out.axis_tready = axis_out_slaver_inf.ready;
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data_c_pipe_force_vld data_c_pipe_force_vld_inst(
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/* data_inf_c.slaver */ .slaver (axis_out_slaver_inf ),
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/* data_inf_c.master */ .master (axis_out_master_inf )
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);
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assign axis_out.axis_tvalid = axis_out_master_inf.valid;
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assign {axis_out.axis_tdata,axis_out.axis_tlast} = axis_out_master_inf.data;
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assign axis_out_master_inf.ready = axis_out.axis_tready;
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end else
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axis_valve axis_valve_inst(
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/* input */ .button (axi_stream_en ), //[1] OPEN ; [0] CLOSE
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/* axi_stream_inf.slaver */ .axis_in (axis_valve_slaver ),
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/* axi_stream_inf.master */ .axis_out (axis_out )
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);
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endgenerate
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assign axis_in.axis_tvalid = axi_in.axi_wvalid;
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assign axis_in.axis_tdata = axi_in.axi_wdata;
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assign axis_in.axis_tlast = axi_in.axi_wlast;
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assign axis_in.axis_tkeep = '1;
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assign axis_in.axis_tuser = '0;
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assign axi_in.axi_wready = axis_in.axis_tready;
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assign axi_out.axi_wvalid = axis_out.axis_tvalid;
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assign axi_out.axi_wdata = axis_out.axis_tdata;
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assign axi_out.axi_wlast = axis_out.axis_tlast;
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assign axis_out.axis_tready= axi_out.axi_wready;
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//---<< DATA >>-----------------------
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// axi4_wr_burst_track #(
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// .MAX_LEN (16 ),
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// .MAX_CYCLE (1000 )
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// )axi4_wr_burst_track_inst(
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// /* axi_inf.mirror_wr */ .axi4_mirror (axi_in )
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// );
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endmodule
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@@ -4,7 +4,7 @@ ___________ Cook Darwin __________
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_______________________________________
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descript:
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author : Cook.Darwin
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Version:
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Version:
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creaded: XXXX.XX.XX
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madified:
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***********************************************/
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@@ -55,22 +55,22 @@ axis_direct axis_direct_end_inf_inst0 (
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//-------- CLOCKs Total 3 ----------------------
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//--->> CheckClock <<----------------
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logic
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integer
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ClockSameDomain
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logic cc_done_8,cc_same_8;
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integer cc_afreq_8,cc_bfreq_8;
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ClockSameDomain CheckPClock_inst_8(
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/* input */ .aclk (origin_inf.aclk ),
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/* input */ .bclk (first_inf.aclk ),
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/* output logic */ .done (
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/* output logic */ .same (
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/* output integer */ .aFreqK (
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/* output integer */ .bFreqK (
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/* output logic */ .done (cc_done_8),
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/* output logic */ .same (cc_same_8),
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/* output integer */ .aFreqK (cc_afreq_8),
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/* output integer */ .bFreqK (cc_bfreq_8)
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initial begin
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wait(
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assert(
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wait(cc_done_8);
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assert(cc_same_8)
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else begin
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$error("--- Error : `axi_stream_split_channel` clock is not same, origin_inf.aclk< %0f M> != first_inf.aclk<%0f M>",1000000.0/
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$error("--- Error : `axi_stream_split_channel` clock is not same, origin_inf.aclk< %0f M> != first_inf.aclk<%0f M>",1000000.0/cc_afreq_8, 1000000.0/cc_bfreq_8);
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repeat(10)begin
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@(posedge origin_inf.aclk);
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end
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@@ -80,22 +80,22 @@ end
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80
80
|
//---<< CheckClock >>----------------
|
|
81
81
|
|
|
82
82
|
//--->> CheckClock <<----------------
|
|
83
|
-
logic
|
|
84
|
-
integer
|
|
85
|
-
ClockSameDomain
|
|
83
|
+
logic cc_done_9,cc_same_9;
|
|
84
|
+
integer cc_afreq_9,cc_bfreq_9;
|
|
85
|
+
ClockSameDomain CheckPClock_inst_9(
|
|
86
86
|
/* input */ .aclk (origin_inf.aclk ),
|
|
87
87
|
/* input */ .bclk (end_inf.aclk ),
|
|
88
|
-
/* output logic */ .done (
|
|
89
|
-
/* output logic */ .same (
|
|
90
|
-
/* output integer */ .aFreqK (
|
|
91
|
-
/* output integer */ .bFreqK (
|
|
88
|
+
/* output logic */ .done (cc_done_9),
|
|
89
|
+
/* output logic */ .same (cc_same_9),
|
|
90
|
+
/* output integer */ .aFreqK (cc_afreq_9),
|
|
91
|
+
/* output integer */ .bFreqK (cc_bfreq_9)
|
|
92
92
|
);
|
|
93
93
|
|
|
94
94
|
initial begin
|
|
95
|
-
wait(
|
|
96
|
-
assert(
|
|
95
|
+
wait(cc_done_9);
|
|
96
|
+
assert(cc_same_9)
|
|
97
97
|
else begin
|
|
98
|
-
$error("--- Error : `axi_stream_split_channel` clock is not same, origin_inf.aclk< %0f M> != end_inf.aclk<%0f M>",1000000.0/
|
|
98
|
+
$error("--- Error : `axi_stream_split_channel` clock is not same, origin_inf.aclk< %0f M> != end_inf.aclk<%0f M>",1000000.0/cc_afreq_9, 1000000.0/cc_bfreq_9);
|
|
99
99
|
repeat(10)begin
|
|
100
100
|
@(posedge origin_inf.aclk);
|
|
101
101
|
end
|
|
@@ -1,7 +1,8 @@
|
|
|
1
1
|
/**********************************************
|
|
2
2
|
_______________________________________
|
|
3
3
|
___________ Cook Darwin __________
|
|
4
|
-
|
|
4
|
+
_______________________________________
|
|
5
|
+
descript:
|
|
5
6
|
author : Cook.Darwin
|
|
6
7
|
Version: VERA.0.0
|
|
7
8
|
build from axi_streams_scaler
|
|
@@ -1,7 +1,8 @@
|
|
|
1
1
|
/**********************************************
|
|
2
2
|
_______________________________________
|
|
3
3
|
___________ Cook Darwin __________
|
|
4
|
-
|
|
4
|
+
_______________________________________
|
|
5
|
+
descript:
|
|
5
6
|
author : Cook.Darwin
|
|
6
7
|
Version: VERA.0.0
|
|
7
8
|
build from axi_streams_scaler
|
|
@@ -1,7 +1,8 @@
|
|
|
1
1
|
/**********************************************
|
|
2
2
|
_______________________________________
|
|
3
3
|
___________ Cook Darwin __________
|
|
4
|
-
|
|
4
|
+
_______________________________________
|
|
5
|
+
descript:
|
|
5
6
|
author : Cook.Darwin
|
|
6
7
|
Version: VERA.0.0
|
|
7
8
|
creaded: 2016/12/9
|
|
@@ -1,7 +1,8 @@
|
|
|
1
1
|
/**********************************************
|
|
2
2
|
_______________________________________
|
|
3
3
|
___________ Cook Darwin __________
|
|
4
|
-
|
|
4
|
+
_______________________________________
|
|
5
|
+
descript:
|
|
5
6
|
author : Cook.Darwin
|
|
6
7
|
Version: VERA.1.0 2018-4-16 12:13:05
|
|
7
8
|
use data_c_scaler
|
|
@@ -1,7 +1,8 @@
|
|
|
1
1
|
/**********************************************
|
|
2
2
|
_______________________________________
|
|
3
3
|
___________ Cook Darwin __________
|
|
4
|
-
|
|
4
|
+
_______________________________________
|
|
5
|
+
descript:
|
|
5
6
|
author : Cook.Darwin
|
|
6
7
|
Version: VERA.0.0
|
|
7
8
|
creaded: 2017/3/23
|
|
@@ -34,9 +34,10 @@ logic [DSIZE*16*8-1:0] value_tmp;
|
|
|
34
34
|
|
|
35
35
|
// assign value_tmp = {value,{(16*8-FIELD_LEN){1'b0}}};
|
|
36
36
|
generate
|
|
37
|
-
if(FIELD_LEN < 128)
|
|
37
|
+
if(FIELD_LEN < 128)begin
|
|
38
38
|
assign value_tmp[DSIZE*16*8-1-:DSIZE*FIELD_LEN] = value;
|
|
39
|
-
|
|
39
|
+
assign value_tmp[DSIZE*16*8-1-DSIZE*FIELD_LEN:0] = '0;
|
|
40
|
+
end else
|
|
40
41
|
assign value_tmp = value;
|
|
41
42
|
endgenerate
|
|
42
43
|
|
|
@@ -0,0 +1,129 @@
|
|
|
1
|
+
/**********************************************
|
|
2
|
+
_______________________________________
|
|
3
|
+
___________ Cook Darwin __________
|
|
4
|
+
_______________________________________
|
|
5
|
+
descript:
|
|
6
|
+
author : Cook.Darwin
|
|
7
|
+
Version: VERB.0.0 :
|
|
8
|
+
add custom signalssync to last
|
|
9
|
+
Version: VERB.1.0 :2017/3/15
|
|
10
|
+
add empty size
|
|
11
|
+
Version: VERB.1.1 :2017/11/3
|
|
12
|
+
user xilinx_fifo_verb
|
|
13
|
+
Version: VERB.1.F
|
|
14
|
+
longer fifo
|
|
15
|
+
creaded:
|
|
16
|
+
madified:
|
|
17
|
+
***********************************************/
|
|
18
|
+
`timescale 1ns/1ps
|
|
19
|
+
module axi_stream_packet_fifo_B1F #(
|
|
20
|
+
parameter DEPTH = 2, //2-4
|
|
21
|
+
parameter CSIZE = 1,
|
|
22
|
+
parameter DSIZE = 24,
|
|
23
|
+
parameter MAX_DATA_LEN = 1024*16
|
|
24
|
+
)(
|
|
25
|
+
input [CSIZE-1:0] in_cdata,
|
|
26
|
+
output[CSIZE-1:0] out_cdata,
|
|
27
|
+
axi_stream_inf.slaver slaver_inf,
|
|
28
|
+
axi_stream_inf.master master_inf
|
|
29
|
+
);
|
|
30
|
+
|
|
31
|
+
|
|
32
|
+
parameter LSIZE = $clog2(1024+1);
|
|
33
|
+
|
|
34
|
+
logic data_fifo_full;
|
|
35
|
+
logic data_fifo_empty;
|
|
36
|
+
|
|
37
|
+
|
|
38
|
+
long_fifo_verb #(
|
|
39
|
+
.DSIZE (DSIZE ),
|
|
40
|
+
.LENGTH (MAX_DATA_LEN )
|
|
41
|
+
)long_fifo_verb_inst(
|
|
42
|
+
/* input */ .wr_clk (slaver_inf.aclk ),
|
|
43
|
+
/* input */ .wr_rst (!slaver_inf.aresetn ),
|
|
44
|
+
/* input */ .rd_clk (master_inf.aclk ),
|
|
45
|
+
/* input */ .rd_rst (!master_inf.aresetn ),
|
|
46
|
+
/* input [DSIZE-1:0] */ .din (slaver_inf.axis_tdata ),
|
|
47
|
+
/* input */ .wr_en ((slaver_inf.axis_tvalid && slaver_inf.axis_tready) ),
|
|
48
|
+
/* input */ .rd_en ((master_inf.axis_tvalid && master_inf.axis_tready) ),
|
|
49
|
+
/* output [DSIZE-1:0] */ .dout (master_inf.axis_tdata ),
|
|
50
|
+
/* output */ .full (data_fifo_full ),
|
|
51
|
+
/* output */ .empty (data_fifo_empty )
|
|
52
|
+
);
|
|
53
|
+
|
|
54
|
+
//---<< NATIVE FIFO IP >>------------------------------
|
|
55
|
+
|
|
56
|
+
//--->> PACKET <<--------------------------------------
|
|
57
|
+
logic packet_fifo_full;
|
|
58
|
+
logic packet_fifo_empty;
|
|
59
|
+
logic [15:0] w_bytes_total;
|
|
60
|
+
logic [15:0] r_bytes_total;
|
|
61
|
+
logic w_total_eq_1;
|
|
62
|
+
logic r_total_eq_1;
|
|
63
|
+
|
|
64
|
+
// assign w_total_eq_1 = w_bytes_total=='0;
|
|
65
|
+
assign w_total_eq_1 = slaver_inf.axis_tcnt =='0;
|
|
66
|
+
|
|
67
|
+
localparam IDEPTH = (DEPTH<4)? 4 : DEPTH;
|
|
68
|
+
|
|
69
|
+
independent_clock_fifo #(
|
|
70
|
+
.DEPTH (IDEPTH ),
|
|
71
|
+
.DSIZE (16+1+CSIZE )
|
|
72
|
+
)common_independent_clock_fifo_inst(
|
|
73
|
+
/* input */ .wr_clk (slaver_inf.aclk ),
|
|
74
|
+
/* input */ .wr_rst_n (slaver_inf.aresetn ),
|
|
75
|
+
/* input */ .rd_clk (master_inf.aclk ),
|
|
76
|
+
/* input */ .rd_rst_n (master_inf.aresetn ),
|
|
77
|
+
/* input [DSIZE-1:0] */ .wdata ({w_total_eq_1,w_bytes_total,in_cdata} ),
|
|
78
|
+
/* input */ .wr_en ((slaver_inf.axis_tvalid && slaver_inf.axis_tlast && slaver_inf.axis_tready) ),
|
|
79
|
+
/* output logic[DSIZE-1:0] */ .rdata ({r_total_eq_1,r_bytes_total,out_cdata} ),
|
|
80
|
+
/* input */ .rd_en ((master_inf.axis_tvalid && master_inf.axis_tlast && master_inf.axis_tready) ),
|
|
81
|
+
/* output logic */ .empty (packet_fifo_empty ),
|
|
82
|
+
/* output logic */ .full (packet_fifo_full )
|
|
83
|
+
);
|
|
84
|
+
|
|
85
|
+
assign slaver_inf.axis_tready = !packet_fifo_full && !data_fifo_full;
|
|
86
|
+
assign master_inf.axis_tvalid = !packet_fifo_empty && !data_fifo_empty;
|
|
87
|
+
//---<< PACKET >>--------------------------------------
|
|
88
|
+
//--->> bytes counter <<-------------------------------
|
|
89
|
+
logic reset_w_bytes;
|
|
90
|
+
assign #1 reset_w_bytes = slaver_inf.axis_tvalid && slaver_inf.axis_tlast && slaver_inf.axis_tready;
|
|
91
|
+
|
|
92
|
+
always@(posedge slaver_inf.aclk,negedge slaver_inf.aresetn)
|
|
93
|
+
if(~slaver_inf.aresetn) w_bytes_total <= '0;
|
|
94
|
+
else begin
|
|
95
|
+
if(reset_w_bytes)
|
|
96
|
+
w_bytes_total <= '0;
|
|
97
|
+
else if(slaver_inf.axis_tvalid && slaver_inf.axis_tready)
|
|
98
|
+
w_bytes_total <= w_bytes_total + 1'b1;
|
|
99
|
+
else w_bytes_total <= w_bytes_total;
|
|
100
|
+
end
|
|
101
|
+
|
|
102
|
+
logic [15:0] out_cnt;
|
|
103
|
+
|
|
104
|
+
always@(posedge master_inf.aclk,negedge master_inf.aresetn)
|
|
105
|
+
if(~master_inf.aresetn) out_cnt <= '0;
|
|
106
|
+
else begin
|
|
107
|
+
if(master_inf.axis_tvalid && master_inf.axis_tlast && master_inf.axis_tready)
|
|
108
|
+
out_cnt <= '0;
|
|
109
|
+
else if(master_inf.axis_tvalid && master_inf.axis_tready)
|
|
110
|
+
out_cnt <= out_cnt + 1'b1;
|
|
111
|
+
else out_cnt <= out_cnt;
|
|
112
|
+
end
|
|
113
|
+
//---<< bytes counter >>-------------------------------
|
|
114
|
+
//--->> READ LAST <<-----------------------------------
|
|
115
|
+
logic native_last;
|
|
116
|
+
|
|
117
|
+
always@(posedge master_inf.aclk,negedge master_inf.aresetn)
|
|
118
|
+
if(~master_inf.aresetn) native_last <= 1'b0;
|
|
119
|
+
else begin
|
|
120
|
+
if(master_inf.axis_tvalid && native_last && master_inf.axis_tready)
|
|
121
|
+
native_last <= 1'b0;
|
|
122
|
+
else if(out_cnt == (r_bytes_total-1) && master_inf.axis_tvalid && master_inf.axis_tready)
|
|
123
|
+
native_last <= 1'b1;
|
|
124
|
+
else native_last <= native_last;
|
|
125
|
+
end
|
|
126
|
+
|
|
127
|
+
assign master_inf.axis_tlast = native_last || r_total_eq_1;
|
|
128
|
+
//---<< READ LAST >>-----------------------------------
|
|
129
|
+
endmodule
|
|
@@ -0,0 +1,101 @@
|
|
|
1
|
+
/**********************************************
|
|
2
|
+
_______________________________________
|
|
3
|
+
___________ Cook Darwin __________
|
|
4
|
+
_______________________________________
|
|
5
|
+
descript: 解析大块的值域用于 common_frame_table
|
|
6
|
+
author : Cook.Darwin
|
|
7
|
+
Version: VERA.2.0 2017/9/11
|
|
8
|
+
resever value
|
|
9
|
+
Version: VERA.2.0 2017/12/11
|
|
10
|
+
use parse_common_frame_table_A2
|
|
11
|
+
Version: VERB.0.0 ###### Tue Oct 20 09:42:34 CST 2020
|
|
12
|
+
rebuild
|
|
13
|
+
creaded: 2016/12/22
|
|
14
|
+
madified:
|
|
15
|
+
***********************************************/
|
|
16
|
+
`timescale 1ns/1ps
|
|
17
|
+
module parse_big_field_table_main #(
|
|
18
|
+
parameter DSIZE = 8,
|
|
19
|
+
parameter FIELD_LEN = 16*8, //MAX 16*8
|
|
20
|
+
parameter START_INDEX = 0
|
|
21
|
+
)(
|
|
22
|
+
output logic[START_INDEX:DSIZE*FIELD_LEN-1] value,
|
|
23
|
+
output logic out_valid,
|
|
24
|
+
axi_stream_inf.slaver cm_tb_s,
|
|
25
|
+
axi_stream_inf.master cm_tb_m
|
|
26
|
+
);
|
|
27
|
+
|
|
28
|
+
localparam VSIZE = $clog2(FIELD_LEN);
|
|
29
|
+
|
|
30
|
+
import SystemPkg::*;
|
|
31
|
+
|
|
32
|
+
initial begin
|
|
33
|
+
assert(DSIZE == cm_tb_s.DSIZE)
|
|
34
|
+
else begin
|
|
35
|
+
$error("DSIZE<%d> != stream.DSIZE<%d>",DSIZE, cm_tb_s.DSIZE);
|
|
36
|
+
end
|
|
37
|
+
end
|
|
38
|
+
|
|
39
|
+
wire clock,rst_n,clken;
|
|
40
|
+
|
|
41
|
+
axi_stream_inf #(.DSIZE(DSIZE)) parse_stream (.aclk(clock),.aresetn(rst_n),.aclken(clken));
|
|
42
|
+
|
|
43
|
+
assign clock = cm_tb_s.aclk;
|
|
44
|
+
assign rst_n = cm_tb_s.aresetn;
|
|
45
|
+
assign clken = cm_tb_s.aclken;
|
|
46
|
+
|
|
47
|
+
|
|
48
|
+
assign parse_stream.axis_tkeep = cm_tb_s.axis_tkeep ;
|
|
49
|
+
assign parse_stream.axis_tuser = cm_tb_s.axis_tuser ;
|
|
50
|
+
assign parse_stream.axis_tlast = cm_tb_s.axis_tlast ;
|
|
51
|
+
assign parse_stream.axis_tdata = cm_tb_s.axis_tdata ;
|
|
52
|
+
assign parse_stream.axis_tvalid= cm_tb_s.axis_tvalid;
|
|
53
|
+
assign parse_stream.axis_tready= cm_tb_m.axis_tready;
|
|
54
|
+
assign cm_tb_s.axis_tready = cm_tb_m.axis_tready;
|
|
55
|
+
|
|
56
|
+
|
|
57
|
+
logic region_valid;
|
|
58
|
+
|
|
59
|
+
always_ff@(posedge clock,negedge rst_n)begin
|
|
60
|
+
if(~rst_n) region_valid <= 1'b1;
|
|
61
|
+
else begin
|
|
62
|
+
if(parse_stream.axis_tvalid && parse_stream.axis_tready && parse_stream.axis_tlast)
|
|
63
|
+
region_valid <= 1'b1;
|
|
64
|
+
else if(parse_stream.axis_tvalid && parse_stream.axis_tready && parse_stream.axis_tcnt[VSIZE:0] == (FIELD_LEN-1'b1))
|
|
65
|
+
region_valid <= 1'b0;
|
|
66
|
+
else region_valid <= region_valid;
|
|
67
|
+
end
|
|
68
|
+
end
|
|
69
|
+
|
|
70
|
+
|
|
71
|
+
logic[DSIZE-1:0] value_array [0:FIELD_LEN-1];
|
|
72
|
+
|
|
73
|
+
always_ff@(posedge clock,negedge rst_n)begin
|
|
74
|
+
if(~rst_n)
|
|
75
|
+
foreach(value_array[i])
|
|
76
|
+
value_array[i] <= '0;
|
|
77
|
+
else begin
|
|
78
|
+
if(region_valid)begin
|
|
79
|
+
value_array[parse_stream.axis_tcnt[VSIZE-1:0]] <= parse_stream.axis_tdata;
|
|
80
|
+
end
|
|
81
|
+
end
|
|
82
|
+
end
|
|
83
|
+
|
|
84
|
+
assign value = {>>{value_array}};
|
|
85
|
+
|
|
86
|
+
always_ff@(posedge clock,negedge rst_n)begin
|
|
87
|
+
if(~rst_n) out_valid <= 1'b0;
|
|
88
|
+
else begin
|
|
89
|
+
if(parse_stream.axis_tvalid && parse_stream.axis_tready && parse_stream.axis_tlast)
|
|
90
|
+
if(out_valid)
|
|
91
|
+
out_valid <= 1'b0;
|
|
92
|
+
else out_valid <= 1'b1;
|
|
93
|
+
else if(parse_stream.axis_tvalid && parse_stream.axis_tready && parse_stream.axis_tcnt[VSIZE:0] == (FIELD_LEN-1'b1))
|
|
94
|
+
out_valid <= 1'b1;
|
|
95
|
+
else if(region_valid)
|
|
96
|
+
out_valid <= 1'b0;
|
|
97
|
+
else out_valid <= out_valid;
|
|
98
|
+
end
|
|
99
|
+
end
|
|
100
|
+
|
|
101
|
+
endmodule
|
|
@@ -0,0 +1,94 @@
|
|
|
1
|
+
/**********************************************
|
|
2
|
+
_______________________________________
|
|
3
|
+
___________ Cook Darwin __________
|
|
4
|
+
_______________________________________
|
|
5
|
+
descript: 解析大块的值域用于 common_frame_table
|
|
6
|
+
author : Cook.Darwin
|
|
7
|
+
Version: VERA.2.0 2017/9/11
|
|
8
|
+
resever value
|
|
9
|
+
Version: VERA.2.0 2017/12/11
|
|
10
|
+
use parse_common_frame_table_A2
|
|
11
|
+
Version: VERB.0.0 ###### Tue Oct 20 09:42:34 CST 2020
|
|
12
|
+
rebuild
|
|
13
|
+
creaded: 2016/12/22
|
|
14
|
+
madified:
|
|
15
|
+
***********************************************/
|
|
16
|
+
`timescale 1ns/1ps
|
|
17
|
+
module parse_big_field_table_mirror #(
|
|
18
|
+
parameter DSIZE = 8,
|
|
19
|
+
parameter FIELD_LEN = 16*8, //MAX 16*8
|
|
20
|
+
parameter START_INDEX = 0
|
|
21
|
+
)(
|
|
22
|
+
output logic[START_INDEX:DSIZE*FIELD_LEN-1] value,
|
|
23
|
+
output logic out_valid,
|
|
24
|
+
axi_stream_inf.mirror cm_mirror
|
|
25
|
+
);
|
|
26
|
+
|
|
27
|
+
localparam VSIZE = $clog2(FIELD_LEN);
|
|
28
|
+
|
|
29
|
+
import SystemPkg::*;
|
|
30
|
+
|
|
31
|
+
|
|
32
|
+
wire clock,rst_n,clken;
|
|
33
|
+
|
|
34
|
+
axi_stream_inf #(.DSIZE(DSIZE)) parse_stream (.aclk(clock),.aresetn(rst_n),.aclken(clken));
|
|
35
|
+
|
|
36
|
+
|
|
37
|
+
|
|
38
|
+
assign clock = cm_mirror.aclk;
|
|
39
|
+
assign rst_n = cm_mirror.aresetn;
|
|
40
|
+
assign clken = cm_mirror.aclken;
|
|
41
|
+
|
|
42
|
+
assign parse_stream.axis_tkeep = cm_mirror.axis_tkeep ;
|
|
43
|
+
assign parse_stream.axis_tuser = cm_mirror.axis_tuser ;
|
|
44
|
+
assign parse_stream.axis_tlast = cm_mirror.axis_tlast ;
|
|
45
|
+
assign parse_stream.axis_tdata = cm_mirror.axis_tdata ;
|
|
46
|
+
assign parse_stream.axis_tvalid= cm_mirror.axis_tvalid;
|
|
47
|
+
assign parse_stream.axis_tready= cm_mirror.axis_tready;
|
|
48
|
+
|
|
49
|
+
|
|
50
|
+
logic region_valid;
|
|
51
|
+
|
|
52
|
+
always_ff@(posedge clock,negedge rst_n)begin
|
|
53
|
+
if(~rst_n) region_valid <= 1'b1;
|
|
54
|
+
else begin
|
|
55
|
+
if(parse_stream.axis_tvalid && parse_stream.axis_tready && parse_stream.axis_tlast)
|
|
56
|
+
region_valid <= 1'b1;
|
|
57
|
+
else if(parse_stream.axis_tvalid && parse_stream.axis_tready && parse_stream.axis_tcnt[VSIZE:0] == (FIELD_LEN-1'b1))
|
|
58
|
+
region_valid <= 1'b0;
|
|
59
|
+
else region_valid <= region_valid;
|
|
60
|
+
end
|
|
61
|
+
end
|
|
62
|
+
|
|
63
|
+
|
|
64
|
+
logic[DSIZE-1:0] value_array [0:FIELD_LEN-1];
|
|
65
|
+
|
|
66
|
+
always_ff@(posedge clock,negedge rst_n)begin
|
|
67
|
+
if(~rst_n)
|
|
68
|
+
foreach(value_array[i])
|
|
69
|
+
value_array[i] <= '0;
|
|
70
|
+
else begin
|
|
71
|
+
if(region_valid)begin
|
|
72
|
+
value_array[parse_stream.axis_tcnt[VSIZE-1:0]] <= parse_stream.axis_tdata;
|
|
73
|
+
end
|
|
74
|
+
end
|
|
75
|
+
end
|
|
76
|
+
|
|
77
|
+
assign value = {>>{value_array}};
|
|
78
|
+
|
|
79
|
+
always_ff@(posedge clock,negedge rst_n)begin
|
|
80
|
+
if(~rst_n) out_valid <= 1'b0;
|
|
81
|
+
else begin
|
|
82
|
+
if(parse_stream.axis_tvalid && parse_stream.axis_tready && parse_stream.axis_tlast)
|
|
83
|
+
if(out_valid)
|
|
84
|
+
out_valid <= 1'b0;
|
|
85
|
+
else out_valid <= 1'b1;
|
|
86
|
+
else if(parse_stream.axis_tvalid && parse_stream.axis_tready && parse_stream.axis_tcnt[VSIZE:0] == (FIELD_LEN-1'b1))
|
|
87
|
+
out_valid <= 1'b1;
|
|
88
|
+
else if(region_valid)
|
|
89
|
+
out_valid <= 1'b0;
|
|
90
|
+
else out_valid <= out_valid;
|
|
91
|
+
end
|
|
92
|
+
end
|
|
93
|
+
|
|
94
|
+
endmodule
|