axi_tdl 0.1.20 → 0.2.0

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Files changed (42) hide show
  1. checksums.yaml +4 -4
  2. data/lib/axi/AXI4/axi4_direct_algin_addr_step.sv +223 -0
  3. data/lib/axi/AXI4/axi4_direct_verc.sv +54 -5
  4. data/lib/axi/AXI4/axi4_long_to_axi4_wide_B1.sv +146 -0
  5. data/lib/axi/AXI4/packet_fifo/axi4_packet_fifo_verb.sv +62 -0
  6. data/lib/axi/AXI4/packet_fifo/axi4_wr_packet_fifo.sv +4 -3
  7. data/lib/axi/AXI4/wide_axis_to_axi4_wr.sv +1 -1
  8. data/lib/axi/AXI4/width_convert/axi4_data_convert_verb.sv +280 -0
  9. data/lib/axi/AXI_stream/axi_stream_interconnect_M2S_cpVCS.sv +80 -0
  10. data/lib/axi/AXI_stream/axi_stream_split_channel.sv +20 -20
  11. data/lib/axi/AXI_stream/axis_append_A1.sv +15 -2
  12. data/lib/axi/AXI_stream/axis_uncompress_verb.sv +9 -9
  13. data/lib/axi/AXI_stream/parse_big_field_table_verb.sv +3 -2
  14. data/lib/axi/data_interface/data_inf_c/data_c_pipe_sync_seam.sv +10 -10
  15. data/lib/axi/data_interface/data_inf_c/data_c_scaler_A1.sv +2 -1
  16. data/lib/axi/interface_define/axi_inf.sv +1 -1
  17. data/lib/axi/macro/RTL/define_macro.sv +210 -0
  18. data/lib/axi/macro/SIM/define_macro.sv +194 -0
  19. data/lib/axi_tdl/version.rb +1 -1
  20. data/lib/tdl/auto_script/import_sdl.rb +3 -0
  21. data/lib/tdl/axi4/axi4_interconnect_verb.rb +76 -10
  22. data/lib/tdl/examples/11_test_unit/exp_test_unit.sv +7 -33
  23. data/lib/tdl/examples/11_test_unit/tb_exp_test_unit.sv +1 -1
  24. data/lib/tdl/examples/11_test_unit/tb_exp_test_unit_sim.sv +3 -14
  25. data/lib/tdl/examples/11_test_unit/tu0.sv +1 -1
  26. data/lib/tdl/examples/2_hdl_class/tmp/test_module_var.sv +2 -2
  27. data/lib/tdl/examples/2_hdl_class/tmp/test_vcs_string.sv +1 -1
  28. data/lib/tdl/examples/8_top_module/dve.tcl +0 -6
  29. data/lib/tdl/examples/8_top_module/test_top.sv +1 -1
  30. data/lib/tdl/examples/9_itegration/clock_manage/tu_ClockManage_test_clock_bb.sv +35 -0
  31. data/lib/tdl/examples/9_itegration/tb_test_tttop_sim.sv +2 -2
  32. data/lib/tdl/examples/9_itegration/test_tttop.sv +38 -7
  33. data/lib/tdl/examples/9_itegration/test_tttop_sim.sv +7 -38
  34. data/lib/tdl/examples/9_itegration/top.rb +1 -1
  35. data/lib/tdl/exlib/itegration_test_unit.rb +13 -0
  36. data/lib/tdl/exlib/itegration_verb.rb +22 -17
  37. data/lib/tdl/rebuild_ele/ele_base.rb +15 -3
  38. data/lib/tdl/sdlmodule/sdlmodule_arraychain.rb +1 -0
  39. data/lib/tdl/sdlmodule/sdlmodule_instance.rb +1 -1
  40. data/lib/tdl/sdlmodule/test_unit_module.rb +12 -16
  41. data/lib/tdl/tdl.rb +1 -0
  42. metadata +11 -2
@@ -13,8 +13,6 @@ gui_set_time_units 1ps
13
13
  ## ==== [add_signal] ===== ##
14
14
 
15
15
 
16
-
17
-
18
16
  ## 创建波形窗口
19
17
  if {![info exists useOldWindow]} {
20
18
  set useOldWindow true
@@ -44,8 +42,6 @@ gui_wv_zoom_timerange -id ${Wave.3} 0 1000000000
44
42
  ## === [add_signal_wave] === ##
45
43
 
46
44
 
47
-
48
-
49
45
  gui_seek_criteria -id ${Wave.3} {Any Edge}
50
46
 
51
47
 
@@ -63,8 +59,6 @@ gui_list_set_filter -id ${Wave.3} -text {*}
63
59
  ## === [add_bar] === ##
64
60
 
65
61
 
66
-
67
-
68
62
  gui_marker_move -id ${Wave.3} {C1} 560248001
69
63
  gui_view_scroll -id ${Wave.3} -vertical -set 35
70
64
  gui_show_grid -id ${Wave.3} -enable false
@@ -5,7 +5,7 @@ _______________________________________
5
5
  descript:
6
6
  author : Cook.Darwin
7
7
  Version: VERA.0.0
8
- created: 2021-09-30 21:21:38 +0800
8
+ created: 2022-07-10 11:21:37 +0800
9
9
  madified:
10
10
  ***********************************************/
11
11
  `timescale 1ns/1ps
@@ -0,0 +1,35 @@
1
+ /**********************************************
2
+ _______________________________________
3
+ ___________ Cook Darwin __________
4
+ _______________________________________
5
+ descript:
6
+ author : Cook.Darwin
7
+ Version: VERA.0.0
8
+ created: 2022-07-10 11:14:33 +0800
9
+ madified:
10
+ ***********************************************/
11
+ `timescale 1ns/1ps
12
+
13
+ module tu_ClockManage_test_clock_bb(
14
+ input from_up_pass,
15
+ output logic to_down_pass
16
+ );
17
+
18
+ //==========================================================================
19
+ //-------- define ----------------------------------------------------------
20
+
21
+
22
+ //==========================================================================
23
+ //-------- instance --------------------------------------------------------
24
+
25
+ //==========================================================================
26
+ //-------- expression ------------------------------------------------------
27
+ initial begin
28
+ to_down_pass = 1'b0;
29
+ wait(from_up_pass);
30
+ $root.tb_test_tttop_sim.test_unit_region = "tu_ClockManage_test_clock_bb";
31
+ $display("--------------- Current test_unit <%0s> --------------------", "tu_ClockManage_test_clock_bb");
32
+ to_down_pass = 1'b1;
33
+ end
34
+
35
+ endmodule
@@ -5,7 +5,7 @@ _______________________________________
5
5
  descript:
6
6
  author : Cook.Darwin
7
7
  Version: VERA.0.0
8
- created: 2021-04-03 14:05:10 +0800
8
+ created: 2022-07-10 11:14:33 +0800
9
9
  madified:
10
10
  ***********************************************/
11
11
  `timescale 1ns/1ps
@@ -23,7 +23,7 @@ logic unit_pass_d;
23
23
  test_tttop_sim rtl_top(
24
24
  /* input clock */.global_sys_clk (gl_clk )
25
25
  );
26
- test_clock_bb test_unit_0(
26
+ tu_ClockManage_test_clock_bb test_unit_0(
27
27
  /* input */.from_up_pass (unit_pass_u ),
28
28
  /* output */.to_down_pass (unit_pass_d )
29
29
  );
@@ -1,9 +1,40 @@
1
-
1
+ /**********************************************
2
+ _______________________________________
3
+ ___________ Cook Darwin __________
4
+ _______________________________________
5
+ descript:
6
+ author : Cook.Darwin
7
+ Version: VERA.0.0
8
+ created: 2022-07-10 11:21:57 +0800
9
+ madified:
10
+ ***********************************************/
2
11
  `timescale 1ns/1ps
3
- module test_tttop();
4
- initial begin
5
- #(1us);
6
- $warning("Check TopModule.sim,please!!!");
7
- $stop;
8
- end
12
+
13
+ module test_tttop (
14
+ input global_sys_clk
15
+ );
16
+
17
+ //==========================================================================
18
+ //-------- define ----------------------------------------------------------
19
+ logic clock_100M;
20
+ logic rstn_100M;
21
+ axi_stream_inf #(.DSIZE(16),.FreqM(100),.USIZE(1)) x_origin_inf (.aclk(clock_100M),.aresetn(rstn_100M),.aclken(1'b1)) ;
22
+ //==========================================================================
23
+ //-------- instance --------------------------------------------------------
24
+ simple_clock simple_clock_inst(
25
+ /* input clock */.sys_clk (global_sys_clk ),
26
+ /* output clock */.clock (clock_100M ),
27
+ /* output reset */.rst_n (rstn_100M )
28
+ );
29
+ a_test_md a_test_md_inst(
30
+ /* input clock */.clock (clock_100M ),
31
+ /* input reset */.rst (~rstn_100M ),
32
+ /* axi_stream_inf.master */.origin_inf (x_origin_inf )
33
+ );
34
+ //==========================================================================
35
+ //-------- expression ------------------------------------------------------
36
+ assign x_origin_inf.axis_tvalid = 1'b0;
37
+ assign x_origin_inf.axis_tdata = '0;
38
+ assign x_origin_inf.axis_tlast = 1'b0;
39
+
9
40
  endmodule
@@ -1,40 +1,9 @@
1
- /**********************************************
2
- _______________________________________
3
- ___________ Cook Darwin __________
4
- _______________________________________
5
- descript:
6
- author : Cook.Darwin
7
- Version: VERA.0.0
8
- created: 2021-09-30 21:21:22 +0800
9
- madified:
10
- ***********************************************/
11
- `timescale 1ns/1ps
12
-
13
- module test_tttop_sim (
14
- input global_sys_clk
15
- );
16
-
17
- //==========================================================================
18
- //-------- define ----------------------------------------------------------
19
- logic clock_100M;
20
- logic rstn_100M;
21
- axi_stream_inf #(.DSIZE(16),.FreqM(100),.USIZE(1)) x_origin_inf (.aclk(clock_100M),.aresetn(rstn_100M),.aclken(1'b1)) ;
22
- //==========================================================================
23
- //-------- instance --------------------------------------------------------
24
- simple_clock simple_clock_inst(
25
- /* input clock */.sys_clk (global_sys_clk ),
26
- /* output clock */.clock (clock_100M ),
27
- /* output reset */.rst_n (rstn_100M )
28
- );
29
- a_test_md a_test_md_inst(
30
- /* input clock */.clock (clock_100M ),
31
- /* input reset */.rst (~rstn_100M ),
32
- /* axi_stream_inf.master */.origin_inf (x_origin_inf )
33
- );
34
- //==========================================================================
35
- //-------- expression ------------------------------------------------------
36
- assign x_origin_inf.axis_tvalid = 1'b0;
37
- assign x_origin_inf.axis_tdata = '0;
38
- assign x_origin_inf.axis_tlast = 1'b0;
39
1
 
2
+ `timescale 1ns/1ps
3
+ module test_tttop_sim();
4
+ initial begin
5
+ #(1us);
6
+ $warning("Check TopModule.sim,please!!!");
7
+ $stop;
8
+ end
40
9
  endmodule
@@ -8,5 +8,5 @@ TopModule.test_tttop(__dir__) do
8
8
  add_itegration('ClockManage',pins_map: :CM)
9
9
  add_itegration('ABlock')
10
10
 
11
- add_test_unit('test_clock_bb')
11
+ add_test_unit(ClockManage.test_clock_bb)
12
12
  end
@@ -0,0 +1,13 @@
1
+
2
+ class ItegrationTestUnit
3
+ "
4
+ test unit in Itgt
5
+ "
6
+ attr_accessor :path,:block,:itgt,:name
7
+ def initialize(name: 'tmp',path: '',block: Proc.new , itgt: nil )
8
+ @path = path
9
+ @block = block
10
+ @itgt = itgt
11
+ @name = name
12
+ end
13
+ end
@@ -470,17 +470,18 @@ class ItegrationVerb
470
470
  return
471
471
  end
472
472
 
473
- blocks.each do |b|
473
+ blocks.each do |key,valueItgtTU|
474
474
  # @top_module.techbench.instance_exec(self,&b.clone)
475
- sdlm = TestUnitModule.new(name: b[0],out_sv_path: b[1])
475
+ sdlm = TestUnitModule.new(name: key ,out_sv_path: valueItgtTU.path )
476
476
  $_implicit_curr_itgt_.with_none_itgt do
477
477
  sdlm.input - "from_up_pass"
478
478
  sdlm.output.logic - "to_down_pass"
479
479
  end
480
- sdlm.instance_exec(self,&b[2])
480
+ sdlm.instance_exec(self,&valueItgtTU.block)
481
481
 
482
- if b[1] && File.exist?(b[1])
482
+ if valueItgtTU.path && File.exist?(valueItgtTU.path)
483
483
  sdlm.gen_sv_module
484
+ Tdl.Puts "[warnning] #{key} path error !!!"
484
485
  else
485
486
  sdlm.origin_sv = true
486
487
  end
@@ -491,27 +492,26 @@ class ItegrationVerb
491
492
  end
492
493
 
493
494
  def self.test_unit_inst(&filter_block)
494
- # blocks = self.instance_variable_get("@_inst_test_unit_blocks_")
495
- # blocks = instance_variable_get("@_inst_test_unit_blocks_") || []
496
- blocks = @@_inst_test_unit_blocks_ || []
495
+ blocks = @@_inst_test_unit_blocks_ || {}
497
496
  return unless blocks
498
497
  return if blocks.empty?
499
498
  return unless TopModule.sim
500
499
 
501
500
  ItegrationVerb.curr_itgt_push nil
502
501
 
503
- blocks.each do |b|
502
+ blocks.each do |key,valueItgtTU|
504
503
  # @top_module.techbench.instance_exec(self,&b.clone)
505
- if !(block_given?) || filter_block.call(b[0])
506
- sdlm = TestUnitModule.new(name: b[0],out_sv_path: b[1])
504
+ if !(block_given?) || filter_block.call(valueItgtTU)
505
+ sdlm = TestUnitModule.new(name: "tu_#{key}",out_sv_path: valueItgtTU.path)
507
506
  $_implicit_curr_itgt_.with_none_itgt do
508
507
  sdlm.input - "from_up_pass"
509
508
  sdlm.output.logic - "to_down_pass"
510
509
  end
511
- sdlm.instance_exec(nil,&b[2])
510
+ sdlm.instance_exec(nil,&valueItgtTU.block)
512
511
 
513
- if b[1] && File.exist?(b[1])
512
+ if valueItgtTU.path && File.exist?(valueItgtTU.path)
514
513
  sdlm.gen_sv_module
514
+ Tdl.Puts "[warnning] #{key} path error !!!"
515
515
  else
516
516
  sdlm.origin_sv = true
517
517
  end
@@ -776,12 +776,17 @@ class ItegrationVerb
776
776
  end
777
777
 
778
778
  ## 添加测试用例
779
- @@_inst_test_unit_blocks_ = []
779
+ @@_inst_test_unit_blocks_ = {}
780
780
  def self.def_test_unit(name,path,&block)
781
- # @@_inst_test_unit_blocks_ = instance_variable_get("@_inst_test_unit_blocks_")
782
- @@_inst_test_unit_blocks_ ||= []
783
- @@_inst_test_unit_blocks_ << [name.to_s, path, block]
784
- # instance_variable_set("@_inst_test_unit_blocks_",_inst_test_unit_blocks_)
781
+ @@_inst_test_unit_blocks_ ||= {}
782
+ # @@_inst_test_unit_blocks_ << [name.to_s, path, block]
783
+ itgt_testunit = ItegrationTestUnit.new(name:name,path:path, block: block, itgt: self)
784
+ @@_inst_test_unit_blocks_["#{self}_#{name.to_s}"] = itgt_testunit
785
+
786
+ self.define_singleton_method(name.to_s) do
787
+ itgt_testunit
788
+ end
789
+
785
790
  @@_inst_test_unit_blocks_
786
791
  end
787
792
 
@@ -128,7 +128,11 @@ module TdlSpace
128
128
  define_method(tdl_key) do
129
129
  rel = self.instance_variable_get("@_#{tdl_key}_")
130
130
  unless rel
131
- TdlSpace::ArrayChain.create(obj: "#{inst_name}.#{hdl_key}".to_nq, belong_to_module: belong_to_module)
131
+ if !dimension || dimension.empty?
132
+ TdlSpace::ArrayChain.create(obj: "#{inst_name}.#{hdl_key}".to_nq, belong_to_module: belong_to_module)
133
+ else
134
+ TdlSpace::ArrayChain.create(obj: "#{inst_name}[0].#{hdl_key}".to_nq, belong_to_module: belong_to_module)
135
+ end
132
136
  else
133
137
  rel
134
138
  end
@@ -171,7 +175,11 @@ module TdlSpace
171
175
  self.class_exec(tdl_key) do |tdl_key|
172
176
  define_method('reset') do
173
177
  rel = self.instance_variable_get("@_#{tdl_key}_")
174
- rel || TdlSpace::ArrayChain.create(obj:"#{self.inst_name}.#{hdl_key}", belong_to_module: belong_to_module)
178
+ if !dimension || dimension.empty?
179
+ rel || TdlSpace::ArrayChain.create(obj:"#{self.inst_name}.#{hdl_key}", belong_to_module: belong_to_module)
180
+ else
181
+ rel || TdlSpace::ArrayChain.create(obj:"#{self.inst_name}[0].#{hdl_key}", belong_to_module: belong_to_module)
182
+ end
175
183
  end
176
184
 
177
185
  define_method("reset=") do |arg|
@@ -200,7 +208,11 @@ module TdlSpace
200
208
  self.class_exec(tdl_key) do |tdl_key|
201
209
  define_method(tdl_key) do
202
210
  rel = self.instance_variable_get("@_#{tdl_key}_") || default_value
203
- rel || TdlSpace::ArrayChain.create(obj:"#{self.inst_name}.#{hdl_key}", belong_to_module: belong_to_module)
211
+ if !dimension || dimension.empty?
212
+ rel || TdlSpace::ArrayChain.create(obj:"#{self.inst_name}.#{hdl_key}", belong_to_module: belong_to_module)
213
+ else
214
+ rel || TdlSpace::ArrayChain.create(obj:"#{self.inst_name}[0].#{hdl_key}", belong_to_module: belong_to_module)
215
+ end
204
216
  end
205
217
 
206
218
  define_method("#{tdl_key}=") do |arg|
@@ -26,6 +26,7 @@ module TdlSpace
26
26
  end
27
27
  new_dla = self.class.new(@belong_to_module)
28
28
  new_dla.chain = @chain + a
29
+ new_dla.instance_variable_set("@type",self.instance_variable_get("@type"))
29
30
  new_dla
30
31
  end
31
32
 
@@ -415,7 +415,7 @@ end
415
415
  class SdlInstPortSugar < SdlInstSimplePortSugar
416
416
 
417
417
 
418
- @@ml = [:input,:in,:output,:out,:inout,:mirror,:mirror_out,:master,:slaver,:master_wr,:slaver_wr,:master_rd,:slaver_rd,:master_rd_aux,:mirror_rd,:mirror_wr,:master_wr_aux,:master_wr_aux_no_resp]
418
+ @@ml = [:input,:in,:output,:out,:inout,:mirror,:mirror_out,:master,:slaver,:master_wr,:slaver_wr,:master_rd,:slaver_rd,:master_rd_aux,:mirror_rd,:out_mirror,:mirror_wr,:master_wr_aux,:master_wr_aux_no_resp]
419
419
  # @@ml += ['data_inf_c','data_inf','axi_stream_inf','axi4','axi_inf','axis','data_c']
420
420
  @@ml.each do |e|
421
421
  define_method(e) do |*args|
@@ -65,9 +65,9 @@ class SdlModule
65
65
  if _ref_paths.size == 1
66
66
  # rels[0]
67
67
  elsif _ref_paths.size == 0
68
- raise TdlError.new "#{ele.to_s} Cant find root ref"
68
+ raise TdlError.new "#{self.module_name}.#{ele.to_s} Cant find root ref "
69
69
  else
70
- raise TdlError.new "#{ele.to_s} Find multi root refs \n#{_ref_paths.join("\n")}\n"
70
+ raise TdlError.new "#{self.module_name}.#{ele.to_s} Find multi root refs \n#{_ref_paths.join("\n")}\n"
71
71
  end
72
72
 
73
73
 
@@ -324,6 +324,11 @@ end
324
324
  class TopModule
325
325
  public
326
326
  def add_test_unit(*args)
327
+ args.each do |e|
328
+ unless e.is_a? ItegrationTestUnit
329
+ raise TdlError.new(" add_test_unit args<#{e}> must be ItegrationTestUnit ")
330
+ end
331
+ end
327
332
  @_test_unit_collect_ ||= []
328
333
  @_test_unit_collect_ = @_test_unit_collect_ + args
329
334
  end
@@ -336,7 +341,7 @@ class TopModule
336
341
  ## 例化需要的itgt test unit
337
342
  # ItegrationVerb.test_unit_inst
338
343
  ItegrationVerb.test_unit_inst do |name|
339
- args.include? name.to_s
344
+ args.include? name
340
345
  end
341
346
 
342
347
  self.techbench.instance_exec(args) do |args|
@@ -347,24 +352,15 @@ class TopModule
347
352
  logic[args.size] - 'unit_pass_d'
348
353
 
349
354
  nqq = args.size <= 1
350
- args.each do |tu|
351
- if tu.is_a? SdlModule
352
- _inst_name_ = tu.module_name
353
- else
354
- _inst_name_ = tu.to_s
355
- end
356
-
357
- # puts _inst_name_
358
- # puts SdlModule.call_module(_inst_name_).class
359
- tu_inst = Instance(_inst_name_,"test_unit_#{index}") do |h|
355
+ args.each do |itgt_testunit|
356
+
357
+ tu_inst = Instance("tu_#{itgt_testunit.itgt}_#{itgt_testunit.name}","test_unit_#{index}") do |h|
360
358
  h.input.from_up_pass (nqq ? unit_pass_u : unit_pass_u[index])
361
359
  h.output.logic.to_down_pass (nqq ? unit_pass_d : unit_pass_d[index])
362
360
  end
363
361
 
364
362
  tu_inst.origin.be_instanced_by_sim
365
- # TdlTestUnit.collect_unit tu_inst
366
- # TopModule.current.test_unit.collect_unit tu_inst
367
-
363
+
368
364
  ## 添加dve wave 信号
369
365
  # TopModule.current.test_unit.dve_wave(name: _inst_name_, signals: tu_inst.origin.dve_wave_signals )
370
366
 
data/lib/tdl/tdl.rb CHANGED
@@ -90,6 +90,7 @@ require_relative "./exlib/constraints"
90
90
  require_relative "./exlib/constraints_verb"
91
91
  require_relative "./exlib/itegration"
92
92
  require_relative "./exlib/itegration_verb"
93
+ require_relative "./exlib/itegration_test_unit"
93
94
  require_relative "./exlib/parse_argv"
94
95
  # require_relative "./tdlmodule_ex"
95
96
  # require_relative "./SDL/path_lib" # require sdlmodule
metadata CHANGED
@@ -1,14 +1,14 @@
1
1
  --- !ruby/object:Gem::Specification
2
2
  name: axi_tdl
3
3
  version: !ruby/object:Gem::Version
4
- version: 0.1.20
4
+ version: 0.2.0
5
5
  platform: ruby
6
6
  authors:
7
7
  - Cook.Darwin
8
8
  autorequire:
9
9
  bindir: exe
10
10
  cert_chain: []
11
- date: 2021-09-30 00:00:00.000000000 Z
11
+ date: 2022-07-17 00:00:00.000000000 Z
12
12
  dependencies:
13
13
  - !ruby/object:Gem::Dependency
14
14
  name: rake
@@ -77,12 +77,14 @@ files:
77
77
  - lib/axi/AXI4/axi4_direct.sv
78
78
  - lib/axi/AXI4/axi4_direct_A1.sv
79
79
  - lib/axi/AXI4/axi4_direct_B1.sv
80
+ - lib/axi/AXI4/axi4_direct_algin_addr_step.sv
80
81
  - lib/axi/AXI4/axi4_direct_verb.sv
81
82
  - lib/axi/AXI4/axi4_direct_verc.sv
82
83
  - lib/axi/AXI4/axi4_dpram_cache.rb
83
84
  - lib/axi/AXI4/axi4_dpram_cache.sv
84
85
  - lib/axi/AXI4/axi4_long_to_axi4_wide.sv
85
86
  - lib/axi/AXI4/axi4_long_to_axi4_wide_A1.sv
87
+ - lib/axi/AXI4/axi4_long_to_axi4_wide_B1.sv
86
88
  - lib/axi/AXI4/axi4_long_to_axi4_wide_track.sv
87
89
  - lib/axi/AXI4/axi4_long_to_axi4_wide_verb.sv
88
90
  - lib/axi/AXI4/axi4_pipe/axi4_pipe.sv
@@ -130,6 +132,7 @@ files:
130
132
  - lib/axi/AXI4/odata_pool_axi4_A2.sv
131
133
  - lib/axi/AXI4/odata_pool_axi4_A3.sv
132
134
  - lib/axi/AXI4/packet_fifo/axi4_packet_fifo.sv
135
+ - lib/axi/AXI4/packet_fifo/axi4_packet_fifo_verb.sv
133
136
  - lib/axi/AXI4/packet_fifo/axi4_rd_packet_fifo.sv
134
137
  - lib/axi/AXI4/packet_fifo/axi4_wr_packet_fifo.sv
135
138
  - lib/axi/AXI4/packet_merge/axi4_merge.sv
@@ -153,6 +156,7 @@ files:
153
156
  - lib/axi/AXI4/width_convert/axi4_data_combin_aflag_pipe_A1.sv
154
157
  - lib/axi/AXI4/width_convert/axi4_data_convert.sv
155
158
  - lib/axi/AXI4/width_convert/axi4_data_convert_A1.sv
159
+ - lib/axi/AXI4/width_convert/axi4_data_convert_verb.sv
156
160
  - lib/axi/AXI4/width_convert/data_combin.sv
157
161
  - lib/axi/AXI4/width_convert/data_combin.sv.bak
158
162
  - lib/axi/AXI4/width_convert/data_destruct.sv
@@ -201,6 +205,7 @@ files:
201
205
  - lib/axi/AXI_stream/axi_stream_interconnect_M2S_A1.sv
202
206
  - lib/axi/AXI_stream/axi_stream_interconnect_M2S_A2.sv
203
207
  - lib/axi/AXI_stream/axi_stream_interconnect_M2S_bind_tuser.sv
208
+ - lib/axi/AXI_stream/axi_stream_interconnect_M2S_cpVCS.sv
204
209
  - lib/axi/AXI_stream/axi_stream_interconnect_M2S_noaddr.sv
205
210
  - lib/axi/AXI_stream/axi_stream_interconnect_M2S_with_addr.sv
206
211
  - lib/axi/AXI_stream/axi_stream_interconnect_S2M.sv
@@ -478,6 +483,8 @@ files:
478
483
  - lib/axi/interface_define/lite_inf2_to_inf.sv
479
484
  - lib/axi/interface_define/xilinx_axi4_to_axi4.sv
480
485
  - lib/axi/interface_define/xilinx_lite_to_lite.sv
486
+ - lib/axi/macro/RTL/define_macro.sv
487
+ - lib/axi/macro/SIM/define_macro.sv
481
488
  - lib/axi/macro/axil_macro.sv
482
489
  - lib/axi/macro/bak/axi4_base_files_add_to_vivado.tcl
483
490
  - lib/axi/macro/bak/axi_macro.sv
@@ -1250,6 +1257,7 @@ files:
1250
1257
  - lib/tdl/examples/9_itegration/clock_manage/simple_clock.rb
1251
1258
  - lib/tdl/examples/9_itegration/clock_manage/simple_clock.sv
1252
1259
  - lib/tdl/examples/9_itegration/clock_manage/test_clock_bb.sv
1260
+ - lib/tdl/examples/9_itegration/clock_manage/tu_ClockManage_test_clock_bb.sv
1253
1261
  - lib/tdl/examples/9_itegration/dve.tcl
1254
1262
  - lib/tdl/examples/9_itegration/pins.yml
1255
1263
  - lib/tdl/examples/9_itegration/tb_test_top.sv
@@ -1278,6 +1286,7 @@ files:
1278
1286
  - lib/tdl/exlib/integral_test/reset_itest.rb
1279
1287
  - lib/tdl/exlib/integral_test/simple_logic_itest.rb
1280
1288
  - lib/tdl/exlib/itegration.rb
1289
+ - lib/tdl/exlib/itegration_test_unit.rb
1281
1290
  - lib/tdl/exlib/itegration_verb.rb
1282
1291
  - lib/tdl/exlib/logic_verify.rb
1283
1292
  - lib/tdl/exlib/parse_argv.rb