axi_tdl 0.1.20 → 0.2.0

data/lib/tdl/examples/8_top_module/dve.tcl

@@ -13,8 +13,6 @@ gui_set_time_units 1ps
 ## ==== [add_signal] ===== ##
 
 
-
-
 ## 创建波形窗口
 if {![info exists useOldWindow]} { 
     set useOldWindow true
@@ -44,8 +42,6 @@ gui_wv_zoom_timerange -id ${Wave.3} 0 1000000000
 ## === [add_signal_wave] === ##
 
 
-
-
 gui_seek_criteria -id ${Wave.3} {Any Edge}
 
 
@@ -63,8 +59,6 @@ gui_list_set_filter -id ${Wave.3} -text {*}
 ## === [add_bar] === ##
 
 
-
-
 gui_marker_move -id ${Wave.3} {C1} 560248001
 gui_view_scroll -id ${Wave.3} -vertical -set 35
 gui_show_grid -id ${Wave.3} -enable false

data/lib/tdl/examples/8_top_module/test_top.sv

@@ -5,7 +5,7 @@ _______________________________________
 descript:
 author : Cook.Darwin
 Version: VERA.0.0
-created: 2021-09-30 21:21:38 +0800
+created: 2022-07-10 11:21:37 +0800
 madified:
 ***********************************************/
 `timescale 1ns/1ps

data/lib/tdl/examples/9_itegration/clock_manage/tu_ClockManage_test_clock_bb.sv

@@ -0,0 +1,35 @@
+/**********************************************
+_______________________________________ 
+___________    Cook Darwin   __________    
+_______________________________________
+descript:
+author : Cook.Darwin
+Version: VERA.0.0
+created: 2022-07-10 11:14:33 +0800
+madified:
+***********************************************/
+`timescale 1ns/1ps
+
+module tu_ClockManage_test_clock_bb(
+    input        from_up_pass,
+    output logic to_down_pass
+);
+
+//==========================================================================
+//-------- define ----------------------------------------------------------
+
+
+//==========================================================================
+//-------- instance --------------------------------------------------------
+
+//==========================================================================
+//-------- expression ------------------------------------------------------
+initial begin
+    to_down_pass = 1'b0;
+    wait(from_up_pass);
+    $root.tb_test_tttop_sim.test_unit_region = "tu_ClockManage_test_clock_bb";
+    $display("--------------- Current test_unit <%0s> --------------------", "tu_ClockManage_test_clock_bb");
+    to_down_pass = 1'b1;
+end
+
+endmodule

data/lib/tdl/examples/9_itegration/tb_test_tttop_sim.sv

@@ -5,7 +5,7 @@ _______________________________________
 descript:
 author : Cook.Darwin
 Version: VERA.0.0
-created: 2021-04-03 14:05:10 +0800
+created: 2022-07-10 11:14:33 +0800
 madified:
 ***********************************************/
 `timescale 1ns/1ps
@@ -23,7 +23,7 @@ logic unit_pass_d;
 test_tttop_sim rtl_top(
 /* input clock */.global_sys_clk (gl_clk )
 );
-test_clock_bb test_unit_0(
+tu_ClockManage_test_clock_bb test_unit_0(
 /* input  */.from_up_pass (unit_pass_u ),
 /* output */.to_down_pass (unit_pass_d )
 );

data/lib/tdl/examples/9_itegration/test_tttop.sv

@@ -1,9 +1,40 @@
-
+/**********************************************
+_______________________________________ 
+___________    Cook Darwin   __________    
+_______________________________________
+descript:
+author : Cook.Darwin
+Version: VERA.0.0
+created: 2022-07-10 11:21:57 +0800
+madified:
+***********************************************/
 `timescale 1ns/1ps
-module test_tttop();
-initial begin
-    #(1us);
-    $warning("Check TopModule.sim,please!!!");
-    $stop;
-end
+
+module test_tttop (
+    input global_sys_clk
+);
+
+//==========================================================================
+//-------- define ----------------------------------------------------------
+logic  clock_100M;
+logic  rstn_100M;
+axi_stream_inf #(.DSIZE(16),.FreqM(100),.USIZE(1)) x_origin_inf (.aclk(clock_100M),.aresetn(rstn_100M),.aclken(1'b1)) ;
+//==========================================================================
+//-------- instance --------------------------------------------------------
+simple_clock simple_clock_inst(
+/* input clock  */.sys_clk (global_sys_clk ),
+/* output clock */.clock   (clock_100M     ),
+/* output reset */.rst_n   (rstn_100M      )
+);
+a_test_md a_test_md_inst(
+/* input clock           */.clock      (clock_100M   ),
+/* input reset           */.rst        (~rstn_100M   ),
+/* axi_stream_inf.master */.origin_inf (x_origin_inf )
+);
+//==========================================================================
+//-------- expression ------------------------------------------------------
+assign x_origin_inf.axis_tvalid = 1'b0;
+assign x_origin_inf.axis_tdata = '0;
+assign x_origin_inf.axis_tlast = 1'b0;
+
 endmodule

data/lib/tdl/examples/9_itegration/test_tttop_sim.sv

@@ -1,40 +1,9 @@
-/**********************************************
-_______________________________________ 
-___________    Cook Darwin   __________    
-_______________________________________
-descript:
-author : Cook.Darwin
-Version: VERA.0.0
-created: 2021-09-30 21:21:22 +0800
-madified:
-***********************************************/
-`timescale 1ns/1ps
-
-module test_tttop_sim (
-    input global_sys_clk
-);
-
-//==========================================================================
-//-------- define ----------------------------------------------------------
-logic  clock_100M;
-logic  rstn_100M;
-axi_stream_inf #(.DSIZE(16),.FreqM(100),.USIZE(1)) x_origin_inf (.aclk(clock_100M),.aresetn(rstn_100M),.aclken(1'b1)) ;
-//==========================================================================
-//-------- instance --------------------------------------------------------
-simple_clock simple_clock_inst(
-/* input clock  */.sys_clk (global_sys_clk ),
-/* output clock */.clock   (clock_100M     ),
-/* output reset */.rst_n   (rstn_100M      )
-);
-a_test_md a_test_md_inst(
-/* input clock           */.clock      (clock_100M   ),
-/* input reset           */.rst        (~rstn_100M   ),
-/* axi_stream_inf.master */.origin_inf (x_origin_inf )
-);
-//==========================================================================
-//-------- expression ------------------------------------------------------
-assign x_origin_inf.axis_tvalid = 1'b0;
-assign x_origin_inf.axis_tdata = '0;
-assign x_origin_inf.axis_tlast = 1'b0;
 
+`timescale 1ns/1ps
+module test_tttop_sim();
+initial begin
+    #(1us);
+    $warning("Check TopModule.sim,please!!!");
+    $stop;
+end
 endmodule

data/lib/tdl/examples/9_itegration/top.rb

@@ -8,5 +8,5 @@ TopModule.test_tttop(__dir__) do
     add_itegration('ClockManage',pins_map: :CM)
     add_itegration('ABlock')
 
-    add_test_unit('test_clock_bb')
+    add_test_unit(ClockManage.test_clock_bb)
 end

data/lib/tdl/exlib/itegration_test_unit.rb

@@ -0,0 +1,13 @@
+
+class ItegrationTestUnit 
+    "
+    test unit in Itgt
+    "
+    attr_accessor :path,:block,:itgt,:name
+    def initialize(name: 'tmp',path: '',block: Proc.new , itgt: nil )
+        @path = path 
+        @block = block 
+        @itgt = itgt
+        @name = name
+    end
+end

data/lib/tdl/exlib/itegration_verb.rb

@@ -470,17 +470,18 @@ class ItegrationVerb
             return 
         end
 
-        blocks.each do |b|
+        blocks.each do |key,valueItgtTU|
             # @top_module.techbench.instance_exec(self,&b.clone)
-            sdlm = TestUnitModule.new(name: b[0],out_sv_path: b[1])
+            sdlm = TestUnitModule.new(name: key ,out_sv_path: valueItgtTU.path )
             $_implicit_curr_itgt_.with_none_itgt do 
                 sdlm.input - "from_up_pass"
                 sdlm.output.logic - "to_down_pass"
             end
-            sdlm.instance_exec(self,&b[2])
+            sdlm.instance_exec(self,&valueItgtTU.block)
 
-            if b[1] && File.exist?(b[1])
+            if valueItgtTU.path && File.exist?(valueItgtTU.path)
                 sdlm.gen_sv_module
+                Tdl.Puts "[warnning]   #{key} path error !!!"
             else 
                 sdlm.origin_sv = true 
             end
@@ -491,27 +492,26 @@ class ItegrationVerb
     end
 
     def self.test_unit_inst(&filter_block)
-        # blocks = self.instance_variable_get("@_inst_test_unit_blocks_")
-        # blocks = instance_variable_get("@_inst_test_unit_blocks_") || []
-        blocks = @@_inst_test_unit_blocks_ || []
+        blocks = @@_inst_test_unit_blocks_ || {}
         return unless blocks
         return if blocks.empty?
         return unless TopModule.sim
 
         ItegrationVerb.curr_itgt_push nil
 
-        blocks.each do |b|
+        blocks.each do |key,valueItgtTU|
             # @top_module.techbench.instance_exec(self,&b.clone)
-            if !(block_given?) || filter_block.call(b[0])
-                sdlm = TestUnitModule.new(name: b[0],out_sv_path: b[1])
+            if !(block_given?) || filter_block.call(valueItgtTU)
+                sdlm = TestUnitModule.new(name: "tu_#{key}",out_sv_path: valueItgtTU.path)
                 $_implicit_curr_itgt_.with_none_itgt do 
                     sdlm.input - "from_up_pass"
                     sdlm.output.logic - "to_down_pass"
                 end
-                sdlm.instance_exec(nil,&b[2])
+                sdlm.instance_exec(nil,&valueItgtTU.block)
 
-                if b[1] && File.exist?(b[1])
+                if valueItgtTU.path && File.exist?(valueItgtTU.path)
                     sdlm.gen_sv_module
+                    Tdl.Puts "[warnning]   #{key} path error !!!"
                 else 
                     sdlm.origin_sv = true 
                 end
@@ -776,12 +776,17 @@ class ItegrationVerb
     end
 
     ## 添加测试用例
-    @@_inst_test_unit_blocks_ = []
+    @@_inst_test_unit_blocks_ = {}
     def self.def_test_unit(name,path,&block)
-        # @@_inst_test_unit_blocks_ = instance_variable_get("@_inst_test_unit_blocks_")
-        @@_inst_test_unit_blocks_ ||= []
-        @@_inst_test_unit_blocks_ << [name.to_s, path, block]
-        # instance_variable_set("@_inst_test_unit_blocks_",_inst_test_unit_blocks_)
+        @@_inst_test_unit_blocks_ ||= {}
+        # @@_inst_test_unit_blocks_ << [name.to_s, path, block]
+        itgt_testunit = ItegrationTestUnit.new(name:name,path:path, block: block, itgt: self)
+        @@_inst_test_unit_blocks_["#{self}_#{name.to_s}"] = itgt_testunit
+
+        self.define_singleton_method(name.to_s) do 
+            itgt_testunit
+        end
+
         @@_inst_test_unit_blocks_
     end
 

data/lib/tdl/rebuild_ele/ele_base.rb

@@ -128,7 +128,11 @@ module TdlSpace
                 define_method(tdl_key) do 
                     rel = self.instance_variable_get("@_#{tdl_key}_")
                     unless rel 
-                        TdlSpace::ArrayChain.create(obj: "#{inst_name}.#{hdl_key}".to_nq, belong_to_module: belong_to_module)
+                        if !dimension || dimension.empty?
+                            TdlSpace::ArrayChain.create(obj: "#{inst_name}.#{hdl_key}".to_nq, belong_to_module: belong_to_module)
+                        else 
+                            TdlSpace::ArrayChain.create(obj: "#{inst_name}[0].#{hdl_key}".to_nq, belong_to_module: belong_to_module)
+                        end
                     else 
                         rel 
                     end
@@ -171,7 +175,11 @@ module TdlSpace
              self.class_exec(tdl_key) do |tdl_key|
                 define_method('reset') do 
                     rel = self.instance_variable_get("@_#{tdl_key}_")
-                    rel || TdlSpace::ArrayChain.create(obj:"#{self.inst_name}.#{hdl_key}", belong_to_module: belong_to_module)
+                    if !dimension || dimension.empty?
+                        rel || TdlSpace::ArrayChain.create(obj:"#{self.inst_name}.#{hdl_key}", belong_to_module: belong_to_module)
+                    else 
+                        rel || TdlSpace::ArrayChain.create(obj:"#{self.inst_name}[0].#{hdl_key}", belong_to_module: belong_to_module)
+                    end
                 end
 
                 define_method("reset=") do |arg|
@@ -200,7 +208,11 @@ module TdlSpace
             self.class_exec(tdl_key) do |tdl_key|
                 define_method(tdl_key) do 
                     rel = self.instance_variable_get("@_#{tdl_key}_") || default_value
-                    rel || TdlSpace::ArrayChain.create(obj:"#{self.inst_name}.#{hdl_key}", belong_to_module: belong_to_module)
+                    if !dimension || dimension.empty?
+                        rel || TdlSpace::ArrayChain.create(obj:"#{self.inst_name}.#{hdl_key}", belong_to_module: belong_to_module)
+                    else 
+                        rel || TdlSpace::ArrayChain.create(obj:"#{self.inst_name}[0].#{hdl_key}", belong_to_module: belong_to_module)
+                    end
                 end
 
                 define_method("#{tdl_key}=") do |arg|

data/lib/tdl/sdlmodule/sdlmodule_arraychain.rb

@@ -26,6 +26,7 @@ module TdlSpace
             end
             new_dla = self.class.new(@belong_to_module)
             new_dla.chain = @chain + a
+            new_dla.instance_variable_set("@type",self.instance_variable_get("@type"))
             new_dla
         end
 

data/lib/tdl/sdlmodule/sdlmodule_instance.rb

@@ -415,7 +415,7 @@ end
 class SdlInstPortSugar < SdlInstSimplePortSugar
     
 
-    @@ml = [:input,:in,:output,:out,:inout,:mirror,:mirror_out,:master,:slaver,:master_wr,:slaver_wr,:master_rd,:slaver_rd,:master_rd_aux,:mirror_rd,:mirror_wr,:master_wr_aux,:master_wr_aux_no_resp]
+    @@ml = [:input,:in,:output,:out,:inout,:mirror,:mirror_out,:master,:slaver,:master_wr,:slaver_wr,:master_rd,:slaver_rd,:master_rd_aux,:mirror_rd,:out_mirror,:mirror_wr,:master_wr_aux,:master_wr_aux_no_resp]
     # @@ml += ['data_inf_c','data_inf','axi_stream_inf','axi4','axi_inf','axis','data_c']
     @@ml.each do |e|
         define_method(e) do |*args|

data/lib/tdl/sdlmodule/test_unit_module.rb

@@ -65,9 +65,9 @@ class SdlModule
                 if _ref_paths.size == 1
                     # rels[0]
                 elsif _ref_paths.size == 0
-                    raise TdlError.new "#{ele.to_s} Cant find root ref"
+                    raise TdlError.new "#{self.module_name}.#{ele.to_s} Cant find root ref "
                 else
-                    raise TdlError.new "#{ele.to_s} Find multi root refs \n#{_ref_paths.join("\n")}\n"
+                    raise TdlError.new "#{self.module_name}.#{ele.to_s} Find multi root refs \n#{_ref_paths.join("\n")}\n"
                 end
 
 
@@ -324,6 +324,11 @@ end
 class TopModule
     public 
     def add_test_unit(*args)
+        args.each do |e|
+            unless e.is_a? ItegrationTestUnit
+                raise TdlError.new(" add_test_unit args<#{e}> must be ItegrationTestUnit ")
+            end
+        end
         @_test_unit_collect_ ||= []
         @_test_unit_collect_ = @_test_unit_collect_ + args
     end
@@ -336,7 +341,7 @@ class TopModule
         ## 例化需要的itgt test unit
         # ItegrationVerb.test_unit_inst
         ItegrationVerb.test_unit_inst do |name|
-            args.include? name.to_s
+            args.include? name
         end
 
         self.techbench.instance_exec(args) do |args|
@@ -347,24 +352,15 @@ class TopModule
             logic[args.size]    - 'unit_pass_d'
 
             nqq  = args.size <= 1
-            args.each do |tu|
-                if tu.is_a? SdlModule
-                    _inst_name_ = tu.module_name
-                else
-                    _inst_name_ = tu.to_s 
-                end
-
-                # puts _inst_name_
-                # puts SdlModule.call_module(_inst_name_).class
-                tu_inst = Instance(_inst_name_,"test_unit_#{index}") do |h|
+            args.each do |itgt_testunit|
+                
+                tu_inst = Instance("tu_#{itgt_testunit.itgt}_#{itgt_testunit.name}","test_unit_#{index}") do |h|
                     h.input.from_up_pass            (nqq ? unit_pass_u : unit_pass_u[index])
                     h.output.logic.to_down_pass     (nqq ? unit_pass_d : unit_pass_d[index])
                 end
 
                 tu_inst.origin.be_instanced_by_sim
-                # TdlTestUnit.collect_unit tu_inst
-                # TopModule.current.test_unit.collect_unit tu_inst
-
+    
                 ## 添加dve wave 信号
                 # TopModule.current.test_unit.dve_wave(name: _inst_name_, signals: tu_inst.origin.dve_wave_signals )
 

data/lib/tdl/tdl.rb

@@ -90,6 +90,7 @@ require_relative "./exlib/constraints"
 require_relative "./exlib/constraints_verb"
 require_relative "./exlib/itegration"
 require_relative "./exlib/itegration_verb"
+require_relative "./exlib/itegration_test_unit"
 require_relative "./exlib/parse_argv"
 # require_relative "./tdlmodule_ex"
 # require_relative "./SDL/path_lib"     # require sdlmodule

metadata

@@ -1,14 +1,14 @@
 --- !ruby/object:Gem::Specification
 name: axi_tdl
 version: !ruby/object:Gem::Version
-  version: 0.1.20
+  version: 0.2.0
 platform: ruby
 authors:
 - Cook.Darwin
 autorequire: 
 bindir: exe
 cert_chain: []
-date: 2021-09-30 00:00:00.000000000 Z
+date: 2022-07-17 00:00:00.000000000 Z
 dependencies:
 - !ruby/object:Gem::Dependency
   name: rake
@@ -77,12 +77,14 @@ files:
 - lib/axi/AXI4/axi4_direct.sv
 - lib/axi/AXI4/axi4_direct_A1.sv
 - lib/axi/AXI4/axi4_direct_B1.sv
+- lib/axi/AXI4/axi4_direct_algin_addr_step.sv
 - lib/axi/AXI4/axi4_direct_verb.sv
 - lib/axi/AXI4/axi4_direct_verc.sv
 - lib/axi/AXI4/axi4_dpram_cache.rb
 - lib/axi/AXI4/axi4_dpram_cache.sv
 - lib/axi/AXI4/axi4_long_to_axi4_wide.sv
 - lib/axi/AXI4/axi4_long_to_axi4_wide_A1.sv
+- lib/axi/AXI4/axi4_long_to_axi4_wide_B1.sv
 - lib/axi/AXI4/axi4_long_to_axi4_wide_track.sv
 - lib/axi/AXI4/axi4_long_to_axi4_wide_verb.sv
 - lib/axi/AXI4/axi4_pipe/axi4_pipe.sv
@@ -130,6 +132,7 @@ files:
 - lib/axi/AXI4/odata_pool_axi4_A2.sv
 - lib/axi/AXI4/odata_pool_axi4_A3.sv
 - lib/axi/AXI4/packet_fifo/axi4_packet_fifo.sv
+- lib/axi/AXI4/packet_fifo/axi4_packet_fifo_verb.sv
 - lib/axi/AXI4/packet_fifo/axi4_rd_packet_fifo.sv
 - lib/axi/AXI4/packet_fifo/axi4_wr_packet_fifo.sv
 - lib/axi/AXI4/packet_merge/axi4_merge.sv
@@ -153,6 +156,7 @@ files:
 - lib/axi/AXI4/width_convert/axi4_data_combin_aflag_pipe_A1.sv
 - lib/axi/AXI4/width_convert/axi4_data_convert.sv
 - lib/axi/AXI4/width_convert/axi4_data_convert_A1.sv
+- lib/axi/AXI4/width_convert/axi4_data_convert_verb.sv
 - lib/axi/AXI4/width_convert/data_combin.sv
 - lib/axi/AXI4/width_convert/data_combin.sv.bak
 - lib/axi/AXI4/width_convert/data_destruct.sv
@@ -201,6 +205,7 @@ files:
 - lib/axi/AXI_stream/axi_stream_interconnect_M2S_A1.sv
 - lib/axi/AXI_stream/axi_stream_interconnect_M2S_A2.sv
 - lib/axi/AXI_stream/axi_stream_interconnect_M2S_bind_tuser.sv
+- lib/axi/AXI_stream/axi_stream_interconnect_M2S_cpVCS.sv
 - lib/axi/AXI_stream/axi_stream_interconnect_M2S_noaddr.sv
 - lib/axi/AXI_stream/axi_stream_interconnect_M2S_with_addr.sv
 - lib/axi/AXI_stream/axi_stream_interconnect_S2M.sv
@@ -478,6 +483,8 @@ files:
 - lib/axi/interface_define/lite_inf2_to_inf.sv
 - lib/axi/interface_define/xilinx_axi4_to_axi4.sv
 - lib/axi/interface_define/xilinx_lite_to_lite.sv
+- lib/axi/macro/RTL/define_macro.sv
+- lib/axi/macro/SIM/define_macro.sv
 - lib/axi/macro/axil_macro.sv
 - lib/axi/macro/bak/axi4_base_files_add_to_vivado.tcl
 - lib/axi/macro/bak/axi_macro.sv
@@ -1250,6 +1257,7 @@ files:
 - lib/tdl/examples/9_itegration/clock_manage/simple_clock.rb
 - lib/tdl/examples/9_itegration/clock_manage/simple_clock.sv
 - lib/tdl/examples/9_itegration/clock_manage/test_clock_bb.sv
+- lib/tdl/examples/9_itegration/clock_manage/tu_ClockManage_test_clock_bb.sv
 - lib/tdl/examples/9_itegration/dve.tcl
 - lib/tdl/examples/9_itegration/pins.yml
 - lib/tdl/examples/9_itegration/tb_test_top.sv
@@ -1278,6 +1286,7 @@ files:
 - lib/tdl/exlib/integral_test/reset_itest.rb
 - lib/tdl/exlib/integral_test/simple_logic_itest.rb
 - lib/tdl/exlib/itegration.rb
+- lib/tdl/exlib/itegration_test_unit.rb
 - lib/tdl/exlib/itegration_verb.rb
 - lib/tdl/exlib/logic_verify.rb
 - lib/tdl/exlib/parse_argv.rb