axi_tdl 0.1.20 → 0.2.0
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- checksums.yaml +4 -4
- data/lib/axi/AXI4/axi4_direct_algin_addr_step.sv +223 -0
- data/lib/axi/AXI4/axi4_direct_verc.sv +54 -5
- data/lib/axi/AXI4/axi4_long_to_axi4_wide_B1.sv +146 -0
- data/lib/axi/AXI4/packet_fifo/axi4_packet_fifo_verb.sv +62 -0
- data/lib/axi/AXI4/packet_fifo/axi4_wr_packet_fifo.sv +4 -3
- data/lib/axi/AXI4/wide_axis_to_axi4_wr.sv +1 -1
- data/lib/axi/AXI4/width_convert/axi4_data_convert_verb.sv +280 -0
- data/lib/axi/AXI_stream/axi_stream_interconnect_M2S_cpVCS.sv +80 -0
- data/lib/axi/AXI_stream/axi_stream_split_channel.sv +20 -20
- data/lib/axi/AXI_stream/axis_append_A1.sv +15 -2
- data/lib/axi/AXI_stream/axis_uncompress_verb.sv +9 -9
- data/lib/axi/AXI_stream/parse_big_field_table_verb.sv +3 -2
- data/lib/axi/data_interface/data_inf_c/data_c_pipe_sync_seam.sv +10 -10
- data/lib/axi/data_interface/data_inf_c/data_c_scaler_A1.sv +2 -1
- data/lib/axi/interface_define/axi_inf.sv +1 -1
- data/lib/axi/macro/RTL/define_macro.sv +210 -0
- data/lib/axi/macro/SIM/define_macro.sv +194 -0
- data/lib/axi_tdl/version.rb +1 -1
- data/lib/tdl/auto_script/import_sdl.rb +3 -0
- data/lib/tdl/axi4/axi4_interconnect_verb.rb +76 -10
- data/lib/tdl/examples/11_test_unit/exp_test_unit.sv +7 -33
- data/lib/tdl/examples/11_test_unit/tb_exp_test_unit.sv +1 -1
- data/lib/tdl/examples/11_test_unit/tb_exp_test_unit_sim.sv +3 -14
- data/lib/tdl/examples/11_test_unit/tu0.sv +1 -1
- data/lib/tdl/examples/2_hdl_class/tmp/test_module_var.sv +2 -2
- data/lib/tdl/examples/2_hdl_class/tmp/test_vcs_string.sv +1 -1
- data/lib/tdl/examples/8_top_module/dve.tcl +0 -6
- data/lib/tdl/examples/8_top_module/test_top.sv +1 -1
- data/lib/tdl/examples/9_itegration/clock_manage/tu_ClockManage_test_clock_bb.sv +35 -0
- data/lib/tdl/examples/9_itegration/tb_test_tttop_sim.sv +2 -2
- data/lib/tdl/examples/9_itegration/test_tttop.sv +38 -7
- data/lib/tdl/examples/9_itegration/test_tttop_sim.sv +7 -38
- data/lib/tdl/examples/9_itegration/top.rb +1 -1
- data/lib/tdl/exlib/itegration_test_unit.rb +13 -0
- data/lib/tdl/exlib/itegration_verb.rb +22 -17
- data/lib/tdl/rebuild_ele/ele_base.rb +15 -3
- data/lib/tdl/sdlmodule/sdlmodule_arraychain.rb +1 -0
- data/lib/tdl/sdlmodule/sdlmodule_instance.rb +1 -1
- data/lib/tdl/sdlmodule/test_unit_module.rb +12 -16
- data/lib/tdl/tdl.rb +1 -0
- metadata +11 -2
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`define CheckParamPair(X,Y)\
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initial begin\
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Check_Param_Pair(X,Y,`__FILE__,`__LINE__,`"X != Y`");\
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end
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//---- TAP FLAG -----------------------------------
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// `define
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`define VIVADO_ENV
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`define parameter_string parameter
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`define parameter_longstring(num=63) parameter
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// VCS AXI4 comptable macro
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// `define VCS_AXI4_CPT(origin_axi4,origin_modport,to_modport,flag)\
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// axi_inf #(\
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// .IDSIZE (origin_axi4.IDSIZE),\
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// .ASIZE (origin_axi4.ASIZE ),\
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// .LSIZE (origin_axi4.LSIZE ),\
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// .DSIZE (origin_axi4.DSIZE ),\
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// .MODE (origin_axi4.MODE ),\
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// .ADDR_STEP (origin_axi4.ADDR_STEP),\
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// .FreqM (origin_axi4.FreqM )\
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// )origin_axi4``_vcs_cpt_``origin_modport``_``to_modport``(\
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// /* input bit */ .axi_aclk (origin_axi4.axi_aclk ),\
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// /* input bit */ .axi_aresetn (origin_axi4.axi_aresetn )\
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// );\
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// vcs_axi4_comptable #(\
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// .ORIGIN (`"origin_modport`"),\
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// .TO (`"to_modport`")\
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// )origin_axi4``_vcs_axi4_comptable_``origin_modport``_``to_modport``_inst(\
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// /* axi_inf */ .origin (origin_axi4 ),\
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// /* axi_inf */ .to (origin_axi4``_vcs_cpt_``origin_modport``_``to_modport``)\
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// );\
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// `define origin_axi4``_vcs_cpt``flag origin_axi4``_vcs_cpt_``origin_modport``_``to_modport``
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`define VCS_AXI4_CPT(origin_axi4,origin_modport,to_modport,flag)\
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`define origin_axi4``_vcs_cpt``flag origin_axi4
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// VCS AXI STREAM comptable macro
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// `define VCS_AXIS_CPT(origin_axis,origin_modport,to_modport,flag)\
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// axi_stream_inf #(\
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// .DSIZE (origin_axis.DSIZE),\
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// .FreqM (origin_axis.FreqM),\
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// .KSIZE (origin_axis.KSIZE),\
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// .CSIZE (origin_axis.CSIZE)\
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// )origin_axis``_vcs_cpt_``origin_modport``_``to_modport``(\
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// /* input bit */ .aclk (origin_axis.aclk ),\
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// /* input bit */ .aresetn (origin_axis.aresetn ),\
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// /* input bit */ .aclken (origin_axis.aclken )\
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// );\
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// vcs_axis_comptable #(\
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// .ORIGIN (`"origin_modport`"),\
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// .TO (`"to_modport`")\
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// )origin_axis``_vcs_axis_comptable_``origin_modport``_``to_modport``_inst(\
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// /* axi_inf */ .origin (origin_axis ),\
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// /* axi_inf */ .to (origin_axis``_vcs_cpt_``origin_modport``_``to_modport`` )\
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// );\
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// `define origin_axis``_vcs_cpt``flag origin_axis``_vcs_cpt_``origin_modport``_``to_modport``
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`define VCS_AXIS_CPT(origin_axis,origin_modport,to_modport,flag)\
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`define origin_axis``_vcs_cpt``flag origin_axis
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// VCS DATA_C comptable macro
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// `define VCS_DATAC_CPT(origin_inf,origin_modport,to_modport,flag)\
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// data_inf_c #(\
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// .DSIZE (origin_inf.DSIZE),\
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// .FreqM (origin_inf.FreqM)\
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// )origin_inf``_vcs_cpt_``origin_modport``_``to_modport``(\
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// /* input bit */ .clock (origin_inf.clock ),\
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// /* input bit */ .rst_n (origin_inf.rst_n )\
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// );\
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// vcs_data_c_comptable #(\
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// .ORIGIN (`"origin_modport`"),\
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// .TO (`"to_modport`")\
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// )origin_inf``_vcs_axis_comptable_``origin_modport``_``to_modport``_inst(\
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// /* data_inf_c */ .origin (origin_inf ),\
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// /* data_inf_c */ .to (origin_inf``_vcs_cpt_``origin_modport``_``to_modport`` )\
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// );\
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// `define origin_inf``_vcs_cpt``flag origin_inf``_vcs_cpt_``origin_modport``_``to_modport``
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`define VCS_DATAC_CPT(origin_inf,origin_modport,to_modport,flag)\
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`define origin_inf``_vcs_cpt``flag origin_inf
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// VCS AXI4 comptable macro
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// Lock TO
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// `define VCS_AXI4_CPT_LT(inf,origin_modport,to_modport,flag)\
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// axi_inf #(\
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// .IDSIZE (inf.IDSIZE),\
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// .ASIZE (inf.ASIZE ),\
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// .LSIZE (inf.LSIZE ),\
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// .DSIZE (inf.DSIZE ),\
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// .MODE (inf.MODE ),\
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// .ADDR_STEP (inf.ADDR_STEP),\
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// .FreqM (inf.FreqM )\
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// )inf``_vcs_cpt_``origin_modport``_``to_modport``(\
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// /* input bit */ .axi_aclk (inf.axi_aclk ),\
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// /* input bit */ .axi_aresetn (inf.axi_aresetn )\
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// );\
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// vcs_axi4_comptable #(\
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// .ORIGIN (`"origin_modport`"),\
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// .TO (`"to_modport`")\
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// )inf``_vcs_axi4_comptable_``origin_modport``_``to_modport``_inst(\
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// /* axi_inf */ .origin (inf``_vcs_cpt_``origin_modport``_``to_modport``),\
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// /* axi_inf */ .to (inf)\
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// );\
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// `define inf``_vcs_cpt``flag inf``_vcs_cpt_``origin_modport``_``to_modport``
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`define VCS_AXI4_CPT_LT(inf,origin_modport,to_modport,flag)\
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`define inf``_vcs_cpt``flag inf
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// `define VCS_AXI4_CPT(origin_axi4,origin_modport,to_modport)\
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// `define origin_axi4``_vcs_cpt origin_axi4
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// VCS AXI STREAM comptable macro
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// Lock to
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// `define VCS_AXIS_CPT_LT(inf,origin_modport,to_modport,flag)\
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// axi_stream_inf #(\
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// .DSIZE (inf.DSIZE),\
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// .FreqM (inf.FreqM),\
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// .KSIZE (inf.KSIZE),\
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// .CSIZE (inf.CSIZE)\
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// )inf``_vcs_cpt_``origin_modport``_``to_modport``(\
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// /* input bit */ .aclk (inf.aclk ),\
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// /* input bit */ .aresetn (inf.aresetn ),\
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// /* input bit */ .aclken (inf.aclken )\
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// );\
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// vcs_axis_comptable #(\
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// .ORIGIN (`"origin_modport`"),\
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// .TO (`"to_modport`")\
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// )inf``_vcs_axis_comptable_``origin_modport``_``to_modport``_inst(\
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// /* axi_inf */ .origin (inf``_vcs_cpt_``origin_modport``_``to_modport`` ),\
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// /* axi_inf */ .to (inf )\
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// );\
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// `define inf``_vcs_cpt``flag inf``_vcs_cpt_``origin_modport``_``to_modport``
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`define VCS_AXIS_CPT_LT(inf,origin_modport,to_modport,flag)\
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`define inf``_vcs_cpt``flag inf
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// VCS DATA_C comptable macro
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// Lock to
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// `define VCS_DATAC_CPT_LT(inf,origin_modport,to_modport,flag)\
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// data_inf_c #(\
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// .DSIZE (inf.DSIZE),\
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// .FreqM (inf.FreqM)\
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// )inf``_vcs_cpt_``origin_modport``_``to_modport``(\
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// /* input bit */ .clock (inf.clock ),\
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// /* input bit */ .rst_n (inf.rst_n )\
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// );\
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// vcs_data_c_comptable #(\
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// .ORIGIN (`"origin_modport`"),\
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// .TO (`"to_modport`")\
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// )inf``_vcs_axis_comptable_``origin_modport``_``to_modport``_inst(\
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// /* data_inf_c */ .origin (inf``_vcs_cpt_``origin_modport``_``to_modport`` ),\
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// /* data_inf_c */ .to (inf )\
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// );\
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// `define inf``_vcs_cpt``flag inf``_vcs_cpt_``origin_modport``_``to_modport``
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`define VCS_DATAC_CPT_LT(inf,origin_modport,to_modport,flag)\
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`define inf``_vcs_cpt``flag inf
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// VCS AXI4 comptable macro
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// `define VCS_AXI4_ARRAY_CPT(num,origin_axi4,origin_modport,to_modport,flag)\
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// axi_inf #(\
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// .IDSIZE (origin_axi4[0].IDSIZE),\
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// .ASIZE (origin_axi4[0].ASIZE ),\
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// .LSIZE (origin_axi4[0].LSIZE ),\
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// .DSIZE (origin_axi4[0].DSIZE ),\
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// .MODE (origin_axi4[0].MODE ),\
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// .ADDR_STEP (origin_axi4[0].ADDR_STEP),\
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// .FreqM (origin_axi4[0].FreqM )\
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// )origin_axi4``_vcs_cpt_``origin_modport``_``to_modport`` [num-1:0](\
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// /* input bit */ .axi_aclk (origin_axi4[0].axi_aclk ),\
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// /* input bit */ .axi_aresetn (origin_axi4[0].axi_aresetn )\
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// );\
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// vcs_axi4_array_comptable #(\
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// .NUM (num ),\
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// .ORIGIN (`"origin_modport`"),\
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// .TO (`"to_modport`")\
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// )origin_axi4``_vcs_axi4_comptable_``origin_modport``_``to_modport``_inst(\
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// /* axi_inf */ .origin (origin_axi4 ),\
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// /* axi_inf */ .to (origin_axi4``_vcs_cpt_``origin_modport``_``to_modport``)\
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// );\
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// `define origin_axi4``_vcs_cpt``flag origin_axi4``_vcs_cpt_``origin_modport``_``to_modport``
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`define VCS_AXI4_ARRAY_CPT(num,origin_axi4,origin_modport,to_modport,flag)\
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`define origin_axi4``_vcs_cpt``flag origin_axi4
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// `define VCS_AXI4_ARRAY_CPT_LT(num,inf,origin_modport,to_modport,flag)\
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// axi_inf #(\
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// .IDSIZE (inf[0].IDSIZE),\
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// .ASIZE (inf[0].ASIZE ),\
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// .LSIZE (inf[0].LSIZE ),\
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// .DSIZE (inf[0].DSIZE ),\
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// .MODE (inf[0].MODE ),\
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// .ADDR_STEP (inf[0].ADDR_STEP),\
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// .FreqM (inf[0].FreqM )\
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// )inf``_vcs_cpt_``origin_modport``_``to_modport`` [num-1:0](\
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// /* input bit */ .axi_aclk (inf[0].axi_aclk ),\
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// /* input bit */ .axi_aresetn (inf[0].axi_aresetn )\
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// );\
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// vcs_axi4_array_comptable #(\
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// .NUM (num ),\
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// .ORIGIN (`"origin_modport`"),\
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// .TO (`"to_modport`")\
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// )inf``_vcs_axi4_comptable_``origin_modport``_``to_modport``_inst(\
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// /* axi_inf */ .origin (inf``_vcs_cpt_``origin_modport``_``to_modport``),\
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// /* axi_inf */ .to (inf)\
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// );\
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// `define inf``_vcs_cpt``flag inf``_vcs_cpt_``origin_modport``_``to_modport``
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`define VCS_AXI4_ARRAY_CPT_LT(num,inf,origin_modport,to_modport,flag)\
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`define inf``_vcs_cpt``flag inf
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@@ -0,0 +1,194 @@
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`define CheckParamPair(X,Y)\
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initial begin\
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Check_Param_Pair(X,Y,`__FILE__,`__LINE__,`"X != Y`");\
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5
|
+
end
|
|
6
|
+
//---- TAP FLAG -----------------------------------
|
|
7
|
+
|
|
8
|
+
`define VCS_ENV
|
|
9
|
+
|
|
10
|
+
`define parameter_string parameter [8*32-1:0]
|
|
11
|
+
`define parameter_longstring(num=128) parameter [num*32-1:0]
|
|
12
|
+
// VCS AXI4 comptable macro
|
|
13
|
+
|
|
14
|
+
`define VCS_AXI4_CPT(origin_axi4,origin_modport,to_modport,flag)\
|
|
15
|
+
axi_inf #(\
|
|
16
|
+
.IDSIZE (origin_axi4.IDSIZE),\
|
|
17
|
+
.ASIZE (origin_axi4.ASIZE ),\
|
|
18
|
+
.LSIZE (origin_axi4.LSIZE ),\
|
|
19
|
+
.DSIZE (origin_axi4.DSIZE ),\
|
|
20
|
+
.MODE (`"BOTH`" ),\
|
|
21
|
+
.ADDR_STEP (origin_axi4.ADDR_STEP),\
|
|
22
|
+
.FreqM (origin_axi4.FreqM )\
|
|
23
|
+
)origin_axi4``_vcs_cpt_``origin_modport``_``to_modport``(\
|
|
24
|
+
/* input bit */ .axi_aclk (origin_axi4.axi_aclk ),\
|
|
25
|
+
/* input bit */ .axi_aresetn (origin_axi4.axi_aresetn )\
|
|
26
|
+
);\
|
|
27
|
+
vcs_axi4_comptable #(\
|
|
28
|
+
.ORIGIN (`"origin_modport`"),\
|
|
29
|
+
.TO (`"to_modport`")\
|
|
30
|
+
)origin_axi4``_vcs_axi4_comptable_``origin_modport``_``to_modport``_inst(\
|
|
31
|
+
/* axi_inf */ .origin (origin_axi4 ),\
|
|
32
|
+
/* axi_inf */ .to (origin_axi4``_vcs_cpt_``origin_modport``_``to_modport``)\
|
|
33
|
+
);\
|
|
34
|
+
`define origin_axi4``_vcs_cpt``flag origin_axi4``_vcs_cpt_``origin_modport``_``to_modport``
|
|
35
|
+
|
|
36
|
+
// `define VCS_AXI4_CPT(origin_axi4,origin_modport,to_modport)\
|
|
37
|
+
// `define origin_axi4``_vcs_cpt origin_axi4
|
|
38
|
+
|
|
39
|
+
// VCS AXI STREAM comptable macro
|
|
40
|
+
`define VCS_AXIS_CPT(origin_axis,origin_modport,to_modport,flag)\
|
|
41
|
+
axi_stream_inf #(\
|
|
42
|
+
.DSIZE (origin_axis.DSIZE),\
|
|
43
|
+
.FreqM (origin_axis.FreqM),\
|
|
44
|
+
.KSIZE (origin_axis.KSIZE),\
|
|
45
|
+
.CSIZE (origin_axis.CSIZE)\
|
|
46
|
+
)origin_axis``_vcs_cpt_``origin_modport``_``to_modport``(\
|
|
47
|
+
/* input bit */ .aclk (origin_axis.aclk ),\
|
|
48
|
+
/* input bit */ .aresetn (origin_axis.aresetn ),\
|
|
49
|
+
/* input bit */ .aclken (origin_axis.aclken )\
|
|
50
|
+
);\
|
|
51
|
+
vcs_axis_comptable #(\
|
|
52
|
+
.ORIGIN (`"origin_modport`"),\
|
|
53
|
+
.TO (`"to_modport`")\
|
|
54
|
+
)origin_axis``_vcs_axis_comptable_``origin_modport``_``to_modport``_inst(\
|
|
55
|
+
/* axi_inf */ .origin (origin_axis ),\
|
|
56
|
+
/* axi_inf */ .to (origin_axis``_vcs_cpt_``origin_modport``_``to_modport`` )\
|
|
57
|
+
);\
|
|
58
|
+
`define origin_axis``_vcs_cpt``flag origin_axis``_vcs_cpt_``origin_modport``_``to_modport``
|
|
59
|
+
|
|
60
|
+
// VCS DATA_C comptable macro
|
|
61
|
+
`define VCS_DATAC_CPT(origin_inf,origin_modport,to_modport,flag)\
|
|
62
|
+
data_inf_c #(\
|
|
63
|
+
.DSIZE (origin_inf.DSIZE),\
|
|
64
|
+
.FreqM (origin_inf.FreqM)\
|
|
65
|
+
)origin_inf``_vcs_cpt_``origin_modport``_``to_modport``(\
|
|
66
|
+
/* input bit */ .clock (origin_inf.clock ),\
|
|
67
|
+
/* input bit */ .rst_n (origin_inf.rst_n )\
|
|
68
|
+
);\
|
|
69
|
+
vcs_data_c_comptable #(\
|
|
70
|
+
.ORIGIN (`"origin_modport`"),\
|
|
71
|
+
.TO (`"to_modport`")\
|
|
72
|
+
)origin_inf``_vcs_axis_comptable_``origin_modport``_``to_modport``_inst(\
|
|
73
|
+
/* data_inf_c */ .origin (origin_inf ),\
|
|
74
|
+
/* data_inf_c */ .to (origin_inf``_vcs_cpt_``origin_modport``_``to_modport`` )\
|
|
75
|
+
);\
|
|
76
|
+
`define origin_inf``_vcs_cpt``flag origin_inf``_vcs_cpt_``origin_modport``_``to_modport``
|
|
77
|
+
|
|
78
|
+
|
|
79
|
+
// VCS AXI4 comptable macro
|
|
80
|
+
// Lock TO
|
|
81
|
+
`define VCS_AXI4_CPT_LT(inf,origin_modport,to_modport,flag)\
|
|
82
|
+
axi_inf #(\
|
|
83
|
+
.IDSIZE (inf.IDSIZE),\
|
|
84
|
+
.ASIZE (inf.ASIZE ),\
|
|
85
|
+
.LSIZE (inf.LSIZE ),\
|
|
86
|
+
.DSIZE (inf.DSIZE ),\
|
|
87
|
+
.MODE (`"BOTH`" ),\
|
|
88
|
+
.ADDR_STEP (inf.ADDR_STEP),\
|
|
89
|
+
.FreqM (inf.FreqM )\
|
|
90
|
+
)inf``_vcs_cpt_``origin_modport``_``to_modport``(\
|
|
91
|
+
/* input bit */ .axi_aclk (inf.axi_aclk ),\
|
|
92
|
+
/* input bit */ .axi_aresetn (inf.axi_aresetn )\
|
|
93
|
+
);\
|
|
94
|
+
vcs_axi4_comptable #(\
|
|
95
|
+
.ORIGIN (`"origin_modport`"),\
|
|
96
|
+
.TO (`"to_modport`")\
|
|
97
|
+
)inf``_vcs_axi4_comptable_``origin_modport``_``to_modport``_inst(\
|
|
98
|
+
/* axi_inf */ .origin (inf``_vcs_cpt_``origin_modport``_``to_modport``),\
|
|
99
|
+
/* axi_inf */ .to (inf)\
|
|
100
|
+
);\
|
|
101
|
+
`define inf``_vcs_cpt``flag inf``_vcs_cpt_``origin_modport``_``to_modport``
|
|
102
|
+
|
|
103
|
+
// `define VCS_AXI4_CPT(origin_axi4,origin_modport,to_modport)\
|
|
104
|
+
// `define origin_axi4``_vcs_cpt origin_axi4
|
|
105
|
+
|
|
106
|
+
// VCS AXI STREAM comptable macro
|
|
107
|
+
// Lock to
|
|
108
|
+
`define VCS_AXIS_CPT_LT(inf,origin_modport,to_modport,flag)\
|
|
109
|
+
axi_stream_inf #(\
|
|
110
|
+
.DSIZE (inf.DSIZE),\
|
|
111
|
+
.FreqM (inf.FreqM),\
|
|
112
|
+
.KSIZE (inf.KSIZE),\
|
|
113
|
+
.CSIZE (inf.CSIZE)\
|
|
114
|
+
)inf``_vcs_cpt_``origin_modport``_``to_modport``(\
|
|
115
|
+
/* input bit */ .aclk (inf.aclk ),\
|
|
116
|
+
/* input bit */ .aresetn (inf.aresetn ),\
|
|
117
|
+
/* input bit */ .aclken (inf.aclken )\
|
|
118
|
+
);\
|
|
119
|
+
vcs_axis_comptable #(\
|
|
120
|
+
.ORIGIN (`"origin_modport`"),\
|
|
121
|
+
.TO (`"to_modport`")\
|
|
122
|
+
)inf``_vcs_axis_comptable_``origin_modport``_``to_modport``_inst(\
|
|
123
|
+
/* axi_inf */ .origin (inf``_vcs_cpt_``origin_modport``_``to_modport`` ),\
|
|
124
|
+
/* axi_inf */ .to (inf )\
|
|
125
|
+
);\
|
|
126
|
+
`define inf``_vcs_cpt``flag inf``_vcs_cpt_``origin_modport``_``to_modport``
|
|
127
|
+
|
|
128
|
+
// VCS DATA_C comptable macro
|
|
129
|
+
// Lock to
|
|
130
|
+
`define VCS_DATAC_CPT_LT(inf,origin_modport,to_modport,flag)\
|
|
131
|
+
data_inf_c #(\
|
|
132
|
+
.DSIZE (inf.DSIZE),\
|
|
133
|
+
.FreqM (inf.FreqM)\
|
|
134
|
+
)inf``_vcs_cpt_``origin_modport``_``to_modport``(\
|
|
135
|
+
/* input bit */ .clock (inf.clock ),\
|
|
136
|
+
/* input bit */ .rst_n (inf.rst_n )\
|
|
137
|
+
);\
|
|
138
|
+
vcs_data_c_comptable #(\
|
|
139
|
+
.ORIGIN (`"origin_modport`"),\
|
|
140
|
+
.TO (`"to_modport`")\
|
|
141
|
+
)inf``_vcs_axis_comptable_``origin_modport``_``to_modport``_inst(\
|
|
142
|
+
/* data_inf_c */ .origin (inf``_vcs_cpt_``origin_modport``_``to_modport`` ),\
|
|
143
|
+
/* data_inf_c */ .to (inf )\
|
|
144
|
+
);\
|
|
145
|
+
`define inf``_vcs_cpt``flag inf``_vcs_cpt_``origin_modport``_``to_modport``
|
|
146
|
+
|
|
147
|
+
// VCS AXI4 comptable macro
|
|
148
|
+
|
|
149
|
+
`define VCS_AXI4_ARRAY_CPT(num,origin_axi4,origin_modport,to_modport,flag)\
|
|
150
|
+
axi_inf #(\
|
|
151
|
+
.IDSIZE (origin_axi4[0].IDSIZE),\
|
|
152
|
+
.ASIZE (origin_axi4[0].ASIZE ),\
|
|
153
|
+
.LSIZE (origin_axi4[0].LSIZE ),\
|
|
154
|
+
.DSIZE (origin_axi4[0].DSIZE ),\
|
|
155
|
+
.MODE (`"BOTH`" ),\
|
|
156
|
+
.ADDR_STEP (origin_axi4[0].ADDR_STEP),\
|
|
157
|
+
.FreqM (origin_axi4[0].FreqM )\
|
|
158
|
+
)origin_axi4``_vcs_cpt_``origin_modport``_``to_modport`` [num-1:0](\
|
|
159
|
+
/* input bit */ .axi_aclk (origin_axi4[0].axi_aclk ),\
|
|
160
|
+
/* input bit */ .axi_aresetn (origin_axi4[0].axi_aresetn )\
|
|
161
|
+
);\
|
|
162
|
+
vcs_axi4_array_comptable #(\
|
|
163
|
+
.NUM (num ),\
|
|
164
|
+
.ORIGIN (`"origin_modport`"),\
|
|
165
|
+
.TO (`"to_modport`")\
|
|
166
|
+
)origin_axi4``_vcs_axi4_comptable_``origin_modport``_``to_modport``_inst(\
|
|
167
|
+
/* axi_inf */ .origin (origin_axi4 ),\
|
|
168
|
+
/* axi_inf */ .to (origin_axi4``_vcs_cpt_``origin_modport``_``to_modport``)\
|
|
169
|
+
);\
|
|
170
|
+
`define origin_axi4``_vcs_cpt``flag origin_axi4``_vcs_cpt_``origin_modport``_``to_modport``
|
|
171
|
+
|
|
172
|
+
|
|
173
|
+
`define VCS_AXI4_ARRAY_CPT_LT(num,inf,origin_modport,to_modport,flag)\
|
|
174
|
+
axi_inf #(\
|
|
175
|
+
.IDSIZE (inf[0].IDSIZE),\
|
|
176
|
+
.ASIZE (inf[0].ASIZE ),\
|
|
177
|
+
.LSIZE (inf[0].LSIZE ),\
|
|
178
|
+
.DSIZE (inf[0].DSIZE ),\
|
|
179
|
+
.MODE (`"BOTH`" ),\
|
|
180
|
+
.ADDR_STEP (inf[0].ADDR_STEP),\
|
|
181
|
+
.FreqM (inf[0].FreqM )\
|
|
182
|
+
)inf``_vcs_cpt_``origin_modport``_``to_modport`` [num-1:0](\
|
|
183
|
+
/* input bit */ .axi_aclk (inf[0].axi_aclk ),\
|
|
184
|
+
/* input bit */ .axi_aresetn (inf[0].axi_aresetn )\
|
|
185
|
+
);\
|
|
186
|
+
vcs_axi4_array_comptable #(\
|
|
187
|
+
.NUM (num ),\
|
|
188
|
+
.ORIGIN (`"origin_modport`"),\
|
|
189
|
+
.TO (`"to_modport`")\
|
|
190
|
+
)inf``_vcs_axi4_comptable_``origin_modport``_``to_modport``_inst(\
|
|
191
|
+
/* axi_inf */ .origin (inf``_vcs_cpt_``origin_modport``_``to_modport``),\
|
|
192
|
+
/* axi_inf */ .to (inf)\
|
|
193
|
+
);\
|
|
194
|
+
`define inf``_vcs_cpt``flag inf``_vcs_cpt_``origin_modport``_``to_modport``
|
data/lib/axi_tdl/version.rb
CHANGED
|
@@ -60,6 +60,58 @@ class Axi4
|
|
|
60
60
|
end
|
|
61
61
|
|
|
62
62
|
def <<(*up_streams)
|
|
63
|
+
require_shdl 'axi4_direct_algin_addr_step'
|
|
64
|
+
up_streams.each do |up_stream|
|
|
65
|
+
## e is a Vector
|
|
66
|
+
if up_stream.is_a? Axi4
|
|
67
|
+
if up_stream.dimension && up_stream.dimension[0].is_a?(Integer) && up_stream.dimension[0] > 1
|
|
68
|
+
self.belong_to_module.instance_exec(self,up_stream) do |curr_axi4_inst,up_stream|
|
|
69
|
+
up_stream.copy(
|
|
70
|
+
name: "#{up_stream.inst_name}_algin_addr",
|
|
71
|
+
addr_step: curr_axi4_inst.addr_step*up_stream.dsize/curr_axi4_inst.dsize,
|
|
72
|
+
dimension:up_stream.dimension)
|
|
73
|
+
|
|
74
|
+
generate(up_stream.dimension[0]) do |kk|
|
|
75
|
+
Instance(:axi4_direct_algin_addr_step,"algin_addr_#{up_stream.inst_name}_#{curr_axi4_inst.name}") do |h| #(
|
|
76
|
+
h.param.SLAVER_ADDR_STEP up_stream.addr_step
|
|
77
|
+
h.param.TERMENAL_ADDR_STEP curr_axi4_inst.addr_step
|
|
78
|
+
h.param.TERMENAL_DSIZE curr_axi4_inst.dsize
|
|
79
|
+
h.param.MODE "#{up_stream.mode}_to_#{up_stream.mode}" #//ONLY_READ to BOTH,ONLY_WRITE to BOTH,BOTH to BOTH,BOTH to ONLY_READ,BOTH to ONLY_WRITE
|
|
80
|
+
h.param.SLAVER_MODE up_stream.mode
|
|
81
|
+
h.param.MASTER_MODE up_stream.mode
|
|
82
|
+
h.port.axi_inf.slaver.slaver_inf up_stream[kk]
|
|
83
|
+
h.port.axi_inf.master.master_inf curr_axi4_inst.belong_to_module.signal("#{up_stream.inst_name}_algin_addr")[kk]
|
|
84
|
+
end
|
|
85
|
+
end
|
|
86
|
+
curr_axi4_inst.old_append( signal("#{up_stream.inst_name}_algin_addr") )
|
|
87
|
+
end
|
|
88
|
+
else
|
|
89
|
+
curr_axi4_inst = self
|
|
90
|
+
up_stream.copy(
|
|
91
|
+
name: "#{up_stream.inst_name}_algin_addr",
|
|
92
|
+
addr_step: curr_axi4_inst.addr_step*up_stream.dsize/curr_axi4_inst.dsize)
|
|
93
|
+
|
|
94
|
+
self.belong_to_module.Instance(:axi4_direct_algin_addr_step,"algin_addr_#{up_stream.inst_name}_#{name}_#{belong_to_module._auto_name_incr_index_}") do |h| #(
|
|
95
|
+
h.param.SLAVER_ADDR_STEP up_stream.addr_step
|
|
96
|
+
h.param.TERMENAL_ADDR_STEP curr_axi4_inst.addr_step
|
|
97
|
+
h.param.TERMENAL_DSIZE curr_axi4_inst.dsize
|
|
98
|
+
h.param.MODE "#{up_stream.mode}_to_#{up_stream.mode}" #//ONLY_READ to BOTH,ONLY_WRITE to BOTH,BOTH to BOTH,BOTH to ONLY_READ,BOTH to ONLY_WRITE
|
|
99
|
+
h.param.SLAVER_MODE up_stream.mode
|
|
100
|
+
h.param.MASTER_MODE up_stream.mode
|
|
101
|
+
h.port.axi_inf.slaver.slaver_inf up_stream
|
|
102
|
+
h.port.axi_inf.master.master_inf self.belong_to_module.signal("#{up_stream.inst_name}_algin_addr")
|
|
103
|
+
|
|
104
|
+
end
|
|
105
|
+
curr_axi4_inst.old_append( self.belong_to_module.signal("#{up_stream.inst_name}_algin_addr") )
|
|
106
|
+
end
|
|
107
|
+
else
|
|
108
|
+
self.old_append(up_stream)
|
|
109
|
+
end
|
|
110
|
+
end
|
|
111
|
+
|
|
112
|
+
end
|
|
113
|
+
|
|
114
|
+
def old_append(*up_streams)
|
|
63
115
|
@interconnect_up_streams ||= []
|
|
64
116
|
push_to_stack
|
|
65
117
|
up_streams.each do |e|
|
|
@@ -178,30 +230,44 @@ class Axi4
|
|
|
178
230
|
# if(true )
|
|
179
231
|
new_master = self.copy(mode:e.mode,idsize:e.idsize+4)
|
|
180
232
|
new_master.mode = e.mode
|
|
181
|
-
|
|
182
|
-
|
|
183
|
-
|
|
233
|
+
|
|
234
|
+
require_hdl 'axi4_long_to_axi4_wide_B1.sv'
|
|
235
|
+
|
|
236
|
+
TopModule.contain_hdl 'axi4_packet_fifo_verb.sv'
|
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237
|
+
TopModule.contain_hdl 'axi4_data_convert_verb.sv'
|
|
238
|
+
TopModule.contain_hdl 'data_c_pipe_force_vld.sv'
|
|
239
|
+
|
|
240
|
+
belong_to_module.Instance(:axi4_long_to_axi4_wide_B1,"axi4_long_to_axi4_wide_B1_#{index}_inst") do |h|
|
|
184
241
|
h[:PARTITION] = "ON"
|
|
185
242
|
h[:PIPE] = (@interconnect_pipe ? "ON" : "OFF")
|
|
186
|
-
h[:
|
|
187
|
-
h[:
|
|
243
|
+
h[:MODE] = "#{e.mode}_TO_#{new_master.mode}"
|
|
244
|
+
h[:SLAVER_MODE] = e.mode
|
|
245
|
+
h[:MASTER_MODE] = new_master.mode
|
|
246
|
+
h[:slaver_inf] = e
|
|
247
|
+
h[:master_inf] = new_master
|
|
188
248
|
end
|
|
189
249
|
@_long_slim_to_wide << new_master
|
|
190
250
|
else
|
|
191
251
|
if !(e.dsize.eql? self.dsize)
|
|
192
|
-
require_hdl '
|
|
193
|
-
TopModule.contain_hdl '
|
|
252
|
+
require_hdl 'axi4_long_to_axi4_wide_B1.sv'
|
|
253
|
+
TopModule.contain_hdl 'axi4_direct_verc.sv'
|
|
254
|
+
TopModule.contain_hdl 'axi4_packet_fifo_verb.sv'
|
|
255
|
+
TopModule.contain_hdl 'axi4_data_convert_verb.sv'
|
|
256
|
+
TopModule.contain_hdl 'data_c_pipe_force_vld.sv'
|
|
194
257
|
# puts "#{e.dsize} == #{self.dsize} #{e.dsize != self.dsize} #{e.dsize.class}"
|
|
195
258
|
new_master = self.copy(name: "#{e.name}_renew_dir",mode:e.mode,idsize:e.idsize)
|
|
196
259
|
# new_master.axi4_data_convert(up_stream: e)
|
|
197
260
|
# @_long_slim_to_wide << Axi4.axi4_pipe(up_stream:new_master)
|
|
198
261
|
|
|
199
262
|
# Axi4.axi4_long_to_axi4_wide_verb(slaver:e,master:new_master,partition:"OFF",pipe:(@interconnect_pipe ? "ON" : "OFF"))
|
|
200
|
-
belong_to_module.Instance(:
|
|
263
|
+
belong_to_module.Instance(:axi4_long_to_axi4_wide_B1,"axi4_long_to_axi4_wide_B1_#{index}_inst") do |h|
|
|
201
264
|
h[:PARTITION] = "OFF"
|
|
202
265
|
h[:PIPE] = (@interconnect_pipe ? "ON" : "OFF")
|
|
203
|
-
h[:
|
|
204
|
-
h[:
|
|
266
|
+
h[:MODE] = "#{e.mode}_to_#{new_master.mode}"
|
|
267
|
+
h[:SLAVER_MODE] = e.mode
|
|
268
|
+
h[:MASTER_MODE] = new_master.mode
|
|
269
|
+
h[:slaver_inf] = e
|
|
270
|
+
h[:master_inf] = new_master
|
|
205
271
|
end
|
|
206
272
|
@_long_slim_to_wide << new_master
|
|
207
273
|
|
|
@@ -1,35 +1,9 @@
|
|
|
1
|
-
/**********************************************
|
|
2
|
-
_______________________________________
|
|
3
|
-
___________ Cook Darwin __________
|
|
4
|
-
_______________________________________
|
|
5
|
-
descript:
|
|
6
|
-
author : Cook.Darwin
|
|
7
|
-
Version: VERA.0.0
|
|
8
|
-
created: 2021-09-30 21:21:22 +0800
|
|
9
|
-
madified:
|
|
10
|
-
***********************************************/
|
|
11
|
-
`timescale 1ns/1ps
|
|
12
|
-
|
|
13
|
-
module exp_test_unit (
|
|
14
|
-
input clock,
|
|
15
|
-
input rst_n
|
|
16
|
-
);
|
|
17
|
-
|
|
18
|
-
//==========================================================================
|
|
19
|
-
//-------- define ----------------------------------------------------------
|
|
20
|
-
logic enable;
|
|
21
|
-
axi_stream_inf #(.DSIZE(8),.FreqM(100),.USIZE(1)) axis_data_inf (.aclk(clock),.aresetn(rst_n),.aclken(1'b1)) ;
|
|
22
|
-
//==========================================================================
|
|
23
|
-
//-------- instance --------------------------------------------------------
|
|
24
|
-
sub_md1 sub_md1_inst(
|
|
25
|
-
/* axi_stream_inf.master */.axis_out (axis_data_inf ),
|
|
26
|
-
/* output */.enable (enable )
|
|
27
|
-
);
|
|
28
|
-
sub_md0 sub_md0_inst(
|
|
29
|
-
/* axi_stream_inf.slaver */.axis_in (axis_data_inf ),
|
|
30
|
-
/* input */.enable (enable )
|
|
31
|
-
);
|
|
32
|
-
//==========================================================================
|
|
33
|
-
//-------- expression ------------------------------------------------------
|
|
34
1
|
|
|
2
|
+
`timescale 1ns/1ps
|
|
3
|
+
module exp_test_unit();
|
|
4
|
+
initial begin
|
|
5
|
+
#(1us);
|
|
6
|
+
$warning("Check TopModule.sim,please!!!");
|
|
7
|
+
$stop;
|
|
8
|
+
end
|
|
35
9
|
endmodule
|
|
@@ -5,7 +5,7 @@ _______________________________________
|
|
|
5
5
|
descript:
|
|
6
6
|
author : Cook.Darwin
|
|
7
7
|
Version: VERA.0.0
|
|
8
|
-
created:
|
|
8
|
+
created: 2022-07-10 11:18:28 +0800
|
|
9
9
|
madified:
|
|
10
10
|
***********************************************/
|
|
11
11
|
`timescale 1ns/1ps
|
|
@@ -15,8 +15,8 @@ module tb_exp_test_unit_sim();
|
|
|
15
15
|
//-------- define ----------------------------------------------------------
|
|
16
16
|
logic sys_clk;
|
|
17
17
|
string test_unit_region;
|
|
18
|
-
logic [
|
|
19
|
-
logic [
|
|
18
|
+
logic [0-1:0] unit_pass_u ;
|
|
19
|
+
logic [0-1:0] unit_pass_d ;
|
|
20
20
|
|
|
21
21
|
//==========================================================================
|
|
22
22
|
//-------- instance --------------------------------------------------------
|
|
@@ -24,18 +24,7 @@ exp_test_unit_sim rtl_top(
|
|
|
24
24
|
/* input clock */.clock (sys_clk ),
|
|
25
25
|
/* input reset */.rst_n (1'b1 )
|
|
26
26
|
);
|
|
27
|
-
tu0 test_unit_0(
|
|
28
|
-
/* input */.from_up_pass (unit_pass_u[0] ),
|
|
29
|
-
/* output */.to_down_pass (unit_pass_d[0] )
|
|
30
|
-
);
|
|
31
|
-
tu1 test_unit_1(
|
|
32
|
-
/* input */.from_up_pass (unit_pass_u[1] ),
|
|
33
|
-
/* output */.to_down_pass (unit_pass_d[1] )
|
|
34
|
-
);
|
|
35
27
|
//==========================================================================
|
|
36
28
|
//-------- expression ------------------------------------------------------
|
|
37
|
-
assign unit_pass_u[0] = 1'b1;
|
|
38
|
-
|
|
39
|
-
assign unit_pass_u[1] = unit_pass_d[0];
|
|
40
29
|
|
|
41
30
|
endmodule
|
|
@@ -5,7 +5,7 @@ _______________________________________
|
|
|
5
5
|
descript:
|
|
6
6
|
author : Cook.Darwin
|
|
7
7
|
Version: VERA.0.0
|
|
8
|
-
created:
|
|
8
|
+
created: 2022-07-10 11:18:43 +0800
|
|
9
9
|
madified:
|
|
10
10
|
***********************************************/
|
|
11
11
|
`timescale 1ns/1ps
|
|
@@ -19,7 +19,7 @@ module test_module_var #(
|
|
|
19
19
|
|
|
20
20
|
//==========================================================================
|
|
21
21
|
//-------- define ----------------------------------------------------------
|
|
22
|
-
localparam ASIZE = 20;
|
|
22
|
+
localparam ASIZE = 20 ;
|
|
23
23
|
axi_stream_inf #(.DSIZE(8),.FreqM(100),.USIZE(1)) tmp_axis_inf (.aclk(clock),.aresetn(rst_n),.aclken(1'b1)) ;
|
|
24
24
|
axi_stream_inf #(.DSIZE(8),.FreqM(100),.USIZE(1)) tmp_axis0_inf (.aclk(clock),.aresetn(rst_n),.aclken(1'b1)) ;
|
|
25
25
|
axi_inf #(.DSIZE(32),.IDSIZE(2),.ASIZE(8),.LSIZE(9),.MODE("BOTH"),.ADDR_STEP(4294967295),.FreqM(100)) tmp_axi4_inf (.axi_aclk(clock),.axi_aresetn(rst_n)) ;
|