axi_tdl 0.1.20 → 0.2.0
This diff represents the content of publicly available package versions that have been released to one of the supported registries. The information contained in this diff is provided for informational purposes only and reflects changes between package versions as they appear in their respective public registries.
- checksums.yaml +4 -4
- data/lib/axi/AXI4/axi4_direct_algin_addr_step.sv +223 -0
- data/lib/axi/AXI4/axi4_direct_verc.sv +54 -5
- data/lib/axi/AXI4/axi4_long_to_axi4_wide_B1.sv +146 -0
- data/lib/axi/AXI4/packet_fifo/axi4_packet_fifo_verb.sv +62 -0
- data/lib/axi/AXI4/packet_fifo/axi4_wr_packet_fifo.sv +4 -3
- data/lib/axi/AXI4/wide_axis_to_axi4_wr.sv +1 -1
- data/lib/axi/AXI4/width_convert/axi4_data_convert_verb.sv +280 -0
- data/lib/axi/AXI_stream/axi_stream_interconnect_M2S_cpVCS.sv +80 -0
- data/lib/axi/AXI_stream/axi_stream_split_channel.sv +20 -20
- data/lib/axi/AXI_stream/axis_append_A1.sv +15 -2
- data/lib/axi/AXI_stream/axis_uncompress_verb.sv +9 -9
- data/lib/axi/AXI_stream/parse_big_field_table_verb.sv +3 -2
- data/lib/axi/data_interface/data_inf_c/data_c_pipe_sync_seam.sv +10 -10
- data/lib/axi/data_interface/data_inf_c/data_c_scaler_A1.sv +2 -1
- data/lib/axi/interface_define/axi_inf.sv +1 -1
- data/lib/axi/macro/RTL/define_macro.sv +210 -0
- data/lib/axi/macro/SIM/define_macro.sv +194 -0
- data/lib/axi_tdl/version.rb +1 -1
- data/lib/tdl/auto_script/import_sdl.rb +3 -0
- data/lib/tdl/axi4/axi4_interconnect_verb.rb +76 -10
- data/lib/tdl/examples/11_test_unit/exp_test_unit.sv +7 -33
- data/lib/tdl/examples/11_test_unit/tb_exp_test_unit.sv +1 -1
- data/lib/tdl/examples/11_test_unit/tb_exp_test_unit_sim.sv +3 -14
- data/lib/tdl/examples/11_test_unit/tu0.sv +1 -1
- data/lib/tdl/examples/2_hdl_class/tmp/test_module_var.sv +2 -2
- data/lib/tdl/examples/2_hdl_class/tmp/test_vcs_string.sv +1 -1
- data/lib/tdl/examples/8_top_module/dve.tcl +0 -6
- data/lib/tdl/examples/8_top_module/test_top.sv +1 -1
- data/lib/tdl/examples/9_itegration/clock_manage/tu_ClockManage_test_clock_bb.sv +35 -0
- data/lib/tdl/examples/9_itegration/tb_test_tttop_sim.sv +2 -2
- data/lib/tdl/examples/9_itegration/test_tttop.sv +38 -7
- data/lib/tdl/examples/9_itegration/test_tttop_sim.sv +7 -38
- data/lib/tdl/examples/9_itegration/top.rb +1 -1
- data/lib/tdl/exlib/itegration_test_unit.rb +13 -0
- data/lib/tdl/exlib/itegration_verb.rb +22 -17
- data/lib/tdl/rebuild_ele/ele_base.rb +15 -3
- data/lib/tdl/sdlmodule/sdlmodule_arraychain.rb +1 -0
- data/lib/tdl/sdlmodule/sdlmodule_instance.rb +1 -1
- data/lib/tdl/sdlmodule/test_unit_module.rb +12 -16
- data/lib/tdl/tdl.rb +1 -0
- metadata +11 -2
@@ -0,0 +1,280 @@
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/**********************************************
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_______________________________________
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___________ Cook Darwin __________
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_______________________________________
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descript:
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author : Cook.Darwin
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Version: VERA.1.0 2017/5/23
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use width convert verb
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Version: VERB.0.0 2021/10
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explicit mode
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creaded: 2017/2/20
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madified:
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***********************************************/
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`timescale 1ns/1ps
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`include "define_macro.sv"
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module axi4_data_convert_verb #(
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`parameter_string SLAVER_MODE = "BOTH", //
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`parameter_string MASTER_MODE = "BOTH" //
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)(
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axi_inf.slaver axi_in,
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axi_inf.master axi_out
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);
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import SystemPkg::*;
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initial begin
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assert(axi_in.MODE == axi_out.MODE)
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else begin
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$error("SLAVER AXI4 MODE != MASTER AXI4 MODE");
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$stop;
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end
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assert(SLAVER_MODE == MASTER_MODE)
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else begin
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$error("SLAVER AXI4 MODE<%0s> != MASTER AXI4 MODE<%0s>",SLAVER_MODE, MASTER_MODE);
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$stop;
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end
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assert(SLAVER_MODE == axi_out.MODE && SLAVER_MODE == axi_in.MODE)
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else begin
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$error("SLAVER AXI4 MODE<%0s> != MASTER AXI4 MODE<%0s>",SLAVER_MODE, MASTER_MODE);
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$stop;
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end
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assert(real'(axi_in.DSIZE)/axi_in.ADDR_STEP == real'(axi_out.DSIZE)/axi_out.ADDR_STEP)
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else begin
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// $error("SLAVER ADDR STEP DONT MATCH MASTER");
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$error("SLAVER ADDR STEP [%d][%d] DONT MATCH MASTER[%d][%d]",axi_in.DSIZE,axi_in.ADDR_STEP,axi_out.DSIZE,axi_out.ADDR_STEP);
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$finish;
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end
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end
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generate
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if(SLAVER_MODE=="BOTH" || SLAVER_MODE=="ONLY_WRITE")begin:AW_BLOCK
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axi4_data_combin_aflag_pipe_A1 #(
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.MODE ("WRITE" ),
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.IDSIZE (axi_in.IDSIZE ),
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.ASIZE (axi_in.ASIZE ),
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.ILSIZE (axi_in.LSIZE ),
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.OLSIZE (axi_out.LSIZE ),
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.ISIZE (axi_in.DSIZE ),
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.OSIZE (axi_out.DSIZE )
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)axi4_data_combin_aflag_pipe_wr(
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/* input */ .clock (axi_in.axi_aclk ),
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/* input */ .rst_n (axi_in.axi_aresetn ),
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/* input[IDSIZE-1:0] */ .in_a_id (axi_in.axi_awid ),
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/* input[ASIZE-1:0] */ .in_a_addr (axi_in.axi_awaddr ),
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/* input[ILSIZE-1:0] */ .in_a_len (axi_in.axi_awlen ),
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/* input[2:0] */ .in_a_size (axi_in.axi_awsize ),
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/* input[1:0] */ .in_a_burst (axi_in.axi_awburst ),
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/* input[0:0] */ .in_a_lock (axi_in.axi_awlock ),
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/* input[3:0] */ .in_a_cache (axi_in.axi_awcache ),
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/* input[2:0] */ .in_a_prot (axi_in.axi_awprot ),
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/* input[3:0] */ .in_a_qos (axi_in.axi_awqos ),
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/* input */ .in_a_valid (axi_in.axi_awvalid ),
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/* output */ .in_a_ready (axi_in.axi_awready ),
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/* output[IDSIZE-1:0] */ .out_a_id (axi_out.axi_awid ),
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/* output[ASIZE-1:0] */ .out_a_addr (axi_out.axi_awaddr ),
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/* output[OLSIZE-1:0] */ .out_a_len (axi_out.axi_awlen ),
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/* output[2:0] */ .out_a_size (axi_out.axi_awsize ),
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/* output[1:0] */ .out_a_burst (axi_out.axi_awburst),
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/* output[0:0] */ .out_a_lock (axi_out.axi_awlock ),
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/* output[3:0] */ .out_a_cache (axi_out.axi_awcache),
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/* output[2:0] */ .out_a_prot (axi_out.axi_awprot ),
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/* output[3:0] */ .out_a_qos (axi_out.axi_awqos ),
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/* output */ .out_a_valid (axi_out.axi_awvalid),
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/* input */ .out_a_ready (axi_out.axi_awready)
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);
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end
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endgenerate
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generate
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if(SLAVER_MODE=="BOTH" || SLAVER_MODE=="ONLY_READ")begin:AR_BLOCK
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axi4_data_combin_aflag_pipe_A1 #(
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.MODE ("READ" ),
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.IDSIZE (axi_in.IDSIZE ),
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.ASIZE (axi_in.ASIZE ),
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.ILSIZE (axi_in.LSIZE ),
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.OLSIZE (axi_out.LSIZE ),
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.ISIZE (axi_in.DSIZE ),
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.OSIZE (axi_out.DSIZE )
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)axi4_data_combin_aflag_pipe_rd(
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/* input */ .clock (axi_in.axi_aclk ),
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/* input */ .rst_n (axi_in.axi_aresetn ),
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/* input[IDSIZE-1:0] */ .in_a_id (axi_in.axi_arid ),
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/* input[ASIZE-1:0] */ .in_a_addr (axi_in.axi_araddr ),
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/* input[ILSIZE-1:0] */ .in_a_len (axi_in.axi_arlen ),
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/* input[2:0] */ .in_a_size (axi_in.axi_arsize ),
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/* input[1:0] */ .in_a_burst (axi_in.axi_arburst ),
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/* input[0:0] */ .in_a_lock (axi_in.axi_arlock ),
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/* input[3:0] */ .in_a_cache (axi_in.axi_arcache ),
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/* input[2:0] */ .in_a_prot (axi_in.axi_arprot ),
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/* input[3:0] */ .in_a_qos (axi_in.axi_arqos ),
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/* input */ .in_a_valid (axi_in.axi_arvalid ),
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/* output */ .in_a_ready (axi_in.axi_arready ),
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/* output[IDSIZE-1:0] */ .out_a_id (axi_out.axi_arid ),
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/* output[ASIZE-1:0] */ .out_a_addr (axi_out.axi_araddr ),
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/* output[OLSIZE-1:0] */ .out_a_len (axi_out.axi_arlen ),
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/* output[2:0] */ .out_a_size (axi_out.axi_arsize ),
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/* output[1:0] */ .out_a_burst (axi_out.axi_arburst),
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/* output[0:0] */ .out_a_lock (axi_out.axi_arlock ),
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/* output[3:0] */ .out_a_cache (axi_out.axi_arcache),
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/* output[2:0] */ .out_a_prot (axi_out.axi_arprot ),
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/* output[3:0] */ .out_a_qos (axi_out.axi_arqos ),
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/* output */ .out_a_valid (axi_out.axi_arvalid),
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/* input */ .out_a_ready (axi_out.axi_arready)
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);
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end
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endgenerate
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generate
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if(SLAVER_MODE=="BOTH" || SLAVER_MODE=="ONLY_WRITE")begin:WDATA_BLOCK
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width_convert_verb #(
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.ISIZE (axi_in.DSIZE ),
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.OSIZE (axi_out.DSIZE )
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)width_convert_wr(
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/* input */ .clock (axi_in.axi_aclk ),
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/* input */ .rst_n (axi_in.axi_aresetn ),
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/* input [DSIZE-1:0] */ .wr_data (axi_in.axi_wdata ),
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/* input */ .wr_vld (axi_in.axi_wvalid ),
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/* output logic */ .wr_ready (axi_in.axi_wready ),
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/* input */ .wr_last (axi_in.axi_wlast ),
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/* input */ .wr_align_last (1'b0 ),
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/* output logic[DSIZE*NSIZE-1:0] */ .rd_data (axi_out.axi_wdata ),
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/* output logic */ .rd_vld (axi_out.axi_wvalid ),
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/* input */ .rd_ready (axi_out.axi_wready ),
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/* output logic */ .rd_last (axi_out.axi_wlast )
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);
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end
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endgenerate
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generate
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if(SLAVER_MODE=="BOTH" || SLAVER_MODE=="ONLY_READ")begin:RDATA_BLOCK
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width_convert_verb #(
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.ISIZE (axi_out.DSIZE ),
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.OSIZE (axi_in.DSIZE )
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)width_convert_rd(
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/* input */ .clock (axi_in.axi_aclk ),
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/* input */ .rst_n (axi_in.axi_aresetn ),
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/* input [DSIZE-1:0] */ .wr_data (axi_out.axi_rdata ),
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/* input */ .wr_vld (axi_out.axi_rvalid ),
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/* output logic */ .wr_ready (axi_out.axi_rready ),
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/* input */ .wr_last (axi_out.axi_rlast ),
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/* input */ .wr_align_last (1'b0 ),
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/* output logic[DSIZE*NSIZE-1:0] */ .rd_data (axi_in.axi_rdata ),
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/* output logic */ .rd_vld (axi_in.axi_rvalid ),
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/* input */ .rd_ready (axi_in.axi_rready ),
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/* output logic */ .rd_last (axi_in.axi_rlast )
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);
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end
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endgenerate
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generate
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if(SLAVER_MODE=="BOTH" || SLAVER_MODE=="ONLY_READ")
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simple_data_pipe_slaver #(
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.DSIZE (axi_in.IDSIZE)
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)rid_data_pipe_inst(
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/* input */ .clock (axi_in.axi_aclk ),
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/* input */ .rst_n (axi_in.axi_aresetn ),
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/* input [DSIZE-1:0] */ .indata (axi_out.axi_rid ),
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/* input */ .invalid (axi_out.axi_rvalid ),
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/* output logic */ .inready (axi_out.axi_rready ),
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/* output logic[DSIZE-1:0] */ .outdata (axi_in.axi_rid ),
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/* inpit logic */ .outvalid (axi_in.axi_rvalid ),
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/* input */ .outready (axi_in.axi_rready )
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);
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endgenerate
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//----<< READ ID >>------------
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generate
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if(SLAVER_MODE=="BOTH" || SLAVER_MODE=="ONLY_WRITE")
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simple_data_pipe #(
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.DSIZE (2)
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)bresp_data_pipe_inst(
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/* input */ .clock (axi_in.axi_aclk ),
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/* input */ .rst_n (axi_in.axi_aresetn ),
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/* input [DSIZE-1:0] */ .indata (axi_out.axi_bresp ),
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/* input */ .invalid (axi_out.axi_bvalid ),
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/* output logic */ .inready (axi_out.axi_bready ),
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/* output logic[DSIZE-1:0] */ .outdata (axi_in.axi_bresp ),
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/* output logic */ .outvalid (axi_in.axi_bvalid ),
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/* input */ .outready (axi_in.axi_bready )
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);
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endgenerate
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generate
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if(SLAVER_MODE=="BOTH" || SLAVER_MODE=="ONLY_WRITE")
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simple_data_pipe_slaver #(
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.DSIZE (axi_in.IDSIZE)
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)bid_data_pipe_inst(
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/* input */ .clock (axi_in.axi_aclk ),
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/* input */ .rst_n (axi_in.axi_aresetn ),
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/* input [DSIZE-1:0] */ .indata (axi_out.axi_bid ),
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/* input */ .invalid (axi_out.axi_bvalid ),
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/* output logic */ .inready (axi_out.axi_bready ),
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/* output logic[DSIZE-1:0] */ .outdata (axi_in.axi_bid ),
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/* input logic */ .outvalid (axi_in.axi_bvalid ),
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/* input */ .outready (axi_in.axi_bready )
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);
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endgenerate
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int slim_wcnt;
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int wide_wcnt;
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int slim_rcnt;
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int wide_rcnt;
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assign slim_wcnt = axi_in.axi_wcnt;
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assign wide_wcnt = axi_out.axi_wcnt;
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assign slim_rcnt = axi_in.axi_rcnt;
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assign wide_rcnt = axi_out.axi_rcnt;
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generate
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if(SLAVER_MODE == "ONLY_WRITE")begin
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assign axi_out.axi_arid = '0;
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assign axi_out.axi_araddr = '0;
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assign axi_out.axi_arlen = '0;
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assign axi_out.axi_arsize = '0;
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assign axi_out.axi_arburst = '0;
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assign axi_out.axi_arlock = '0;
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assign axi_out.axi_arcache = '0;
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assign axi_out.axi_arprot = '0;
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assign axi_out.axi_arqos = '0;
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assign axi_out.axi_arvalid = '0;
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assign axi_in.axi_arready = 1'b1;
|
250
|
+
assign axi_out.axi_rready = 1'b1 ;
|
251
|
+
assign axi_in.axi_rid = '0;
|
252
|
+
assign axi_in.axi_rdata = '0;
|
253
|
+
assign axi_in.axi_rresp = '0;
|
254
|
+
assign axi_in.axi_rlast = '0;
|
255
|
+
assign axi_in.axi_rvalid = '0;
|
256
|
+
end else if(SLAVER_MODE == "ONLY_READ")begin
|
257
|
+
assign axi_out.axi_awid = '0;
|
258
|
+
assign axi_out.axi_awaddr = '0;
|
259
|
+
assign axi_out.axi_awlen = '0;
|
260
|
+
assign axi_out.axi_awsize = '0;
|
261
|
+
assign axi_out.axi_awburst = '0;
|
262
|
+
assign axi_out.axi_awlock = '0;
|
263
|
+
assign axi_out.axi_awcache = '0;
|
264
|
+
assign axi_out.axi_awprot = '0;
|
265
|
+
assign axi_out.axi_awqos = '0;
|
266
|
+
assign axi_out.axi_awvalid = '0;
|
267
|
+
assign axi_in.axi_awready = 1'b1;
|
268
|
+
assign axi_out.axi_wdata = '0;
|
269
|
+
assign axi_out.axi_wstrb = '0;
|
270
|
+
assign axi_out.axi_wlast = '0;
|
271
|
+
assign axi_out.axi_wvalid = '0;
|
272
|
+
assign axi_in.axi_wready = 1'b1 ;
|
273
|
+
assign axi_out.axi_bready = 1'b1 ;
|
274
|
+
assign axi_in.axi_bid = 1'b0;
|
275
|
+
assign axi_in.axi_bresp = 1'b0;
|
276
|
+
assign axi_in.axi_bvalid = 1'b0;
|
277
|
+
end
|
278
|
+
endgenerate
|
279
|
+
|
280
|
+
endmodule
|
@@ -0,0 +1,80 @@
|
|
1
|
+
/**********************************************
|
2
|
+
_______________________________________
|
3
|
+
___________ Cook Darwin __________
|
4
|
+
_______________________________________
|
5
|
+
descript:
|
6
|
+
author : Cook.Darwin
|
7
|
+
Version: VERA.0.0
|
8
|
+
creaded: 2017/1/3
|
9
|
+
madified:
|
10
|
+
***********************************************/
|
11
|
+
`timescale 1ns/1ps
|
12
|
+
(* axi_stream = "true" *)
|
13
|
+
module axi_stream_interconnect_M2S_cpVCS #(
|
14
|
+
parameter NUM = 8,
|
15
|
+
parameter PDSIZE = 8, //m00.DSIZE+1+1+m00.KSIZE
|
16
|
+
parameter NSIZE = NUM <= 2? 1 :
|
17
|
+
NUM <= 4? 2 :
|
18
|
+
NUM <= 8? 3 :
|
19
|
+
NUM <= 16?4 : 5
|
20
|
+
)(
|
21
|
+
input [NSIZE-1:0] addr,
|
22
|
+
axi_stream_inf.slaver s00 [NUM-1:0],
|
23
|
+
axi_stream_inf.master m00
|
24
|
+
);
|
25
|
+
|
26
|
+
// initial begin
|
27
|
+
// $error("axi_stream_interconnect_M2S has be abandon,pleace use axi_stream_interconnect_M2S_with_addr");
|
28
|
+
// $stop;
|
29
|
+
// end
|
30
|
+
|
31
|
+
// localparam DSIZE = m00.DSIZE;
|
32
|
+
// localparam KSIZE = (m00.DSIZE/8 > 0)? m00.DSIZE/8 : 1;
|
33
|
+
|
34
|
+
// data_inf #(.DSIZE(m00.DSIZE+1+1+m00.KSIZE) ) s00_data_inf [NUM-1:0] ();
|
35
|
+
// data_inf #(.DSIZE(m00.DSIZE+1+1+m00.KSIZE) ) m00_data_inf ();
|
36
|
+
|
37
|
+
data_inf #(.DSIZE(PDSIZE) ) s00_data_inf [NUM-1:0] ();
|
38
|
+
data_inf #(.DSIZE(PDSIZE) ) m00_data_inf ();
|
39
|
+
|
40
|
+
genvar KK;
|
41
|
+
generate
|
42
|
+
for(KK=0;KK<NUM;KK++)begin
|
43
|
+
assign s00_data_inf[KK].valid = s00[KK].axis_tvalid;
|
44
|
+
assign s00_data_inf[KK].data = {s00[KK].axis_tkeep,s00[KK].axis_tuser,s00[KK].axis_tlast,s00[KK].axis_tdata};
|
45
|
+
// assign s00_data_inf[KK].data[m00.DSIZE-1:0] = s00[KK].axis_tdata;
|
46
|
+
// assign s00_data_inf[KK].data[m00.DSIZE] = s00[KK].axis_tlast;
|
47
|
+
// assign s00_data_inf[KK].data[m00.DSIZE+1] = s00[KK].axis_tuser;
|
48
|
+
// assign s00_data_inf[KK].data[m00.DSIZE+m00.KSIZE+1-:m00.KSIZE] = s00[KK].axis_tkeep;
|
49
|
+
assign s00[KK].axis_tready = s00_data_inf[KK].ready;
|
50
|
+
end
|
51
|
+
endgenerate
|
52
|
+
`include "define_macro.sv"
|
53
|
+
`ifdef VIVADO_ENV
|
54
|
+
localparam DSIZE = PDSIZE;
|
55
|
+
`endif
|
56
|
+
|
57
|
+
data_pipe_interconnect_M2S_verb #(
|
58
|
+
`ifdef VIVADO_ENV
|
59
|
+
.DSIZE (DSIZE ),
|
60
|
+
`else
|
61
|
+
.DSIZE (PDSIZE ),
|
62
|
+
`endif
|
63
|
+
.NUM (NUM )
|
64
|
+
)data_pipe_interconnect_M2S_verb_inst(
|
65
|
+
/* input */ .clock (m00.aclk ),
|
66
|
+
/* input */ .rst_n (m00.aresetn ),
|
67
|
+
/* input */ .clk_en (m00.aclken ),
|
68
|
+
/* input [NSIZE-1:0] */ .addr (addr ),
|
69
|
+
/* data_inf.slaver */ .s00 (s00_data_inf ),
|
70
|
+
/* data_inf.master */ .m00 (m00_data_inf )
|
71
|
+
);
|
72
|
+
|
73
|
+
assign m00.axis_tdata = m00_data_inf.data[m00.DSIZE-1:0];
|
74
|
+
assign m00.axis_tvalid = m00_data_inf.valid;
|
75
|
+
assign m00.axis_tlast = m00_data_inf.data[m00.DSIZE];
|
76
|
+
assign m00.axis_tuser = m00_data_inf.data[m00.DSIZE+1];
|
77
|
+
assign m00_data_inf.ready = m00.axis_tready;
|
78
|
+
assign m00.axis_tkeep = m00_data_inf.data[m00.DSIZE+m00.KSIZE+1-:m00.KSIZE];
|
79
|
+
|
80
|
+
endmodule
|
@@ -55,22 +55,22 @@ axis_direct axis_direct_end_inf_inst0 (
|
|
55
55
|
);
|
56
56
|
//-------- CLOCKs Total 3 ----------------------
|
57
57
|
//--->> CheckClock <<----------------
|
58
|
-
logic
|
59
|
-
integer
|
60
|
-
ClockSameDomain
|
58
|
+
logic cc_done_7,cc_same_7;
|
59
|
+
integer cc_afreq_7,cc_bfreq_7;
|
60
|
+
ClockSameDomain CheckPClock_inst_7(
|
61
61
|
/* input */ .aclk (origin_inf.aclk ),
|
62
62
|
/* input */ .bclk (first_inf.aclk ),
|
63
|
-
/* output logic */ .done (
|
64
|
-
/* output logic */ .same (
|
65
|
-
/* output integer */ .aFreqK (
|
66
|
-
/* output integer */ .bFreqK (
|
63
|
+
/* output logic */ .done (cc_done_7),
|
64
|
+
/* output logic */ .same (cc_same_7),
|
65
|
+
/* output integer */ .aFreqK (cc_afreq_7),
|
66
|
+
/* output integer */ .bFreqK (cc_bfreq_7)
|
67
67
|
);
|
68
68
|
|
69
69
|
initial begin
|
70
|
-
wait(
|
71
|
-
assert(
|
70
|
+
wait(cc_done_7);
|
71
|
+
assert(cc_same_7)
|
72
72
|
else begin
|
73
|
-
$error("--- Error : `axi_stream_split_channel` clock is not same, origin_inf.aclk< %0f M> != first_inf.aclk<%0f M>",1000000.0/
|
73
|
+
$error("--- Error : `axi_stream_split_channel` clock is not same, origin_inf.aclk< %0f M> != first_inf.aclk<%0f M>",1000000.0/cc_afreq_7, 1000000.0/cc_bfreq_7);
|
74
74
|
repeat(10)begin
|
75
75
|
@(posedge origin_inf.aclk);
|
76
76
|
end
|
@@ -80,22 +80,22 @@ end
|
|
80
80
|
//---<< CheckClock >>----------------
|
81
81
|
|
82
82
|
//--->> CheckClock <<----------------
|
83
|
-
logic
|
84
|
-
integer
|
85
|
-
ClockSameDomain
|
83
|
+
logic cc_done_8,cc_same_8;
|
84
|
+
integer cc_afreq_8,cc_bfreq_8;
|
85
|
+
ClockSameDomain CheckPClock_inst_8(
|
86
86
|
/* input */ .aclk (origin_inf.aclk ),
|
87
87
|
/* input */ .bclk (end_inf.aclk ),
|
88
|
-
/* output logic */ .done (
|
89
|
-
/* output logic */ .same (
|
90
|
-
/* output integer */ .aFreqK (
|
91
|
-
/* output integer */ .bFreqK (
|
88
|
+
/* output logic */ .done (cc_done_8),
|
89
|
+
/* output logic */ .same (cc_same_8),
|
90
|
+
/* output integer */ .aFreqK (cc_afreq_8),
|
91
|
+
/* output integer */ .bFreqK (cc_bfreq_8)
|
92
92
|
);
|
93
93
|
|
94
94
|
initial begin
|
95
|
-
wait(
|
96
|
-
assert(
|
95
|
+
wait(cc_done_8);
|
96
|
+
assert(cc_same_8)
|
97
97
|
else begin
|
98
|
-
$error("--- Error : `axi_stream_split_channel` clock is not same, origin_inf.aclk< %0f M> != end_inf.aclk<%0f M>",1000000.0/
|
98
|
+
$error("--- Error : `axi_stream_split_channel` clock is not same, origin_inf.aclk< %0f M> != end_inf.aclk<%0f M>",1000000.0/cc_afreq_8, 1000000.0/cc_bfreq_8);
|
99
99
|
repeat(10)begin
|
100
100
|
@(posedge origin_inf.aclk);
|
101
101
|
end
|
@@ -49,15 +49,28 @@ gen_big_field_table #(
|
|
49
49
|
end
|
50
50
|
endgenerate
|
51
51
|
|
52
|
+
logic end_enable;
|
53
|
+
always@(posedge end_inf.aclk) begin
|
54
|
+
if(~end_inf.aresetn)
|
55
|
+
end_enable <= 1'b0;
|
56
|
+
else begin
|
57
|
+
if(origin_in.axis_tvalid && origin_in.axis_tready)
|
58
|
+
end_enable <= (MODE=="BOTH" || MODE=="END");
|
59
|
+
else if(end_inf.axis_tvalid && end_inf.axis_tlast && end_inf.axis_tready)
|
60
|
+
end_enable <= 1'b0;
|
61
|
+
else end_enable <= end_enable;
|
62
|
+
end
|
63
|
+
end
|
64
|
+
|
52
65
|
generate
|
53
66
|
if(MODE=="BOTH" || MODE=="END")begin
|
54
67
|
gen_big_field_table #(
|
55
|
-
.MASTER_MODE ("
|
68
|
+
.MASTER_MODE ("ON" ),
|
56
69
|
.DSIZE (DSIZE ),
|
57
70
|
.FIELD_LEN (END_FIELD_LEN ), //MAX 16*8
|
58
71
|
.FIELD_NAME (END_FIELD_NAME )
|
59
72
|
)gen_big_field_table_end(
|
60
|
-
/* input */ .enable (
|
73
|
+
/* input */ .enable (end_enable ),
|
61
74
|
/* input [DSIZE*FIELD_LEN-1:0] */ .value (end_value ),
|
62
75
|
/* axi_stream_inf.master */ .cm_tb (end_inf )
|
63
76
|
);
|
@@ -5,7 +5,7 @@ _______________________________________
|
|
5
5
|
descript:
|
6
6
|
author : Cook.Darwin
|
7
7
|
Version: VERA.0.0
|
8
|
-
|
8
|
+
creaded: XXXX.XX.XX
|
9
9
|
madified:
|
10
10
|
***********************************************/
|
11
11
|
`timescale 1ns/1ps
|
@@ -38,17 +38,17 @@ gen_origin_axis_A2 #(
|
|
38
38
|
//==========================================================================
|
39
39
|
//-------- expression ------------------------------------------------------
|
40
40
|
initial begin
|
41
|
-
assert(
|
42
|
-
|
43
|
-
|
41
|
+
assert(axis_zip.DSIZE==(ASIZE+LSIZE))else begin
|
42
|
+
$error(" axis_zip.DSIZE<%0d> != (param.ASIZE<%0d>+param.LSIZE<%0d>)",axis_zip.DSIZE,ASIZE,LSIZE);
|
43
|
+
$stop;
|
44
44
|
end
|
45
|
-
assert(
|
46
|
-
|
47
|
-
|
45
|
+
assert(axis_unzip.DSIZE==ASIZE)else begin
|
46
|
+
$error("axis_unzip.DSIZE<%0d> != param.ASIZE<%0d>",axis_unzip.DSIZE,ASIZE);
|
47
|
+
$stop;
|
48
48
|
end
|
49
49
|
end
|
50
50
|
|
51
|
-
assign
|
52
|
-
assign
|
51
|
+
assign cc_length = axis_zip.axis_tdata[LSIZE-1:0]+1'b1;
|
52
|
+
assign cc_start = axis_zip.axis_tdata[ASIZE+LSIZE-1:LSIZE];
|
53
53
|
|
54
54
|
endmodule
|
@@ -17,9 +17,10 @@ madified:
|
|
17
17
|
module parse_big_field_table_verb #(
|
18
18
|
parameter DSIZE = 8,
|
19
19
|
parameter FIELD_LEN = 16*8, //MAX 16*8
|
20
|
-
parameter TRY_PARSE = "OFF"
|
20
|
+
parameter TRY_PARSE = "OFF",
|
21
|
+
parameter START_INDEX = 0
|
21
22
|
)(
|
22
|
-
output logic[
|
23
|
+
output logic[START_INDEX:DSIZE*FIELD_LEN-1] value,
|
23
24
|
output logic out_valid,
|
24
25
|
axi_stream_inf.slaver cm_tb_s,
|
25
26
|
axi_stream_inf.master cm_tb_m,
|
@@ -48,22 +48,22 @@ for(genvar KK0=0;KK0 < LAT;KK0++)begin
|
|
48
48
|
endgenerate
|
49
49
|
//-------- CLOCKs Total 2 ----------------------
|
50
50
|
//--->> CheckClock <<----------------
|
51
|
-
logic
|
52
|
-
integer
|
53
|
-
ClockSameDomain
|
51
|
+
logic cc_done_9,cc_same_9;
|
52
|
+
integer cc_afreq_9,cc_bfreq_9;
|
53
|
+
ClockSameDomain CheckPClock_inst_9(
|
54
54
|
/* input */ .aclk (in_inf.clock ),
|
55
55
|
/* input */ .bclk (out_inf.clock ),
|
56
|
-
/* output logic */ .done (
|
57
|
-
/* output logic */ .same (
|
58
|
-
/* output integer */ .aFreqK (
|
59
|
-
/* output integer */ .bFreqK (
|
56
|
+
/* output logic */ .done (cc_done_9),
|
57
|
+
/* output logic */ .same (cc_same_9),
|
58
|
+
/* output integer */ .aFreqK (cc_afreq_9),
|
59
|
+
/* output integer */ .bFreqK (cc_bfreq_9)
|
60
60
|
);
|
61
61
|
|
62
62
|
initial begin
|
63
|
-
wait(
|
64
|
-
assert(
|
63
|
+
wait(cc_done_9);
|
64
|
+
assert(cc_same_9)
|
65
65
|
else begin
|
66
|
-
$error("--- Error : `data_c_pipe_sync_seam` clock is not same, in_inf.clock< %0f M> != out_inf.clock<%0f M>",1000000.0/
|
66
|
+
$error("--- Error : `data_c_pipe_sync_seam` clock is not same, in_inf.clock< %0f M> != out_inf.clock<%0f M>",1000000.0/cc_afreq_9, 1000000.0/cc_bfreq_9);
|
67
67
|
repeat(10)begin
|
68
68
|
@(posedge in_inf.clock);
|
69
69
|
end
|
@@ -130,7 +130,8 @@ always_comb begin
|
|
130
130
|
else nstate = END_EM_CN_EM_BUF;
|
131
131
|
END_VD_CN_EM_BUF:
|
132
132
|
case({m00_vld_rdy,end_vld_rdy})
|
133
|
-
2'b00: nstate = end_last? FSH_VD_CN_EM_BUF : END_VD_CN_EM_BUF;
|
133
|
+
// 2'b00: nstate = end_last? FSH_VD_CN_EM_BUF : END_VD_CN_EM_BUF;
|
134
|
+
2'b00: nstate = END_VD_CN_EM_BUF;
|
134
135
|
2'b10: nstate = END_EM_CN_EM_BUF;
|
135
136
|
2'b01: nstate = end_last? FSH_VD_CN_VD_BUF : END_VD_CN_VD_BUF;
|
136
137
|
2'b11: nstate = end_last? FSH_VD_CN_EM_BUF : END_VD_CN_EM_BUF;
|
@@ -6,7 +6,7 @@ interface axi_inf #(
|
|
6
6
|
parameter LSIZE = 1,
|
7
7
|
parameter DSIZE = 32,
|
8
8
|
`parameter_string MODE = "BOTH", //BOTH:0,ONLY_WRITE:1,ONLY_READ:2
|
9
|
-
parameter ADDR_STEP = 32'hFFFF_FFFF, // 1024
|
9
|
+
parameter ADDR_STEP = 32'hFFFF_FFFF, // 1024*2 地址递增 1 则 数据对于 数据移动 axi.DSIZE*2
|
10
10
|
parameter real FreqM = 1
|
11
11
|
)(
|
12
12
|
input bit axi_aclk ,
|