axi_tdl 0.1.20 → 0.2.0

data/lib/axi/AXI4/width_convert/axi4_data_convert_verb.sv

@@ -0,0 +1,280 @@
+/**********************************************
+_______________________________________ 
+___________    Cook Darwin   __________    
+_______________________________________
+descript:
+author : Cook.Darwin
+Version: VERA.1.0 2017/5/23 
+    use width convert verb
+Version: VERB.0.0 2021/10
+    explicit mode
+creaded: 2017/2/20 
+madified:
+***********************************************/
+`timescale 1ns/1ps
+`include "define_macro.sv"
+module  axi4_data_convert_verb #(
+    `parameter_string SLAVER_MODE  = "BOTH",    //
+    `parameter_string MASTER_MODE  = "BOTH"   //
+)(
+    axi_inf.slaver axi_in,
+    axi_inf.master axi_out
+);
+
+import SystemPkg::*;
+
+initial begin
+    assert(axi_in.MODE == axi_out.MODE)
+    else begin
+        $error("SLAVER AXI4 MODE != MASTER AXI4 MODE");
+        $stop;
+    end
+
+    assert(SLAVER_MODE == MASTER_MODE)
+    else begin 
+        $error("SLAVER AXI4 MODE<%0s> != MASTER AXI4 MODE<%0s>",SLAVER_MODE, MASTER_MODE);
+        $stop;
+    end
+
+    assert(SLAVER_MODE == axi_out.MODE && SLAVER_MODE == axi_in.MODE)
+    else begin 
+        $error("SLAVER AXI4 MODE<%0s> != MASTER AXI4 MODE<%0s>",SLAVER_MODE, MASTER_MODE);
+        $stop;
+    end
+    
+
+    assert(real'(axi_in.DSIZE)/axi_in.ADDR_STEP == real'(axi_out.DSIZE)/axi_out.ADDR_STEP)
+    else begin
+        // $error("SLAVER ADDR STEP DONT MATCH MASTER");
+        $error("SLAVER ADDR STEP [%d][%d] DONT MATCH MASTER[%d][%d]",axi_in.DSIZE,axi_in.ADDR_STEP,axi_out.DSIZE,axi_out.ADDR_STEP);
+        $finish;
+    end
+
+end
+
+generate
+if(SLAVER_MODE=="BOTH" || SLAVER_MODE=="ONLY_WRITE")begin:AW_BLOCK
+    axi4_data_combin_aflag_pipe_A1 #(
+        .MODE       ("WRITE"        ),
+        .IDSIZE     (axi_in.IDSIZE  ),
+        .ASIZE      (axi_in.ASIZE   ),
+        .ILSIZE     (axi_in.LSIZE   ),
+        .OLSIZE     (axi_out.LSIZE  ),
+        .ISIZE      (axi_in.DSIZE   ),
+        .OSIZE      (axi_out.DSIZE  )
+    )axi4_data_combin_aflag_pipe_wr(
+    /*    input                 */      .clock        (axi_in.axi_aclk    ),
+    /*    input                 */      .rst_n        (axi_in.axi_aresetn  ),
+    /*    input[IDSIZE-1:0]     */      .in_a_id      (axi_in.axi_awid    ),
+    /*    input[ASIZE-1:0]      */      .in_a_addr    (axi_in.axi_awaddr  ),
+    /*    input[ILSIZE-1:0]     */      .in_a_len     (axi_in.axi_awlen   ),
+    /*    input[2:0]            */      .in_a_size    (axi_in.axi_awsize  ),
+    /*    input[1:0]            */      .in_a_burst   (axi_in.axi_awburst ),
+    /*    input[0:0]            */      .in_a_lock    (axi_in.axi_awlock  ),
+    /*    input[3:0]            */      .in_a_cache   (axi_in.axi_awcache ),
+    /*    input[2:0]            */      .in_a_prot    (axi_in.axi_awprot  ),
+    /*    input[3:0]            */      .in_a_qos     (axi_in.axi_awqos   ),
+    /*    input                 */      .in_a_valid   (axi_in.axi_awvalid ),
+    /*    output                */      .in_a_ready   (axi_in.axi_awready ),
+    /*    output[IDSIZE-1:0]    */      .out_a_id     (axi_out.axi_awid   ),
+    /*    output[ASIZE-1:0]     */      .out_a_addr   (axi_out.axi_awaddr ),
+    /*    output[OLSIZE-1:0]    */      .out_a_len    (axi_out.axi_awlen  ),
+    /*    output[2:0]           */      .out_a_size   (axi_out.axi_awsize ),
+    /*    output[1:0]           */      .out_a_burst  (axi_out.axi_awburst),
+    /*    output[0:0]           */      .out_a_lock   (axi_out.axi_awlock ),
+    /*    output[3:0]           */      .out_a_cache  (axi_out.axi_awcache),
+    /*    output[2:0]           */      .out_a_prot   (axi_out.axi_awprot ),
+    /*    output[3:0]           */      .out_a_qos    (axi_out.axi_awqos  ),
+    /*    output                */      .out_a_valid  (axi_out.axi_awvalid),
+    /*    input                 */      .out_a_ready  (axi_out.axi_awready)
+    );
+end
+endgenerate
+
+generate
+if(SLAVER_MODE=="BOTH" || SLAVER_MODE=="ONLY_READ")begin:AR_BLOCK
+    axi4_data_combin_aflag_pipe_A1 #(
+        .MODE       ("READ"         ),
+        .IDSIZE     (axi_in.IDSIZE  ),
+        .ASIZE      (axi_in.ASIZE   ),
+        .ILSIZE     (axi_in.LSIZE   ),
+        .OLSIZE     (axi_out.LSIZE  ),
+        .ISIZE      (axi_in.DSIZE   ),
+        .OSIZE      (axi_out.DSIZE  )
+    )axi4_data_combin_aflag_pipe_rd(
+    /*    input                 */      .clock        (axi_in.axi_aclk    ),
+    /*    input                 */      .rst_n        (axi_in.axi_aresetn  ),
+    /*    input[IDSIZE-1:0]     */      .in_a_id      (axi_in.axi_arid    ),
+    /*    input[ASIZE-1:0]      */      .in_a_addr    (axi_in.axi_araddr  ),
+    /*    input[ILSIZE-1:0]     */      .in_a_len     (axi_in.axi_arlen   ),
+    /*    input[2:0]            */      .in_a_size    (axi_in.axi_arsize  ),
+    /*    input[1:0]            */      .in_a_burst   (axi_in.axi_arburst ),
+    /*    input[0:0]            */      .in_a_lock    (axi_in.axi_arlock  ),
+    /*    input[3:0]            */      .in_a_cache   (axi_in.axi_arcache ),
+    /*    input[2:0]            */      .in_a_prot    (axi_in.axi_arprot  ),
+    /*    input[3:0]            */      .in_a_qos     (axi_in.axi_arqos   ),
+    /*    input                 */      .in_a_valid   (axi_in.axi_arvalid ),
+    /*    output                */      .in_a_ready   (axi_in.axi_arready ),
+    /*    output[IDSIZE-1:0]    */      .out_a_id     (axi_out.axi_arid   ),
+    /*    output[ASIZE-1:0]     */      .out_a_addr   (axi_out.axi_araddr ),
+    /*    output[OLSIZE-1:0]    */      .out_a_len    (axi_out.axi_arlen  ),
+    /*    output[2:0]           */      .out_a_size   (axi_out.axi_arsize ),
+    /*    output[1:0]           */      .out_a_burst  (axi_out.axi_arburst),
+    /*    output[0:0]           */      .out_a_lock   (axi_out.axi_arlock ),
+    /*    output[3:0]           */      .out_a_cache  (axi_out.axi_arcache),
+    /*    output[2:0]           */      .out_a_prot   (axi_out.axi_arprot ),
+    /*    output[3:0]           */      .out_a_qos    (axi_out.axi_arqos  ),
+    /*    output                */      .out_a_valid  (axi_out.axi_arvalid),
+    /*    input                 */      .out_a_ready  (axi_out.axi_arready)
+    );
+end
+endgenerate
+
+generate
+if(SLAVER_MODE=="BOTH" || SLAVER_MODE=="ONLY_WRITE")begin:WDATA_BLOCK
+    width_convert_verb #(
+        .ISIZE      (axi_in.DSIZE  ),
+        .OSIZE      (axi_out.DSIZE )
+    )width_convert_wr(
+    /*    input                         */  .clock             (axi_in.axi_aclk    ),
+    /*    input                         */  .rst_n             (axi_in.axi_aresetn  ),
+    /*    input [DSIZE-1:0]             */  .wr_data           (axi_in.axi_wdata   ),
+    /*    input                         */  .wr_vld            (axi_in.axi_wvalid  ),
+    /*    output logic                  */  .wr_ready          (axi_in.axi_wready  ),
+    /*    input                         */  .wr_last           (axi_in.axi_wlast   ),
+    /*    input                         */  .wr_align_last     (1'b0               ),
+    /*    output logic[DSIZE*NSIZE-1:0] */  .rd_data           (axi_out.axi_wdata  ),
+    /*    output logic                  */  .rd_vld            (axi_out.axi_wvalid ),
+    /*    input                         */  .rd_ready          (axi_out.axi_wready ),
+    /*    output logic                  */  .rd_last           (axi_out.axi_wlast  )
+    );
+end
+endgenerate
+
+generate
+if(SLAVER_MODE=="BOTH" || SLAVER_MODE=="ONLY_READ")begin:RDATA_BLOCK
+    width_convert_verb #(
+        .ISIZE      (axi_out.DSIZE  ),
+        .OSIZE      (axi_in.DSIZE   )
+    )width_convert_rd(
+    /*    input                         */  .clock             (axi_in.axi_aclk    ),
+    /*    input                         */  .rst_n             (axi_in.axi_aresetn  ),
+    /*    input [DSIZE-1:0]             */  .wr_data           (axi_out.axi_rdata  ),
+    /*    input                         */  .wr_vld            (axi_out.axi_rvalid ),
+    /*    output logic                  */  .wr_ready          (axi_out.axi_rready ),
+    /*    input                         */  .wr_last           (axi_out.axi_rlast  ),
+    /*    input                         */  .wr_align_last     (1'b0               ),
+    /*    output logic[DSIZE*NSIZE-1:0] */  .rd_data           (axi_in.axi_rdata   ),
+    /*    output logic                  */  .rd_vld            (axi_in.axi_rvalid  ),
+    /*    input                         */  .rd_ready          (axi_in.axi_rready  ),
+    /*    output logic                  */  .rd_last           (axi_in.axi_rlast   )
+    );
+end
+endgenerate
+
+generate
+if(SLAVER_MODE=="BOTH" || SLAVER_MODE=="ONLY_READ")
+simple_data_pipe_slaver #(
+    .DSIZE          (axi_in.IDSIZE)
+)rid_data_pipe_inst(
+/*    input                    */   .clock       (axi_in.axi_aclk    ),
+/*    input                    */   .rst_n       (axi_in.axi_aresetn  ),
+/*    input [DSIZE-1:0]        */   .indata      (axi_out.axi_rid    ),
+/*    input                    */   .invalid     (axi_out.axi_rvalid ),
+/*    output logic             */   .inready     (axi_out.axi_rready ),
+/*    output logic[DSIZE-1:0]  */   .outdata     (axi_in.axi_rid     ),
+/*    inpit  logic             */   .outvalid    (axi_in.axi_rvalid  ),
+/*    input                    */   .outready    (axi_in.axi_rready  )
+);
+endgenerate
+//----<< READ ID >>------------
+
+generate
+if(SLAVER_MODE=="BOTH" || SLAVER_MODE=="ONLY_WRITE")
+simple_data_pipe #(
+    .DSIZE          (2)
+)bresp_data_pipe_inst(
+/*    input                    */   .clock       (axi_in.axi_aclk    ),
+/*    input                    */   .rst_n       (axi_in.axi_aresetn  ),
+/*    input [DSIZE-1:0]        */   .indata      (axi_out.axi_bresp  ),
+/*    input                    */   .invalid     (axi_out.axi_bvalid ),
+/*    output logic             */   .inready     (axi_out.axi_bready ),
+/*    output logic[DSIZE-1:0]  */   .outdata     (axi_in.axi_bresp   ),
+/*    output logic             */   .outvalid    (axi_in.axi_bvalid  ),
+/*    input                    */   .outready    (axi_in.axi_bready  )
+);
+endgenerate
+
+generate
+if(SLAVER_MODE=="BOTH" || SLAVER_MODE=="ONLY_WRITE")
+simple_data_pipe_slaver #(
+    .DSIZE          (axi_in.IDSIZE)
+)bid_data_pipe_inst(
+/*    input                    */   .clock       (axi_in.axi_aclk    ),
+/*    input                    */   .rst_n       (axi_in.axi_aresetn  ),
+/*    input [DSIZE-1:0]        */   .indata      (axi_out.axi_bid    ),
+/*    input                    */   .invalid     (axi_out.axi_bvalid ),
+/*    output logic             */   .inready     (axi_out.axi_bready ),
+/*    output logic[DSIZE-1:0]  */   .outdata     (axi_in.axi_bid     ),
+/*    input  logic             */   .outvalid    (axi_in.axi_bvalid  ),
+/*    input                    */   .outready    (axi_in.axi_bready  )
+);
+endgenerate
+
+int         slim_wcnt;
+int         wide_wcnt;
+
+int         slim_rcnt;
+int         wide_rcnt;
+
+assign slim_wcnt    = axi_in.axi_wcnt;
+assign wide_wcnt    = axi_out.axi_wcnt;
+
+assign slim_rcnt    = axi_in.axi_rcnt;
+assign wide_rcnt    = axi_out.axi_rcnt;
+
+
+generate
+    if(SLAVER_MODE == "ONLY_WRITE")begin 
+        assign axi_out.axi_arid     = '0;
+        assign axi_out.axi_araddr   = '0;
+        assign axi_out.axi_arlen    = '0;
+        assign axi_out.axi_arsize   = '0;
+        assign axi_out.axi_arburst  = '0;
+        assign axi_out.axi_arlock   = '0;
+        assign axi_out.axi_arcache  = '0;
+        assign axi_out.axi_arprot   = '0;
+        assign axi_out.axi_arqos    = '0;
+        assign axi_out.axi_arvalid  = '0;
+        assign axi_in.axi_arready   = 1'b1;
+        assign axi_out.axi_rready   = 1'b1 ;
+        assign axi_in.axi_rid      = '0;
+        assign axi_in.axi_rdata    = '0;
+        assign axi_in.axi_rresp    = '0;
+        assign axi_in.axi_rlast    = '0;
+        assign axi_in.axi_rvalid   = '0;
+    end else if(SLAVER_MODE == "ONLY_READ")begin 
+        assign axi_out.axi_awid     = '0;
+        assign axi_out.axi_awaddr   = '0;
+        assign axi_out.axi_awlen    = '0;
+        assign axi_out.axi_awsize   = '0;
+        assign axi_out.axi_awburst  = '0;
+        assign axi_out.axi_awlock   = '0;
+        assign axi_out.axi_awcache  = '0;
+        assign axi_out.axi_awprot   = '0;
+        assign axi_out.axi_awqos    = '0;
+        assign axi_out.axi_awvalid  = '0;
+        assign axi_in.axi_awready   = 1'b1;
+        assign axi_out.axi_wdata    = '0;
+        assign axi_out.axi_wstrb    = '0;
+        assign axi_out.axi_wlast    = '0;
+        assign axi_out.axi_wvalid   = '0;
+        assign axi_in.axi_wready   = 1'b1 ;
+        assign axi_out.axi_bready   = 1'b1 ;
+        assign axi_in.axi_bid      = 1'b0;
+        assign axi_in.axi_bresp    = 1'b0;
+        assign axi_in.axi_bvalid   = 1'b0;
+    end
+endgenerate
+
+endmodule

data/lib/axi/AXI_stream/axi_stream_interconnect_M2S_cpVCS.sv

@@ -0,0 +1,80 @@
+/**********************************************
+_______________________________________ 
+___________    Cook Darwin   __________    
+_______________________________________
+descript:
+author : Cook.Darwin
+Version: VERA.0.0
+creaded: 2017/1/3 
+madified:
+***********************************************/
+`timescale 1ns/1ps
+(* axi_stream = "true" *)
+module axi_stream_interconnect_M2S_cpVCS  #(
+    parameter   NUM   = 8,
+    parameter   PDSIZE = 8, //m00.DSIZE+1+1+m00.KSIZE
+    parameter   NSIZE =  NUM <= 2? 1 :
+                         NUM <= 4? 2 :
+                         NUM <= 8? 3 :
+                         NUM <= 16?4 : 5
+)(
+    input [NSIZE-1:0]      addr,
+    axi_stream_inf.slaver  s00 [NUM-1:0],
+    axi_stream_inf.master  m00
+);
+
+// initial begin
+//     $error("axi_stream_interconnect_M2S has be abandon,pleace use axi_stream_interconnect_M2S_with_addr");
+//     $stop;
+// end
+
+// localparam  DSIZE   = m00.DSIZE;
+// localparam  KSIZE   = (m00.DSIZE/8 > 0)? m00.DSIZE/8 : 1;
+
+// data_inf #(.DSIZE(m00.DSIZE+1+1+m00.KSIZE) ) s00_data_inf [NUM-1:0] ();
+// data_inf #(.DSIZE(m00.DSIZE+1+1+m00.KSIZE) ) m00_data_inf ();
+
+data_inf #(.DSIZE(PDSIZE) ) s00_data_inf [NUM-1:0] ();
+data_inf #(.DSIZE(PDSIZE) ) m00_data_inf ();
+
+genvar KK;
+generate
+for(KK=0;KK<NUM;KK++)begin
+assign s00_data_inf[KK].valid                                   = s00[KK].axis_tvalid;
+assign s00_data_inf[KK].data                                    = {s00[KK].axis_tkeep,s00[KK].axis_tuser,s00[KK].axis_tlast,s00[KK].axis_tdata};
+// assign s00_data_inf[KK].data[m00.DSIZE-1:0]                     = s00[KK].axis_tdata;
+// assign s00_data_inf[KK].data[m00.DSIZE]                         = s00[KK].axis_tlast;
+// assign s00_data_inf[KK].data[m00.DSIZE+1]                       = s00[KK].axis_tuser;
+// assign s00_data_inf[KK].data[m00.DSIZE+m00.KSIZE+1-:m00.KSIZE]  = s00[KK].axis_tkeep;
+assign s00[KK].axis_tready                                      = s00_data_inf[KK].ready;
+end
+endgenerate
+`include "define_macro.sv"
+`ifdef VIVADO_ENV
+localparam DSIZE = PDSIZE;
+`endif
+
+data_pipe_interconnect_M2S_verb #(
+`ifdef VIVADO_ENV
+    .DSIZE      (DSIZE     ),
+`else
+    .DSIZE      (PDSIZE     ),
+`endif
+    .NUM        (NUM       )
+)data_pipe_interconnect_M2S_verb_inst(
+/*    input                 */    .clock            (m00.aclk       ),
+/*    input                 */    .rst_n            (m00.aresetn    ),
+/*    input                 */    .clk_en           (m00.aclken     ),
+/*    input [NSIZE-1:0]     */    .addr             (addr           ),
+/*    data_inf.slaver       */    .s00              (s00_data_inf   ),
+/*    data_inf.master       */    .m00              (m00_data_inf   )
+);
+
+assign m00.axis_tdata            = m00_data_inf.data[m00.DSIZE-1:0];
+assign m00.axis_tvalid           = m00_data_inf.valid;
+assign m00.axis_tlast            = m00_data_inf.data[m00.DSIZE];
+assign m00.axis_tuser            = m00_data_inf.data[m00.DSIZE+1];
+assign m00_data_inf.ready        = m00.axis_tready;
+assign m00.axis_tkeep            = m00_data_inf.data[m00.DSIZE+m00.KSIZE+1-:m00.KSIZE];
+
+endmodule

data/lib/axi/AXI_stream/axi_stream_split_channel.sv

@@ -55,22 +55,22 @@ axis_direct  axis_direct_end_inf_inst0 (
 );
 //-------- CLOCKs Total 3 ----------------------
 //--->> CheckClock <<----------------
-logic cc_done_8,cc_same_8;
-integer cc_afreq_8,cc_bfreq_8;
-ClockSameDomain CheckPClock_inst_8(
+logic cc_done_7,cc_same_7;
+integer cc_afreq_7,cc_bfreq_7;
+ClockSameDomain CheckPClock_inst_7(
 /*  input         */      .aclk     (origin_inf.aclk        ),
 /*  input         */      .bclk     (first_inf.aclk         ),
-/*  output logic  */      .done     (cc_done_8),
-/*  output logic  */      .same     (cc_same_8),
-/*  output integer */     .aFreqK   (cc_afreq_8),
-/*  output integer */     .bFreqK   (cc_bfreq_8)
+/*  output logic  */      .done     (cc_done_7),
+/*  output logic  */      .same     (cc_same_7),
+/*  output integer */     .aFreqK   (cc_afreq_7),
+/*  output integer */     .bFreqK   (cc_bfreq_7)
 );
 
 initial begin
-    wait(cc_done_8);
-    assert(cc_same_8)
+    wait(cc_done_7);
+    assert(cc_same_7)
     else begin
-        $error("--- Error : `axi_stream_split_channel` clock is not same, origin_inf.aclk< %0f M> != first_inf.aclk<%0f M>",1000000.0/cc_afreq_8, 1000000.0/cc_bfreq_8);
+        $error("--- Error : `axi_stream_split_channel` clock is not same, origin_inf.aclk< %0f M> != first_inf.aclk<%0f M>",1000000.0/cc_afreq_7, 1000000.0/cc_bfreq_7);
         repeat(10)begin 
             @(posedge origin_inf.aclk);
         end
@@ -80,22 +80,22 @@ end
 //---<< CheckClock >>----------------
 
 //--->> CheckClock <<----------------
-logic cc_done_9,cc_same_9;
-integer cc_afreq_9,cc_bfreq_9;
-ClockSameDomain CheckPClock_inst_9(
+logic cc_done_8,cc_same_8;
+integer cc_afreq_8,cc_bfreq_8;
+ClockSameDomain CheckPClock_inst_8(
 /*  input         */      .aclk     (origin_inf.aclk        ),
 /*  input         */      .bclk     (end_inf.aclk           ),
-/*  output logic  */      .done     (cc_done_9),
-/*  output logic  */      .same     (cc_same_9),
-/*  output integer */     .aFreqK   (cc_afreq_9),
-/*  output integer */     .bFreqK   (cc_bfreq_9)
+/*  output logic  */      .done     (cc_done_8),
+/*  output logic  */      .same     (cc_same_8),
+/*  output integer */     .aFreqK   (cc_afreq_8),
+/*  output integer */     .bFreqK   (cc_bfreq_8)
 );
 
 initial begin
-    wait(cc_done_9);
-    assert(cc_same_9)
+    wait(cc_done_8);
+    assert(cc_same_8)
     else begin
-        $error("--- Error : `axi_stream_split_channel` clock is not same, origin_inf.aclk< %0f M> != end_inf.aclk<%0f M>",1000000.0/cc_afreq_9, 1000000.0/cc_bfreq_9);
+        $error("--- Error : `axi_stream_split_channel` clock is not same, origin_inf.aclk< %0f M> != end_inf.aclk<%0f M>",1000000.0/cc_afreq_8, 1000000.0/cc_bfreq_8);
         repeat(10)begin 
             @(posedge origin_inf.aclk);
         end

data/lib/axi/AXI_stream/axis_append_A1.sv

@@ -49,15 +49,28 @@ gen_big_field_table #(
 end
 endgenerate
 
+logic   end_enable;
+always@(posedge end_inf.aclk) begin 
+    if(~end_inf.aresetn)
+            end_enable  <= 1'b0;
+    else begin 
+        if(origin_in.axis_tvalid && origin_in.axis_tready)
+                end_enable  <= (MODE=="BOTH" || MODE=="END");
+        else if(end_inf.axis_tvalid && end_inf.axis_tlast && end_inf.axis_tready)
+                end_enable  <= 1'b0;
+        else    end_enable  <= end_enable;
+    end 
+end
+
 generate
 if(MODE=="BOTH" || MODE=="END")begin
 gen_big_field_table #(
-    .MASTER_MODE    ("OFF"               ),
+    .MASTER_MODE    ("ON"               ),
     .DSIZE          (DSIZE              ),
     .FIELD_LEN      (END_FIELD_LEN      ),     //MAX 16*8
     .FIELD_NAME     (END_FIELD_NAME     )
 )gen_big_field_table_end(
-/*  input                       */  .enable     (enable         ),
+/*  input                       */  .enable     (end_enable     ),
 /*  input [DSIZE*FIELD_LEN-1:0] */  .value      (end_value      ),
 /*  axi_stream_inf.master       */  .cm_tb      (end_inf        )
 );

data/lib/axi/AXI_stream/axis_uncompress_verb.sv

@@ -5,7 +5,7 @@ _______________________________________
 descript:
 author : Cook.Darwin
 Version: VERA.0.0
-created: xxxx.xx.xx
+creaded: XXXX.XX.XX
 madified:
 ***********************************************/
 `timescale 1ns/1ps
@@ -38,17 +38,17 @@ gen_origin_axis_A2 #(
 //==========================================================================
 //-------- expression ------------------------------------------------------
 initial begin
-    assert( axis_zip.DSIZE==( ASIZE+LSIZE))else begin
-         $error(" axis_zip.DSIZE<%0d> != (param.ASIZE<%0d>+param.LSIZE<%0d>)",axis_zip.DSIZE,ASIZE,LSIZE);
-         $stop;
+    assert(axis_zip.DSIZE==(ASIZE+LSIZE))else begin
+        $error(" axis_zip.DSIZE<%0d> != (param.ASIZE<%0d>+param.LSIZE<%0d>)",axis_zip.DSIZE,ASIZE,LSIZE);
+        $stop;
     end
-    assert( axis_unzip.DSIZE==ASIZE)else begin
-         $error("axis_unzip.DSIZE<%0d> != param.ASIZE<%0d>",axis_unzip.DSIZE,ASIZE);
-         $stop;
+    assert(axis_unzip.DSIZE==ASIZE)else begin
+        $error("axis_unzip.DSIZE<%0d> != param.ASIZE<%0d>",axis_unzip.DSIZE,ASIZE);
+        $stop;
     end
 end
 
-assign  cc_length = ( axis_zip.axis_tdata[ LSIZE-1:0]+1'b1);
-assign  cc_start = axis_zip.axis_tdata[ ASIZE+LSIZE-1:LSIZE];
+assign cc_length = axis_zip.axis_tdata[LSIZE-1:0]+1'b1;
+assign cc_start = axis_zip.axis_tdata[ASIZE+LSIZE-1:LSIZE];
 
 endmodule

data/lib/axi/AXI_stream/parse_big_field_table_verb.sv

@@ -17,9 +17,10 @@ madified:
 module parse_big_field_table_verb #(
     parameter   DSIZE         = 8,
     parameter   FIELD_LEN     = 16*8,     //MAX 16*8
-    parameter   TRY_PARSE     = "OFF"
+    parameter   TRY_PARSE     = "OFF",
+    parameter   START_INDEX   = 0
 )(
-    output logic[0:DSIZE*FIELD_LEN-1]       value,
+    output logic[START_INDEX:DSIZE*FIELD_LEN-1]       value,
     output logic                            out_valid,
     axi_stream_inf.slaver                   cm_tb_s,
     axi_stream_inf.master                   cm_tb_m,

data/lib/axi/data_interface/data_inf_c/data_c_pipe_sync_seam.sv

@@ -48,22 +48,22 @@ for(genvar KK0=0;KK0 < LAT;KK0++)begin
 endgenerate
 //-------- CLOCKs Total 2 ----------------------
 //--->> CheckClock <<----------------
-logic cc_done_10,cc_same_10;
-integer cc_afreq_10,cc_bfreq_10;
-ClockSameDomain CheckPClock_inst_10(
+logic cc_done_9,cc_same_9;
+integer cc_afreq_9,cc_bfreq_9;
+ClockSameDomain CheckPClock_inst_9(
 /*  input         */      .aclk     (in_inf.clock           ),
 /*  input         */      .bclk     (out_inf.clock          ),
-/*  output logic  */      .done     (cc_done_10),
-/*  output logic  */      .same     (cc_same_10),
-/*  output integer */     .aFreqK   (cc_afreq_10),
-/*  output integer */     .bFreqK   (cc_bfreq_10)
+/*  output logic  */      .done     (cc_done_9),
+/*  output logic  */      .same     (cc_same_9),
+/*  output integer */     .aFreqK   (cc_afreq_9),
+/*  output integer */     .bFreqK   (cc_bfreq_9)
 );
 
 initial begin
-    wait(cc_done_10);
-    assert(cc_same_10)
+    wait(cc_done_9);
+    assert(cc_same_9)
     else begin
-        $error("--- Error : `data_c_pipe_sync_seam` clock is not same, in_inf.clock< %0f M> != out_inf.clock<%0f M>",1000000.0/cc_afreq_10, 1000000.0/cc_bfreq_10);
+        $error("--- Error : `data_c_pipe_sync_seam` clock is not same, in_inf.clock< %0f M> != out_inf.clock<%0f M>",1000000.0/cc_afreq_9, 1000000.0/cc_bfreq_9);
         repeat(10)begin 
             @(posedge in_inf.clock);
         end

data/lib/axi/data_interface/data_inf_c/data_c_scaler_A1.sv

@@ -130,7 +130,8 @@ always_comb begin
         else    nstate  = END_EM_CN_EM_BUF;
     END_VD_CN_EM_BUF:
         case({m00_vld_rdy,end_vld_rdy})
-        2'b00:  nstate  = end_last? FSH_VD_CN_EM_BUF : END_VD_CN_EM_BUF;
+        // 2'b00:  nstate  = end_last? FSH_VD_CN_EM_BUF : END_VD_CN_EM_BUF;
+        2'b00:  nstate  = END_VD_CN_EM_BUF;
         2'b10:  nstate  = END_EM_CN_EM_BUF;
         2'b01:  nstate  = end_last? FSH_VD_CN_VD_BUF : END_VD_CN_VD_BUF;
         2'b11:  nstate  = end_last? FSH_VD_CN_EM_BUF : END_VD_CN_EM_BUF;

data/lib/axi/interface_define/axi_inf.sv

@@ -6,7 +6,7 @@ interface axi_inf #(
     parameter LSIZE     = 1,
     parameter DSIZE     = 32,
     `parameter_string MODE      = "BOTH",        //BOTH:0,ONLY_WRITE:1,ONLY_READ:2
-    parameter ADDR_STEP = 32'hFFFF_FFFF,            // 1024 : 0
+    parameter ADDR_STEP = 32'hFFFF_FFFF,            // 1024*2 地址递增 1 则 数据对于 数据移动 axi.DSIZE*2
     parameter real FreqM    = 1
 )(
     input bit axi_aclk      ,