axi_tdl 0.1.20 → 0.2.0
This diff represents the content of publicly available package versions that have been released to one of the supported registries. The information contained in this diff is provided for informational purposes only and reflects changes between package versions as they appear in their respective public registries.
- checksums.yaml +4 -4
- data/lib/axi/AXI4/axi4_direct_algin_addr_step.sv +223 -0
- data/lib/axi/AXI4/axi4_direct_verc.sv +54 -5
- data/lib/axi/AXI4/axi4_long_to_axi4_wide_B1.sv +146 -0
- data/lib/axi/AXI4/packet_fifo/axi4_packet_fifo_verb.sv +62 -0
- data/lib/axi/AXI4/packet_fifo/axi4_wr_packet_fifo.sv +4 -3
- data/lib/axi/AXI4/wide_axis_to_axi4_wr.sv +1 -1
- data/lib/axi/AXI4/width_convert/axi4_data_convert_verb.sv +280 -0
- data/lib/axi/AXI_stream/axi_stream_interconnect_M2S_cpVCS.sv +80 -0
- data/lib/axi/AXI_stream/axi_stream_split_channel.sv +20 -20
- data/lib/axi/AXI_stream/axis_append_A1.sv +15 -2
- data/lib/axi/AXI_stream/axis_uncompress_verb.sv +9 -9
- data/lib/axi/AXI_stream/parse_big_field_table_verb.sv +3 -2
- data/lib/axi/data_interface/data_inf_c/data_c_pipe_sync_seam.sv +10 -10
- data/lib/axi/data_interface/data_inf_c/data_c_scaler_A1.sv +2 -1
- data/lib/axi/interface_define/axi_inf.sv +1 -1
- data/lib/axi/macro/RTL/define_macro.sv +210 -0
- data/lib/axi/macro/SIM/define_macro.sv +194 -0
- data/lib/axi_tdl/version.rb +1 -1
- data/lib/tdl/auto_script/import_sdl.rb +3 -0
- data/lib/tdl/axi4/axi4_interconnect_verb.rb +76 -10
- data/lib/tdl/examples/11_test_unit/exp_test_unit.sv +7 -33
- data/lib/tdl/examples/11_test_unit/tb_exp_test_unit.sv +1 -1
- data/lib/tdl/examples/11_test_unit/tb_exp_test_unit_sim.sv +3 -14
- data/lib/tdl/examples/11_test_unit/tu0.sv +1 -1
- data/lib/tdl/examples/2_hdl_class/tmp/test_module_var.sv +2 -2
- data/lib/tdl/examples/2_hdl_class/tmp/test_vcs_string.sv +1 -1
- data/lib/tdl/examples/8_top_module/dve.tcl +0 -6
- data/lib/tdl/examples/8_top_module/test_top.sv +1 -1
- data/lib/tdl/examples/9_itegration/clock_manage/tu_ClockManage_test_clock_bb.sv +35 -0
- data/lib/tdl/examples/9_itegration/tb_test_tttop_sim.sv +2 -2
- data/lib/tdl/examples/9_itegration/test_tttop.sv +38 -7
- data/lib/tdl/examples/9_itegration/test_tttop_sim.sv +7 -38
- data/lib/tdl/examples/9_itegration/top.rb +1 -1
- data/lib/tdl/exlib/itegration_test_unit.rb +13 -0
- data/lib/tdl/exlib/itegration_verb.rb +22 -17
- data/lib/tdl/rebuild_ele/ele_base.rb +15 -3
- data/lib/tdl/sdlmodule/sdlmodule_arraychain.rb +1 -0
- data/lib/tdl/sdlmodule/sdlmodule_instance.rb +1 -1
- data/lib/tdl/sdlmodule/test_unit_module.rb +12 -16
- data/lib/tdl/tdl.rb +1 -0
- metadata +11 -2
checksums.yaml
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@@ -1,7 +1,7 @@
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---
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SHA256:
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metadata.gz:
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data.tar.gz:
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metadata.gz: 07d14bdc63e601755761b703ae0203852d824e1ffbb0cff1cd61e0c427325401
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data.tar.gz: 94c7af9a7d499b545956f3f4363eb622aba5d78c67be914958867381764e43d6
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metadata.gz: ceee62403d3d7c232713c554600bc774edea66c5aeb059471ea2a1f3ce6f8a5e96826b5204d8ec3e5e825b192648573ac2f4b1c8aee6358e104c714fa2f5a97e
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data.tar.gz: aa71d8cf174190ee50e8b2347509160b8890b963dbba84e25e2133dc90e7d25608b192dcb6d72ff22e799e714b672c665c24fdad6df7fb8bbc7c8f27e8aa70bf
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/**********************************************
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_______________________________________
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___________ Cook Darwin __________
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_______________________________________
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descript:
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author : Cook.Darwin
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Version: VERA.1.0
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just fot tdl
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Version: VERC.0.0
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just fot tdl, use class parameter
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creaded: 2017/4/5
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madified:
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***********************************************/
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`timescale 1ns/1ps
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`include "define_macro.sv"
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module axi4_direct_algin_addr_step #(
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// parameter ABANDON = "MASTER";
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parameter SLAVER_ADDR_STEP = 1024,
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// parameter MASTER_ADDR_STEP = 1024,
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parameter TERMENAL_ADDR_STEP = 1024,
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parameter TERMENAL_DSIZE = 128,
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`parameter_string MODE = "BOTH_to_BOTH", //ONLY_READ to BOTH,ONLY_WRITE to BOTH,BOTH to BOTH,BOTH to ONLY_READ,BOTH to ONLY_WRITE
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`parameter_string SLAVER_MODE = "BOTH", //
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`parameter_string MASTER_MODE = "BOTH", //
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//(* show = "false" *)
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`parameter_string IGNORE_IDSIZE = "FALSE", //(* show = "false" *)
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`parameter_string IGNORE_DSIZE = "FALSE", //(* show = "false" *)
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`parameter_string IGNORE_ASIZE = "FALSE", //(* show = "false" *)
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`parameter_string IGNORE_LSIZE = "FALSE" //(* show = "false" *)
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)(
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axi_inf.slaver slaver_inf,
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axi_inf.master master_inf
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);
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import SystemPkg::*;
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initial begin
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#(1us);
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if(IGNORE_IDSIZE == "FALSE")begin
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assert(slaver_inf.IDSIZE <= master_inf.IDSIZE) //idsize of slaver_inf can be smaller thane master_inf's
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else begin
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$error("SLAVER AXIS IDSIZE != MASTER AXIS IDSIZE");
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$finish;
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end
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end
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if(IGNORE_DSIZE == "FALSE")begin
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assert(slaver_inf.DSIZE == master_inf.DSIZE)
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else $error("SLAVER AXIS DSIZE != MASTER AXIS DSIZE");
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end
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// if(IGNORE_ASIZE == "FALSE")begin
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// assert(slaver_inf.ASIZE == master_inf.ASIZE)
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// else $error("SLAVER AXIS ASIZE != MASTER AXIS ASIZE");
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// end
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if(IGNORE_LSIZE == "FALSE")begin
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assert(slaver_inf.LSIZE == master_inf.LSIZE)
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else $error("SLAVER AXIS LSIZE != MASTER AXIS LSIZE");
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end
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case(MODE)
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"BOTH_to_BOTH","BOTH_to_ONLY_READ","BOTH_to_ONLY_WRITE":
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assert(slaver_inf.MODE =="BOTH" && SLAVER_MODE=="BOTH")
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else $error("SLAVER AXIS MODE<%s> != BOTH",slaver_inf.MODE);
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"ONLY_READ_to_BOTH":
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assert(slaver_inf.MODE == "ONLY_READ" && SLAVER_MODE=="ONLY_READ")
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else $error("SLAVER AXIS MODE != ONLY_READ");
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"ONLY_WRITE_to_BOTH","ONLY_WRITE_to_ONLY_WRITE":
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assert(slaver_inf.MODE == "ONLY_WRITE" && SLAVER_MODE=="ONLY_WRITE")
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else begin
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$error("SLAVER AXIS MODE != ONLY_WRITE");
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$finish;
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end
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"ONLY_READ_to_ONLY_READ","ONLY_READ_TO_ONLY_READ":
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assert(slaver_inf.MODE == "ONLY_READ" && SLAVER_MODE=="ONLY_READ")
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else $error("SLAVER AXIS MODE != ONLY_READ");
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"ONLY_WRITE_TO_ONLY_WRITE":
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assert(slaver_inf.MODE == "ONLY_WRITE" && SLAVER_MODE=="ONLY_WRITE")
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else $error("SLAVER AXIS MODE != ONLY_WRITE");
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default:
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assert(slaver_inf.MODE == "_____")
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else $error("SLAVER AXIS MODE ERROR") ;
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endcase
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case(MODE)
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"ONLY_WRITE_to_BOTH","ONLY_READ_to_BOTH","BOTH_to_BOTH":
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assert(master_inf.MODE == "BOTH" && MASTER_MODE=="BOTH")
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else $error("MASTER AXIS MODE != BOTH");
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"BOTH_to_ONLY_READ":
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assert(master_inf.MODE == "ONLY_READ" && MASTER_MODE=="ONLY_READY")
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else $error("MASTER AXIS MODE != ONLY_READ");
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"BOTH_to_ONLY_WRITE","ONLY_WRITE_to_ONLY_WRITE":
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assert(master_inf.MODE == "ONLY_WRITE" && MASTER_MODE=="ONLY_WRITE")
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else $error("MASTER AXIS MODE != ONLY_WRITE");
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"ONLY_READ_to_ONLY_READ","ONLY_READ_TO_ONLY_READ":
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assert(master_inf.MODE == "ONLY_READ" && MASTER_MODE=="ONLY_READ")
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else $error("MASTER AXIS MODE != ONLY_READ");
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"ONLY_WRITE_TO_ONLY_WRITE":
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assert(master_inf.MODE == "ONLY_WRITE" && MASTER_MODE=="ONLY_WRITE")
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else $error("MASTER AXIS MODE != ONLY_WRITE");
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default:
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assert(master_inf.MODE == "_____")
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else $error("MASTER AXIS MODE<%0s> ERROR",MODE);
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endcase
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end
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localparam RF = $clog2(TERMENAL_DSIZE) - $clog2(slaver_inf.DSIZE) + $clog2(SLAVER_ADDR_STEP) - $clog2(TERMENAL_ADDR_STEP);
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localparam FR = $clog2(TERMENAL_DSIZE) + $clog2(SLAVER_ADDR_STEP);
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localparam FL = $clog2(slaver_inf.DSIZE) + $clog2(TERMENAL_ADDR_STEP);
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generate
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if( (MASTER_MODE=="ONLY_WRITE") || (MASTER_MODE=="BOTH" && (SLAVER_MODE=="ONLY_WRITE" || SLAVER_MODE=="BOTH") ) )begin
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assign master_inf.axi_awid = slaver_inf.axi_awid ;
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if(FR == FL)
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assign master_inf.axi_awaddr = slaver_inf.axi_awaddr ;
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else if(FR < FL)
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assign master_inf.axi_awaddr = slaver_inf.axi_awaddr << (FL - FR) ;
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else if(FR > FL)
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assign master_inf.axi_awaddr = slaver_inf.axi_awaddr >> (FR - FL) ;
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assign master_inf.axi_awlen = slaver_inf.axi_awlen ;
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assign master_inf.axi_awsize = slaver_inf.axi_awsize ;
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assign master_inf.axi_awburst = slaver_inf.axi_awburst;
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assign master_inf.axi_awlock = slaver_inf.axi_awlock ;
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assign master_inf.axi_awcache = slaver_inf.axi_awcache;
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assign master_inf.axi_awprot = slaver_inf.axi_awprot ;
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assign master_inf.axi_awqos = slaver_inf.axi_awqos ;
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assign master_inf.axi_awvalid = slaver_inf.axi_awvalid;
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assign slaver_inf.axi_awready = master_inf.axi_awready;
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assign master_inf.axi_wdata = slaver_inf.axi_wdata ;
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assign master_inf.axi_wstrb = slaver_inf.axi_wstrb ;
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assign master_inf.axi_wlast = slaver_inf.axi_wlast ;
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assign master_inf.axi_wvalid = slaver_inf.axi_wvalid ;
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assign slaver_inf.axi_wready = master_inf.axi_wready ;
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assign master_inf.axi_bready = slaver_inf.axi_bready ;
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assign slaver_inf.axi_bid = master_inf.axi_bid ;
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assign slaver_inf.axi_bresp = master_inf.axi_bresp ;
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assign slaver_inf.axi_bvalid = master_inf.axi_bvalid ;
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end
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endgenerate
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generate
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if( (MASTER_MODE=="ONLY_READ") || (MASTER_MODE=="BOTH" && (SLAVER_MODE=="ONLY_READ" || SLAVER_MODE=="BOTH") ) )begin
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assign master_inf.axi_arid = slaver_inf.axi_arid ;
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// assign master_inf.axi_araddr = slaver_inf.axi_araddr ;
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if(FR == FL)
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assign master_inf.axi_araddr = slaver_inf.axi_araddr ;
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else if(FR < FL)
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assign master_inf.axi_araddr = slaver_inf.axi_araddr << (FL - FR) ;
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else if(FR > FL)
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assign master_inf.axi_araddr = slaver_inf.axi_araddr >> (FR - FL) ;
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assign master_inf.axi_arlen = slaver_inf.axi_arlen ;
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assign master_inf.axi_arsize = slaver_inf.axi_arsize ;
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assign master_inf.axi_arburst = slaver_inf.axi_arburst;
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assign master_inf.axi_arlock = slaver_inf.axi_arlock ;
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assign master_inf.axi_arcache = slaver_inf.axi_arcache;
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assign master_inf.axi_arprot = slaver_inf.axi_arprot ;
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assign master_inf.axi_arqos = slaver_inf.axi_arqos ;
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assign master_inf.axi_arvalid = slaver_inf.axi_arvalid;
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assign slaver_inf.axi_arready = master_inf.axi_arready;
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assign master_inf.axi_rready = slaver_inf.axi_rready ;
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assign slaver_inf.axi_rid = master_inf.axi_rid ;
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assign slaver_inf.axi_rdata = master_inf.axi_rdata ;
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assign slaver_inf.axi_rresp = master_inf.axi_rresp ;
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assign slaver_inf.axi_rlast = master_inf.axi_rlast ;
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assign slaver_inf.axi_rvalid = master_inf.axi_rvalid ;
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end
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endgenerate
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generate
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if(MASTER_MODE=="BOTH")begin
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if(SLAVER_MODE == "ONLY_READ")begin
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assign master_inf.axi_awid = '0;
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assign master_inf.axi_awaddr = '0;
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assign master_inf.axi_awlen = '0;
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assign master_inf.axi_awsize = '0;
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assign master_inf.axi_awburst = '0;
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assign master_inf.axi_awlock = '0;
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assign master_inf.axi_awcache = '0;
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assign master_inf.axi_awprot = '0;
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assign master_inf.axi_awqos = '0;
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assign master_inf.axi_awvalid = '0;
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assign master_inf.axi_wdata = '0;
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assign master_inf.axi_wstrb = '0;
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assign master_inf.axi_wlast = '0;
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assign master_inf.axi_wvalid = '0;
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assign master_inf.axi_bready = 1'b1;
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end if(SLAVER_MODE == "ONLY_WRITE")begin
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assign master_inf.axi_arid = '0;
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assign master_inf.axi_araddr = '0;
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assign master_inf.axi_arlen = '0;
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assign master_inf.axi_arsize = '0;
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assign master_inf.axi_arburst = '0;
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assign master_inf.axi_arlock = '0;
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assign master_inf.axi_arcache = '0;
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assign master_inf.axi_arprot = '0;
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assign master_inf.axi_arqos = '0;
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assign master_inf.axi_arvalid = '0;
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assign master_inf.axi_rready = 1'b1;
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end
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end else if(SLAVER_MODE == "BOTH")begin
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if(MASTER_MODE == "ONLY_READ")begin
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assign slaver_inf.axi_awready = 1'b1;
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assign slaver_inf.axi_wready = 1'b1;
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assign slaver_inf.axi_bid = '0;
|
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|
+
assign slaver_inf.axi_bresp = '0;
|
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211
|
+
assign slaver_inf.axi_bvalid = '0;
|
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|
+
end else if(SLAVER_MODE == "ONLY_WRITE")begin
|
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|
+
assign slaver_inf.axi_arready = 1'b1;
|
|
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|
+
assign slaver_inf.axi_rid = '0;
|
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215
|
+
assign slaver_inf.axi_rdata = '0;
|
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216
|
+
assign slaver_inf.axi_rresp = '0;
|
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217
|
+
assign slaver_inf.axi_rlast = '0;
|
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218
|
+
assign slaver_inf.axi_rvalid = '0;
|
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|
+
end
|
|
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|
+
end
|
|
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|
+
endgenerate
|
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|
+
|
|
223
|
+
endmodule
|
|
@@ -67,7 +67,7 @@ initial begin
|
|
|
67
67
|
$error("SLAVER AXIS MODE != ONLY_WRITE");
|
|
68
68
|
$finish;
|
|
69
69
|
end
|
|
70
|
-
"ONLY_READ_to_ONLY_READ":
|
|
70
|
+
"ONLY_READ_to_ONLY_READ","ONLY_READ_TO_ONLY_READ":
|
|
71
71
|
assert(slaver_inf.MODE == "ONLY_READ" && SLAVER_MODE=="ONLY_READ")
|
|
72
72
|
else $error("SLAVER AXIS MODE != ONLY_READ");
|
|
73
73
|
"ONLY_WRITE_TO_ONLY_WRITE":
|
|
@@ -88,7 +88,7 @@ initial begin
|
|
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88
88
|
"BOTH_to_ONLY_WRITE","ONLY_WRITE_to_ONLY_WRITE":
|
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89
89
|
assert(master_inf.MODE == "ONLY_WRITE" && MASTER_MODE=="ONLY_WRITE")
|
|
90
90
|
else $error("MASTER AXIS MODE != ONLY_WRITE");
|
|
91
|
-
"ONLY_READ_to_ONLY_READ":
|
|
91
|
+
"ONLY_READ_to_ONLY_READ","ONLY_READ_TO_ONLY_READ":
|
|
92
92
|
assert(master_inf.MODE == "ONLY_READ" && MASTER_MODE=="ONLY_READ")
|
|
93
93
|
else $error("MASTER AXIS MODE != ONLY_READ");
|
|
94
94
|
"ONLY_WRITE_TO_ONLY_WRITE":
|
|
@@ -96,13 +96,13 @@ initial begin
|
|
|
96
96
|
else $error("MASTER AXIS MODE != ONLY_WRITE");
|
|
97
97
|
default:
|
|
98
98
|
assert(master_inf.MODE == "_____")
|
|
99
|
-
else $error("MASTER AXIS MODE ERROR");
|
|
99
|
+
else $error("MASTER AXIS MODE<%0s> ERROR",MODE);
|
|
100
100
|
endcase
|
|
101
101
|
|
|
102
102
|
end
|
|
103
103
|
|
|
104
104
|
generate
|
|
105
|
-
if(MASTER_MODE
|
|
105
|
+
if( (MASTER_MODE=="ONLY_WRITE") || (MASTER_MODE=="BOTH" && (SLAVER_MODE=="ONLY_WRITE" || SLAVER_MODE=="BOTH") ) )begin
|
|
106
106
|
assign master_inf.axi_awid = slaver_inf.axi_awid ;
|
|
107
107
|
assign master_inf.axi_awaddr = slaver_inf.axi_awaddr ;
|
|
108
108
|
assign master_inf.axi_awlen = slaver_inf.axi_awlen ;
|
|
@@ -128,7 +128,7 @@ endgenerate
|
|
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128
128
|
|
|
129
129
|
|
|
130
130
|
generate
|
|
131
|
-
if(MASTER_MODE
|
|
131
|
+
if( (MASTER_MODE=="ONLY_READ") || (MASTER_MODE=="BOTH" && (SLAVER_MODE=="ONLY_READ" || SLAVER_MODE=="BOTH") ) )begin
|
|
132
132
|
assign master_inf.axi_arid = slaver_inf.axi_arid ;
|
|
133
133
|
assign master_inf.axi_araddr = slaver_inf.axi_araddr ;
|
|
134
134
|
assign master_inf.axi_arlen = slaver_inf.axi_arlen ;
|
|
@@ -149,4 +149,53 @@ generate
|
|
|
149
149
|
end
|
|
150
150
|
endgenerate
|
|
151
151
|
|
|
152
|
+
generate
|
|
153
|
+
if(MASTER_MODE=="BOTH")begin
|
|
154
|
+
if(SLAVER_MODE == "ONLY_READ")begin
|
|
155
|
+
assign master_inf.axi_awid = '0;
|
|
156
|
+
assign master_inf.axi_awaddr = '0;
|
|
157
|
+
assign master_inf.axi_awlen = '0;
|
|
158
|
+
assign master_inf.axi_awsize = '0;
|
|
159
|
+
assign master_inf.axi_awburst = '0;
|
|
160
|
+
assign master_inf.axi_awlock = '0;
|
|
161
|
+
assign master_inf.axi_awcache = '0;
|
|
162
|
+
assign master_inf.axi_awprot = '0;
|
|
163
|
+
assign master_inf.axi_awqos = '0;
|
|
164
|
+
assign master_inf.axi_awvalid = '0;
|
|
165
|
+
assign master_inf.axi_wdata = '0;
|
|
166
|
+
assign master_inf.axi_wstrb = '0;
|
|
167
|
+
assign master_inf.axi_wlast = '0;
|
|
168
|
+
assign master_inf.axi_wvalid = '0;
|
|
169
|
+
assign master_inf.axi_bready = 1'b1;
|
|
170
|
+
end if(SLAVER_MODE == "ONLY_WRITE")begin
|
|
171
|
+
assign master_inf.axi_arid = '0;
|
|
172
|
+
assign master_inf.axi_araddr = '0;
|
|
173
|
+
assign master_inf.axi_arlen = '0;
|
|
174
|
+
assign master_inf.axi_arsize = '0;
|
|
175
|
+
assign master_inf.axi_arburst = '0;
|
|
176
|
+
assign master_inf.axi_arlock = '0;
|
|
177
|
+
assign master_inf.axi_arcache = '0;
|
|
178
|
+
assign master_inf.axi_arprot = '0;
|
|
179
|
+
assign master_inf.axi_arqos = '0;
|
|
180
|
+
assign master_inf.axi_arvalid = '0;
|
|
181
|
+
assign master_inf.axi_rready = 1'b1;
|
|
182
|
+
end
|
|
183
|
+
end else if(SLAVER_MODE == "BOTH")begin
|
|
184
|
+
if(MASTER_MODE == "ONLY_READ")begin
|
|
185
|
+
assign slaver_inf.axi_awready = 1'b1;
|
|
186
|
+
assign slaver_inf.axi_wready = 1'b1;
|
|
187
|
+
assign slaver_inf.axi_bid = '0;
|
|
188
|
+
assign slaver_inf.axi_bresp = '0;
|
|
189
|
+
assign slaver_inf.axi_bvalid = '0;
|
|
190
|
+
end else if(SLAVER_MODE == "ONLY_WRITE")begin
|
|
191
|
+
assign slaver_inf.axi_arready = 1'b1;
|
|
192
|
+
assign slaver_inf.axi_rid = '0;
|
|
193
|
+
assign slaver_inf.axi_rdata = '0;
|
|
194
|
+
assign slaver_inf.axi_rresp = '0;
|
|
195
|
+
assign slaver_inf.axi_rlast = '0;
|
|
196
|
+
assign slaver_inf.axi_rvalid = '0;
|
|
197
|
+
end
|
|
198
|
+
end
|
|
199
|
+
endgenerate
|
|
200
|
+
|
|
152
201
|
endmodule
|
|
@@ -0,0 +1,146 @@
|
|
|
1
|
+
/**********************************************
|
|
2
|
+
_______________________________________
|
|
3
|
+
___________ Cook Darwin __________
|
|
4
|
+
_______________________________________
|
|
5
|
+
descript:
|
|
6
|
+
author : Cook.Darwin
|
|
7
|
+
Version: VERA.0.1 2017/5/24
|
|
8
|
+
use axi4_data_convert_A1
|
|
9
|
+
Version: VERA.1.0 2017/9/30
|
|
10
|
+
can discard partition
|
|
11
|
+
Version: VERB.0.0 2017/12/7
|
|
12
|
+
if slaver_inf.DSIZE is not 2**N,then 'width_convert' fisrt
|
|
13
|
+
Version: VERB.1.0 2021/10/03
|
|
14
|
+
axi4_direct_verc replace axi4_direct_verb
|
|
15
|
+
creaded: 2017/3/1
|
|
16
|
+
madified:
|
|
17
|
+
***********************************************/
|
|
18
|
+
`timescale 1ns/1ps
|
|
19
|
+
`include "define_macro.sv"
|
|
20
|
+
module axi4_long_to_axi4_wide_B1 #(
|
|
21
|
+
parameter PIPE = "OFF",
|
|
22
|
+
parameter PARTITION = "ON", //ON OFF
|
|
23
|
+
`parameter_string MODE = "BOTH_to_BOTH", //ONLY_READ to BOTH,ONLY_WRITE to BOTH,BOTH to BOTH,BOTH to ONLY_READ,BOTH to ONLY_WRITE
|
|
24
|
+
`parameter_string SLAVER_MODE = "BOTH", //
|
|
25
|
+
`parameter_string MASTER_MODE = "BOTH" //
|
|
26
|
+
)(
|
|
27
|
+
axi_inf.slaver slaver_inf,
|
|
28
|
+
axi_inf.master master_inf //wide ADDR_STEP == 1
|
|
29
|
+
);
|
|
30
|
+
|
|
31
|
+
// localparam real ADDR_STEP = slaver_inf.DSIZE/(master_inf.DSIZE/8.0); //addr burst == 8
|
|
32
|
+
|
|
33
|
+
import SystemPkg::*;
|
|
34
|
+
|
|
35
|
+
initial begin
|
|
36
|
+
assert(slaver_inf.MODE == master_inf.MODE)
|
|
37
|
+
else begin
|
|
38
|
+
$error("SLAVER AXIS MODE != MASTER AXIS MODE");
|
|
39
|
+
$stop;
|
|
40
|
+
end
|
|
41
|
+
end
|
|
42
|
+
|
|
43
|
+
|
|
44
|
+
//--->> width first <<------------------------------
|
|
45
|
+
|
|
46
|
+
localparam WCSIZE = 2**($clog2(slaver_inf.DSIZE));
|
|
47
|
+
|
|
48
|
+
axi_inf #(
|
|
49
|
+
.IDSIZE (slaver_inf.IDSIZE ),
|
|
50
|
+
.ASIZE (slaver_inf.ASIZE ),
|
|
51
|
+
.LSIZE (slaver_inf.LSIZE ),
|
|
52
|
+
.DSIZE (WCSIZE ),
|
|
53
|
+
.MODE (slaver_inf.MODE ),
|
|
54
|
+
.ADDR_STEP (slaver_inf.ADDR_STEP*WCSIZE/slaver_inf.DSIZE )
|
|
55
|
+
)axi_inf_first_wc(
|
|
56
|
+
.axi_aclk (slaver_inf.axi_aclk ),
|
|
57
|
+
.axi_aresetn (slaver_inf.axi_aresetn )
|
|
58
|
+
);
|
|
59
|
+
|
|
60
|
+
generate
|
|
61
|
+
if(WCSIZE != slaver_inf.DSIZE)
|
|
62
|
+
axi4_data_convert_A1 axi4_data_convert_inst(
|
|
63
|
+
/* axi_inf.slaver_inf */ .axi_in (slaver_inf ),
|
|
64
|
+
/* axi_inf.master_inf */ .axi_out (axi_inf_first_wc )
|
|
65
|
+
);
|
|
66
|
+
else
|
|
67
|
+
axi4_direct_verc #(
|
|
68
|
+
.MODE (MODE), //ONLY_READ to BOTH,ONLY_WRITE to BOTH,BOTH to BOTH,BOTH to ONLY_READ,BOTH to ONLY_WRITE
|
|
69
|
+
.SLAVER_MODE (SLAVER_MODE), //
|
|
70
|
+
.MASTER_MODE (MASTER_MODE) //
|
|
71
|
+
)axi4_direct_verc_inst(
|
|
72
|
+
/* axi_inf.slaver_inf */ .slaver_inf (slaver_inf ),
|
|
73
|
+
/* axi_inf.master_inf */ .master_inf (axi_inf_first_wc )
|
|
74
|
+
);
|
|
75
|
+
endgenerate
|
|
76
|
+
//---<< width first >>------------------------------
|
|
77
|
+
|
|
78
|
+
axi_inf #(
|
|
79
|
+
.IDSIZE (master_inf.IDSIZE ),
|
|
80
|
+
.ASIZE (axi_inf_first_wc.ASIZE ),
|
|
81
|
+
.LSIZE (axi_inf_first_wc.LSIZE ),
|
|
82
|
+
.DSIZE (axi_inf_first_wc.DSIZE ),
|
|
83
|
+
.MODE (axi_inf_first_wc.MODE ),
|
|
84
|
+
.ADDR_STEP (axi_inf_first_wc.ADDR_STEP )
|
|
85
|
+
)axi_inf_pout(
|
|
86
|
+
.axi_aclk (slaver_inf.axi_aclk ),
|
|
87
|
+
.axi_aresetn (slaver_inf.axi_aresetn )
|
|
88
|
+
);
|
|
89
|
+
|
|
90
|
+
axi_inf #(
|
|
91
|
+
.IDSIZE (master_inf.IDSIZE ),
|
|
92
|
+
.ASIZE (master_inf.ASIZE ),
|
|
93
|
+
.LSIZE (master_inf.LSIZE ),
|
|
94
|
+
.DSIZE (master_inf.DSIZE ),
|
|
95
|
+
.MODE (axi_inf_first_wc.MODE ),
|
|
96
|
+
.ADDR_STEP (master_inf.ADDR_STEP )
|
|
97
|
+
)axi_inf_cdout(
|
|
98
|
+
.axi_aclk (slaver_inf.axi_aclk ),
|
|
99
|
+
.axi_aresetn (slaver_inf.axi_aresetn )
|
|
100
|
+
);
|
|
101
|
+
|
|
102
|
+
|
|
103
|
+
// localparam PSIZE = (((128/slaver_inf.DSIZE) * (slaver_inf.DSIZE+0.0)) * master_inf.DSIZE) / slaver_inf.DSIZE;
|
|
104
|
+
generate
|
|
105
|
+
if(PARTITION == "ON" || PARTITION == "TRUE")begin
|
|
106
|
+
axi4_partition_OD #(
|
|
107
|
+
// .PSIZE (master_inf.DSIZE*128/slaver_inf.DSIZE ),
|
|
108
|
+
.PSIZE (int'((((128/axi_inf_first_wc.DSIZE) * (axi_inf_first_wc.DSIZE+0.0)) * master_inf.DSIZE) / axi_inf_first_wc.DSIZE ))
|
|
109
|
+
// .ADDR_STEP (slaver_inf.DSIZE/(master_inf.DSIZE/8.0) )
|
|
110
|
+
// .ADDR_STEP (4*slaver_inf.DSIZE/16.0 )
|
|
111
|
+
)axi4_partition_inst(
|
|
112
|
+
/* axi_inf.slaver_inf */ .slaver_inf (axi_inf_first_wc ),
|
|
113
|
+
/* axi_inf.master_inf */ .master_inf (axi_inf_pout )
|
|
114
|
+
);
|
|
115
|
+
|
|
116
|
+
axi4_data_convert_verb #(
|
|
117
|
+
.SLAVER_MODE (SLAVER_MODE), //
|
|
118
|
+
.MASTER_MODE (MASTER_MODE) //
|
|
119
|
+
)axi4_data_convert_inst(
|
|
120
|
+
/* axi_inf.slaver_inf */ .axi_in (axi_inf_pout ),
|
|
121
|
+
/* axi_inf.master_inf */ .axi_out (axi_inf_cdout )
|
|
122
|
+
);
|
|
123
|
+
end else begin
|
|
124
|
+
axi4_data_convert_verb #(
|
|
125
|
+
.SLAVER_MODE (SLAVER_MODE), //
|
|
126
|
+
.MASTER_MODE (MASTER_MODE) //
|
|
127
|
+
)axi4_data_convert_inst(
|
|
128
|
+
/* axi_inf.slaver_inf */ .axi_in (axi_inf_first_wc ),
|
|
129
|
+
/* axi_inf.master_inf */ .axi_out (axi_inf_cdout )
|
|
130
|
+
);
|
|
131
|
+
|
|
132
|
+
end
|
|
133
|
+
endgenerate
|
|
134
|
+
|
|
135
|
+
|
|
136
|
+
axi4_packet_fifo_verb #( //512
|
|
137
|
+
.PIPE (PIPE ),
|
|
138
|
+
.DEPTH (4 ),
|
|
139
|
+
.SLAVER_MODE (SLAVER_MODE ), //
|
|
140
|
+
.MASTER_MODE (MASTER_MODE ) //
|
|
141
|
+
)axi4_packet_fifo_inst(
|
|
142
|
+
/* axi_inf.slaver_inf */ .axi_in (axi_inf_cdout ),
|
|
143
|
+
/* axi_inf.master_inf */ .axi_out (master_inf )
|
|
144
|
+
);
|
|
145
|
+
|
|
146
|
+
endmodule
|
|
@@ -0,0 +1,62 @@
|
|
|
1
|
+
/**********************************************
|
|
2
|
+
_______________________________________
|
|
3
|
+
___________ Cook Darwin __________
|
|
4
|
+
_______________________________________
|
|
5
|
+
descript:
|
|
6
|
+
author : Cook.Darwin
|
|
7
|
+
Version: VERA.0.0
|
|
8
|
+
creaded: 2017/2/28
|
|
9
|
+
madified:
|
|
10
|
+
***********************************************/
|
|
11
|
+
`timescale 1ns/1ps
|
|
12
|
+
`include "define_macro.sv"
|
|
13
|
+
module axi4_packet_fifo_verb #(
|
|
14
|
+
parameter PIPE = "OFF",
|
|
15
|
+
parameter DEPTH = 4,
|
|
16
|
+
`parameter_string MODE = "BOTH", //ONLY_WRITE ONLY_READ BOTH
|
|
17
|
+
`parameter_string SLAVER_MODE = "BOTH", //
|
|
18
|
+
`parameter_string MASTER_MODE = "BOTH" //
|
|
19
|
+
)(
|
|
20
|
+
axi_inf.slaver axi_in,
|
|
21
|
+
axi_inf.master axi_out
|
|
22
|
+
);
|
|
23
|
+
|
|
24
|
+
import SystemPkg::*;
|
|
25
|
+
|
|
26
|
+
initial begin
|
|
27
|
+
assert(SLAVER_MODE == MASTER_MODE)
|
|
28
|
+
else begin
|
|
29
|
+
$error("SLAVER AXIS MODE != MASTER AXIS MODE");
|
|
30
|
+
$stop;
|
|
31
|
+
end
|
|
32
|
+
end
|
|
33
|
+
|
|
34
|
+
|
|
35
|
+
`VCS_AXI4_CPT(axi_in,slaver,slaver_rd,Read)
|
|
36
|
+
`VCS_AXI4_CPT(axi_in,slaver,slaver_wr,Write)
|
|
37
|
+
`VCS_AXI4_CPT_LT(axi_out,master_rd,master,Read)
|
|
38
|
+
`VCS_AXI4_CPT_LT(axi_out,master_wr,master,Write)
|
|
39
|
+
|
|
40
|
+
|
|
41
|
+
generate
|
|
42
|
+
if(SLAVER_MODE=="BOTH" || SLAVER_MODE=="ONLY_WRITE")
|
|
43
|
+
axi4_wr_packet_fifo #(
|
|
44
|
+
.PIPE (PIPE ),
|
|
45
|
+
.DEPTH (DEPTH )
|
|
46
|
+
)axi4_wr_packet_fifo_inst(
|
|
47
|
+
/* axi_inf.slaver_wr */ .axi_in (`axi_in_vcs_cptWrite ),
|
|
48
|
+
/* axi_inf.master_wr */ .axi_out (`axi_out_vcs_cptWrite )
|
|
49
|
+
);
|
|
50
|
+
endgenerate
|
|
51
|
+
|
|
52
|
+
generate
|
|
53
|
+
if(SLAVER_MODE=="BOTH" || SLAVER_MODE=="ONLY_READ")
|
|
54
|
+
axi4_rd_packet_fifo #(
|
|
55
|
+
.DEPTH (DEPTH )
|
|
56
|
+
)axi4_rd_packet_fifo_inst(
|
|
57
|
+
/* axi_inf.slaver_rd */ .slaver (`axi_in_vcs_cptRead ),
|
|
58
|
+
/* axi_inf.master_rd */ .master (`axi_out_vcs_cptRead )
|
|
59
|
+
);
|
|
60
|
+
endgenerate
|
|
61
|
+
|
|
62
|
+
endmodule
|
|
@@ -46,7 +46,7 @@ assign axi_in.axi_awready = !auxiliary_fifo_full;
|
|
|
46
46
|
|
|
47
47
|
logic stream_fifo_empty;
|
|
48
48
|
|
|
49
|
-
axi_stream_inf #(.DSIZE(axi_in.ASIZE+axi_in.LSIZE+axi_in.IDSIZE)) id_add_len_in(.aclk(
|
|
49
|
+
axi_stream_inf #(.DSIZE(axi_in.ASIZE+axi_in.LSIZE+axi_in.IDSIZE)) id_add_len_in(.aclk(axi_out.axi_aclk),.aresetn(axi_out.axi_aresetn),.aclken(1'b1));
|
|
50
50
|
|
|
51
51
|
assign id_add_len_in.axis_tdata = auxiliary_fifo_rd_data;
|
|
52
52
|
assign id_add_len_in.axis_tvalid = !auxiliary_fifo_empty && !stream_fifo_empty;
|
|
@@ -54,10 +54,11 @@ assign id_add_len_in.axis_tlast = 1'b1;
|
|
|
54
54
|
assign auxiliary_fifo_rd_en = id_add_len_in.axis_tready && !stream_fifo_empty;
|
|
55
55
|
|
|
56
56
|
logic axi_stream_en;
|
|
57
|
-
|
|
57
|
+
`VCS_AXI4_CPT_LT(axi_out,master_wr_aux_no_resp,master_wr,Aux_Write)
|
|
58
58
|
axi4_wr_auxiliary_gen_without_resp axi4_wr_auxiliary_gen_without_resp_inst(
|
|
59
59
|
/* axi_stream_inf.slaver */ .id_add_len_in (id_add_len_in ), //tlast is not necessary
|
|
60
|
-
/* axi_inf.master_wr_aux_no_resp */ .axi_wr_aux (axi_out ),
|
|
60
|
+
// /* axi_inf.master_wr_aux_no_resp */ .axi_wr_aux (axi_out ),
|
|
61
|
+
/* axi_inf.master_wr_aux_no_resp */ .axi_wr_aux (`axi_out_vcs_cptAux_Write ),
|
|
61
62
|
/* output logic */ .stream_en (axi_stream_en )
|
|
62
63
|
);
|
|
63
64
|
//---<< AUXILIARY >>------------------
|
|
@@ -127,7 +127,7 @@ assign addr_s = addr_cur;
|
|
|
127
127
|
assign len_s = split_out.axis_tcnt;
|
|
128
128
|
assign id_add_len_in.axis_tvalid = ~fifo_empty;
|
|
129
129
|
assign id_add_len_in.axis_tdata = fifo_rdata;
|
|
130
|
-
assign id_add_len_in.axis_tlast =
|
|
130
|
+
assign id_add_len_in.axis_tlast = 1'b1;
|
|
131
131
|
assign fifo_rd_en = id_add_len_in.axis_tready;
|
|
132
132
|
|
|
133
133
|
assign axi_wr.axi_wdata = pipe_axis.axis_tdata;
|