HDLRuby 2.11.11 → 2.11.12

data/lib/HDLRuby/hruby_rsim.rb

@@ -66,7 +66,6 @@ module HDLRuby::High
                 @sig_active.each do |sig|
                     next if (sig.c_value.eql?(sig.f_value))
                     # next if (sig.c_value.to_vstr == sig.f_value.to_vstr)
-                    # puts "sig.c_value: #{sig.c_value.to_vstr}, sig.f_value=#{sig.f_value.to_vstr}"
                     sig.each_anyedge { |beh| @sig_exec << beh }
                     if (sig.c_value.zero?) then
                         # puts "sig.c_value=#{sig.c_value.content}"
@@ -108,6 +107,8 @@ module HDLRuby::High
             HDLRuby.show "#{Time.now}#{show_mem}"
             # Merge the included.
             self.merge_included!
+            # Process par in seq.
+            self.par_in_seq2seq!
             # Initializes the time.
             @time = 0
             # Initializes the time and signals execution buffers.
@@ -131,6 +132,9 @@ module HDLRuby::High
             self.init_untimeds
             # puts "End of init_untimed."
 
+            # Maybe there is nothing to execute.
+            return if @total_timed_behaviors == 0
+
             # Is there more than one timed behavior.
             if @total_timed_behaviors <= 1 then
                 # No, no need of multithreading.
@@ -490,6 +494,12 @@ module HDLRuby::High
 
         ## Initialize the simulation for +systemT+
         def init_sim(systemT)
+            # Recurse on the sub signals if any.
+            if self.each_signal.any? then
+                self.each_signal {|sig| sig.init_sim(systemT) }
+                return
+            end
+            # No sub signal, really initialize the current signal.
             if self.value then
                 @c_value = self.value.execute(:par).to_value
                 @f_value = @c_value.to_value
@@ -506,18 +516,27 @@ module HDLRuby::High
 
         ## Adds behavior +beh+ activated on a positive edge of the signal.
         def add_posedge(beh)
+            # Recurse on the sub signals.
+            self.each_signal {|sig| sig.add_posedge(beh) }
+            # Apply on current signal.
             @posedge_behaviors ||= []
             @posedge_behaviors << beh
         end
 
         ## Adds behavior +beh+ activated on a negative edge of the signal.
         def add_negedge(beh)
+            # Recurse on the sub signals.
+            self.each_signal {|sig| sig.add_negedge(beh) }
+            # Apply on current signal.
             @negedge_behaviors ||= []
             @negedge_behaviors << beh
         end
 
         ## Adds behavior +beh+ activated on a any edge of the signal.
         def add_anyedge(beh)
+            # Recurse on the sub signals.
+            self.each_signal {|sig| sig.add_anyedge(beh) }
+            # Apply on current signal.
             @anyedge_behaviors ||= []
             @anyedge_behaviors << beh
         end
@@ -543,9 +562,9 @@ module HDLRuby::High
 
         ## Execute the expression.
         def execute(mode)
-            # puts "Executing signal=#{self.fullname}"
-            # return mode == :par ? self.c_value : self.f_value
+            # puts "Executing signal=#{self.fullname} in mode=#{mode}  with c_value=#{self.c_value} and f_value=#{self.f_value}"
             return @mode == :seq ? self.f_value : self.c_value
+            # return @mode == :seq || mode == :seq ? self.f_value : self.c_value
         end
 
         ## Assigns +value+ the the reference.
@@ -649,10 +668,12 @@ module HDLRuby::High
         ## Initialize the simulation for system +systemT+.
         def init_sim(systemT)
             self.left.init_sim(systemT)
+            self.right.init_sim(systemT)
         end
 
         ## Executes the statement.
         def execute(mode)
+            # puts "execute Transmit in mode=#{mode} for left=#{self.left.object.name}"
             self.left.assign(mode,self.right.execute(mode))
         end
     end
@@ -670,6 +691,7 @@ module HDLRuby::High
 
         ## Executes the statement.
         def execute(mode)
+            # puts "execute hif with mode=#{mode}"
             # Check the main condition.
             if !(self.condition.execute(mode).zero?) then
                 self.yes.execute(mode)
@@ -848,6 +870,7 @@ module HDLRuby::High
 
         ## Executes the statement.
         def execute(mode)
+            # puts "execute block of mode=#{self.mode}"
             self.each_statement { |stmnt| stmnt.execute(self.mode) }
         end
 
@@ -858,6 +881,27 @@ module HDLRuby::High
         end
     end
 
+    class If
+        ## Returns the name of the signal with its hierarchy.
+        def fullname
+            return self.parent.fullname
+        end
+    end
+
+    class When
+        ## Returns the name of the signal with its hierarchy.
+        def fullname
+            return self.parent.fullname
+        end
+    end
+
+    class Case
+        ## Returns the name of the signal with its hierarchy.
+        def fullname
+            return self.parent.fullname
+        end
+    end
+
     # Describes a timed block.
     #
     # NOTE: 
@@ -889,8 +933,9 @@ module HDLRuby::High
         def init_sim(systemT)
             # Add the connection to the list of untimed objets.
             systemT.add_untimed(self)
-            # Recurse on the left.
+            # Recurse on the left and right.
             self.left.init_sim(systemT)
+            self.right.init_sim(systemT)
             # Process the sensitivity list.
             # Is it a clocked behavior?
             events = []
@@ -914,7 +959,7 @@ module HDLRuby::High
 
         ## Executes the statement.
         def execute(mode)
-            # puts "connection = #{self}" if self.left.is_a?(RefObject) && self.left.object.name.to_s.include?("xnor")
+            # puts "connection left=#{left} right=#{right}"
             self.left.assign(mode,self.right.execute(mode))
         end
     end
@@ -926,6 +971,11 @@ module HDLRuby::High
     #
     # NOTE: this is an abstract class which is not to be used directly.
     class Expression
+        ## Initialize the simulation for system +systemT+.
+        def init_sim(systemT)
+            # By default: do nothing.
+        end
+
         ## Executes the expression in +mode+ (:blocking or :nonblocking)
         #  NOTE: to be overrided.
         def execute(mode)
@@ -937,6 +987,11 @@ module HDLRuby::High
     ##
     # Describes a value.
     class Value
+        ## Initialize the simulation for system +systemT+.
+        def init_sim(systemT)
+            # Nothing to do.
+        end
+
         # include Vprocess
 
         ## Executes the expression.
@@ -949,10 +1004,16 @@ module HDLRuby::High
     ##
     # Describes a cast.
     class Cast
+        ## Initialize the simulation for system +systemT+.
+        def init_sim(systemT)
+            # Recurse on the child.
+            self.child.init_sim(systemT)
+        end
+
         ## Executes the expression.
         def execute(mode)
-            # Recurse on the child.
-            # res = tocast.execute(mode)
+            # puts "child=#{self.child}"
+            # puts "child object=#{self.child.object}(#{self.child.object.name})" if self.child.is_a?(RefObject)
             # Shall we reverse the content of a concat.
             if self.child.is_a?(Concat) && 
                     self.type.direction != self.child.type.direction then
@@ -961,6 +1022,7 @@ module HDLRuby::High
             else
                 res = self.child.execute(mode)
             end
+            # puts "res=#{res}"
             # Cast it.
             res = res.cast(self.type,true)
             # Returns the result.
@@ -981,6 +1043,12 @@ module HDLRuby::High
     ## 
     # Describes an unary operation.
     class Unary
+        ## Initialize the simulation for system +systemT+.
+        def init_sim(systemT)
+            # Recurse on the child.
+            self.child.init_sim(systemT)
+        end
+
         ## Execute the expression.
         def execute(mode)
             # puts "Unary with operator=#{self.operator}"
@@ -996,6 +1064,13 @@ module HDLRuby::High
     ##
     # Describes an binary operation.
     class Binary
+        ## Initialize the simulation for system +systemT+.
+        def init_sim(systemT)
+            # Recurse on the children.
+            self.left.init_sim(systemT)
+            self.right.init_sim(systemT)
+        end
+
         ## Execute the expression.
         def execute(mode)
             # Recurse on the children.
@@ -1012,6 +1087,13 @@ module HDLRuby::High
     #
     # NOTE: choice is using the value of +select+ as an index.
     class Select
+        ## Initialize the simulation for system +systemT+.
+        def init_sim(systemT)
+            # Recurse on the children.
+            self.select.init_sim(systemT)
+            self.each_choice { |choice| choice.init_sim(systemT) }
+        end
+
         ## Execute the expression.
         def execute(mode)
             unless @mask then
@@ -1033,6 +1115,12 @@ module HDLRuby::High
     ## 
     # Describes a concatenation expression.
     class Concat
+        ## Initialize the simulation for system +systemT+.
+        def init_sim(systemT)
+            # Recurse on the children.
+            self.each_expression { |expr| expr.init_sim(systemT) }
+        end
+
         ## Execute the expression.
         def execute(mode, reverse=false)
             # Recurse on the children.
@@ -1218,7 +1306,44 @@ module HDLRuby::High
     class RefObject
         ## Initialize the simulation for system +systemT+.
         def init_sim(systemT)
+            # puts "init_sim for RefObject=#{self}"
             @sim = systemT
+
+            # Modify the exectute and assign methods if the object has
+            # sub signals (for faster execution).
+            if self.object.each_signal.any? then
+                ## Execute the expression.
+                self.define_singleton_method(:execute) do |mode|
+                    # Recurse on the children.
+                    iter = self.object.each_signal
+                    iter = iter.reverse_each unless self.object.type.direction == :big
+                    tmpe = iter.map {|sig| sig.execute(mode) }
+                    # Concatenate the result.
+                    # return tmpe.reduce(:concat)
+                    return Vprocess.concat(*tmpe)
+                end
+                ## Assigns +value+ the the reference.
+                self.define_singleton_method(:assign) do |mode,value|
+                    # puts "RefObject #{self} assign with object=#{self.object}"
+                    # Flatten the value type.
+                    value.type = [value.type.width].to_type
+                    pos = 0
+                    width = 0
+                    # Recurse on the children.
+                    iter = self.object.each_signal
+                    iter = iter.reverse_each unless self.object.type.direction == :big
+                    iter.each do |sig|
+                        width = sig.type.width
+                        sig.assign(mode,value[(pos+width-1).to_expr..pos.to_expr])
+                        # Tell the signal changed.
+                        if !(sig.c_value.eql?(sig.f_value)) then
+                            @sim.add_sig_active(sig)
+                        end
+                        # Prepare for the next reference.
+                        pos += width
+                    end
+                end
+            end
         end
 
         ## Execute the expression.

data/lib/HDLRuby/hruby_rsim_vcd.rb

@@ -94,9 +94,10 @@ module HDLRuby::High
 
         ## Gets the VCD variables with their long name.
         def get_vars_with_fullname(vars_with_fullname = {})
-            # Adds the signals of the interface of the system.
+            # Recurse on the signals.
             self.each_signal do |sig|
-                vars_with_fullname[sig] = HDLRuby::High.vcd_name(sig.fullname)
+                sig.get_vars_with_fullname(vars_with_fullname)
+                # vars_with_fullname[sig] = HDLRuby::High.vcd_name(sig.fullname)
             end
             # Recurse on the scope.
             return self.scope.get_vars_with_fullname(vars_with_fullname)
@@ -104,9 +105,13 @@ module HDLRuby::High
 
         ## Gets the VCD variables with their id string.
         def get_vars_with_idstr(vars_with_idstr = {})
-            # Adds the signals of the interface of the system.
+            # # Adds the signals of the interface of the system.
+            # self.each_signal do |sig|
+            #     vars_with_idstr[sig] = HDLRuby::High.vcd_idstr(sig)
+            # end
+            # Recurse on the signals.
             self.each_signal do |sig|
-                vars_with_idstr[sig] = HDLRuby::High.vcd_idstr(sig)
+                sig.get_vars_with_idstr(vars_with_idstr)
             end
             # Recurse on the scope.
             return self.scope.get_vars_with_idstr(vars_with_idstr)
@@ -119,11 +124,11 @@ module HDLRuby::High
             vcdout << "$scope module #{HDLRuby::High.vcd_name(self.name)} $end\n"
             # Shows the interface signals.
             self.each_signal do |sig|
-                # puts "showing signal #{HDLRuby::High.vcd_name(sig.fullname)}"
-                vcdout << "$var wire #{sig.type.width} "
-                # vcdout << "#{HDLRuby::High.vcd_name(sig.fullname)} "
-                vcdout << "#{HDLRuby::High.vcd_idstr(sig)} "
-                vcdout << "#{HDLRuby::High.vcd_name(sig.name)} $end\n"
+                sig.show_hierarchy(vcdout)
+                # # puts "showing signal #{HDLRuby::High.vcd_name(sig.fullname)}"
+                # vcdout << "$var wire #{sig.type.width} "
+                # vcdout << "#{HDLRuby::High.vcd_idstr(sig)} "
+                # vcdout << "#{HDLRuby::High.vcd_name(sig.name)} $end\n"
             end
             # Recurse on the scope.
             self.scope.show_hierarchy(vcdout)
@@ -170,11 +175,12 @@ module HDLRuby::High
             end
             # Shows the inner signals.
             self.each_inner do |sig|
-                # puts "showing inner signal #{HDLRuby::High.vcd_name(sig.fullname)}"
-                vcdout << "$var wire #{sig.type.width} "
-                # vcdout << "#{HDLRuby::High.vcd_name(sig.fullname)} "
-                vcdout << "#{HDLRuby::High.vcd_idstr(sig)} "
-                vcdout << "#{HDLRuby::High.vcd_name(sig.name)} $end\n"
+                sig.show_hierarchy(vcdout)
+                # # puts "showing inner signal #{HDLRuby::High.vcd_name(sig.fullname)}"
+                # vcdout << "$var wire #{sig.type.width} "
+                # # vcdout << "#{HDLRuby::High.vcd_name(sig.fullname)} "
+                # vcdout << "#{HDLRuby::High.vcd_idstr(sig)} "
+                # vcdout << "#{HDLRuby::High.vcd_name(sig.name)} $end\n"
             end
             # Recurse on the behaviors' blocks
             self.each_behavior do |beh|
@@ -196,9 +202,14 @@ module HDLRuby::High
 
         ## Gets the VCD variables with their long name.
         def get_vars_with_fullname(vars_with_fullname = {})
-            # Adds the inner signals.
+            # # Adds the inner signals.
+            # self.each_inner do |sig|
+            #     vars_with_fullname[sig] = HDLRuby::High.vcd_name(sig.fullname)
+            # end
+            # Recurse on the inner signals.
             self.each_inner do |sig|
-                vars_with_fullname[sig] = HDLRuby::High.vcd_name(sig.fullname)
+                sig.get_vars_with_fullname(vars_with_fullname)
+                # vars_with_fullname[sig] = HDLRuby::High.vcd_name(sig.fullname)
             end
             # Recurse on the behaviors' blocks
             self.each_behavior do |beh|
@@ -217,9 +228,13 @@ module HDLRuby::High
 
         ## Gets the VCD variables with their id string.
         def get_vars_with_idstr(vars_with_idstr = {})
-            # Adds the inner signals.
+            # # Adds the inner signals.
+            # self.each_inner do |sig|
+            #     vars_with_idstr[sig] = HDLRuby::High.vcd_idstr(sig)
+            # end
+            # Recurse on the inner signals.
             self.each_inner do |sig|
-                vars_with_idstr[sig] = HDLRuby::High.vcd_idstr(sig)
+                sig.get_vars_with_idstr(vars_with_idstr)
             end
             # Recurse on the behaviors' blocks
             self.each_behavior do |beh|
@@ -237,6 +252,53 @@ module HDLRuby::High
         end
     end
 
+    ##
+    # Enhance the signals class with VCD support.
+    module SimSignal
+        ## Shows the hierarchy of the variables.
+        def show_hierarchy(vcdout)
+            # puts "show_hierarcy for signal=#{self.name}"
+            if self.each_signal.any? then
+                # The signal is hierarchical, recurse on the sub signals.
+                vcdout << "$scope module #{HDLRuby::High.vcd_name(self.name)} $end\n"
+                self.each_signal { |sig| sig.show_hierarchy(vcdout) }
+                vcdout << "$upscope $end\n"
+            else
+                # This is a signal to show.
+                vcdout << "$var wire #{self.type.width} "
+                vcdout << "#{HDLRuby::High.vcd_idstr(self)} "
+                vcdout << "#{HDLRuby::High.vcd_name(self.name)} $end\n"
+            end
+        end
+
+        ## Gets the VCD variables with their long name.
+        def get_vars_with_fullname(vars_with_fullname = {})
+            if self.each_signal.any? then
+                # There are sub signals, recurse on them.
+                self.each_signal do |sig|
+                    sig.get_vars_with_fullname(vars_with_fullname)
+                end
+            else
+                # No add the current signal.
+                vars_with_fullname[self] = HDLRuby::High.vcd_name(self.fullname)
+            end
+            return vars_with_full_name
+        end
+
+        ## Gets the VCD variables with their id string.
+        def get_vars_with_idstr(vars_with_idstr = {})
+            if self.each_signal.any? then
+                # There are sub signals, recurse on them.
+                self.each_signal do |sig|
+                    sig.get_vars_with_idstr(vars_with_idstr)
+                end
+            else
+                # No add the current signal.
+                vars_with_idstr[self] = HDLRuby::High.vcd_idstr(self)
+            end
+            return vars_with_idstr
+        end
+    end
 
     ##
     # Enhance the Transmit class with VCD support.
@@ -329,11 +391,12 @@ module HDLRuby::High
             end
             # Shows the inner signals.
             self.each_inner do |sig|
-                # puts "showing inner signal #{HDLRuby::High.vcd_name(sig.fullname)}"
-                vcdout << "$var wire #{sig.type.width} "
-                # vcdout << "#{HDLRuby::High.vcd_name(sig.fullname)} "
-                vcdout << "#{HDLRuby::High.vcd_idstr(sig)} "
-                vcdout << "#{HDLRuby::High.vcd_name(sig.name)} $end\n"
+                sig.show_hierarchy(vcdout)
+                # # puts "showing inner signal #{HDLRuby::High.vcd_name(sig.fullname)}"
+                # vcdout << "$var wire #{sig.type.width} "
+                # # vcdout << "#{HDLRuby::High.vcd_name(sig.fullname)} "
+                # vcdout << "#{HDLRuby::High.vcd_idstr(sig)} "
+                # vcdout << "#{HDLRuby::High.vcd_name(sig.name)} $end\n"
             end
             # Recurse on the statements
             self.each_statement do |stmnt|
@@ -347,9 +410,14 @@ module HDLRuby::High
 
         ## Gets the VCD variables with their long name.
         def get_vars_with_fullname(vars_with_fullname = {})
-            # Adds the inner signals.
+            # # Adds the inner signals.
+            # self.each_inner do |sig|
+            #     vars_with_fullname[sig] = HDLRuby::High.vcd_name(sig.fullname)
+            # end
+            # Recurse on the inner signals.
             self.each_inner do |sig|
-                vars_with_fullname[sig] = HDLRuby::High.vcd_name(sig.fullname)
+                sig.get_vars_with_fullname(vars_with_fullname)
+                # vars_with_fullname[sig] = HDLRuby::High.vcd_name(sig.fullname)
             end
             # Recurse on the statements.
             self.each_statement do |stmnt|
@@ -360,9 +428,13 @@ module HDLRuby::High
 
         ## Gets the VCD variables with their id string.
         def get_vars_with_idstr(vars_with_idstr = {})
-            # Adds the inner signals.
+            # # Adds the inner signals.
+            # self.each_inner do |sig|
+            #     vars_with_idstr[sig] = HDLRuby::High.vcd_idstr(sig)
+            # end
+            # Recurse on the inner signals.
             self.each_inner do |sig|
-                vars_with_idstr[sig] = HDLRuby::High.vcd_idstr(sig)
+                sif.get_vars_with_idstr(vars_with_idstr)
             end
             # Recurse on the statements.
             self.each_statement do |stmnt|

data/lib/HDLRuby/hruby_values.rb

@@ -13,6 +13,9 @@ module HDLRuby
 
         # Truncs integer +val+ to +width+
         def trunc(val,width)
+            if val.is_a?(BitString) then
+                return val[(width-1)..0]
+            end
             if val.bit_length > width then
                 if val >= 0 then
                     # return val & (2**width-1)
@@ -38,8 +41,9 @@ module HDLRuby
                 unless val.to_value? then
                     # Not computable, use the former method that generates
                     # HDLRuby code.
-                    return self.send(orig_operator(op),value)
+                    return self.send(orig_operator(op),val)
                 end
+                val = val.to_value unless val.is_a?(Value)
                 # Handle Numeric op BitString case.
                 if self.content.is_a?(Numeric) && val.content.is_a?(BitString)
                     if val.content.specified? then
@@ -80,27 +84,29 @@ module HDLRuby
                     return self.send(orig_operator(op),val)
                 end
                 # Process left.
-                # unless left.is_a?(Numeric) || left.is_a?(BitString) then
-                #     left = left.to_value.content
-                # end
-                left = left.content
-                if left.is_a?(BitString) && !left.specified? then
-                    return self.class.new(self.type.base,
-                                          BitString::UNKNOWN.clone)
+                if left.is_a?(Value) then
+                    left = left.content
+                    if left.is_a?(BitString) && !left.specified? then
+                        return self.class.new(self.type.base,
+                                              BitString::UNKNOWN.clone)
+                    end
+                    # left = left.to_i
+                    left = self.trunc(left.to_i,val.first.type.width)
+                else
+                    left = left.to_i
                 end
-                # left = left.to_i
-                left = self.trunc(left.to_i,val.first.type.width)
                 # Process right.
-                # unless right.is_a?(Numeric) || right.is_a?(BitString) then
-                #     right = right.to_value.content
-                # end
-                right = right.content
-                if right.is_a?(BitString) && !right.specified? then
-                    return self.class.new(self.type.base,
-                                          BitString::UNKNOWN.clone)
+                if right.is_a?(Value) then
+                    right = right.content
+                    if right.is_a?(BitString) && !right.specified? then
+                        return self.class.new(self.type.base,
+                                              BitString::UNKNOWN.clone)
+                    end
+                    # right = right.to_i
+                    right = self.trunc(right.to_i,val.last.type.width)
+                else
+                    right = right.to_i
                 end
-                # right = right.to_i
-                right = self.trunc(right.to_i,val.last.type.width)
                 # Generate the resulting type.
                 res_type = self.type.base[(left-right+1).abs]
                 # Generate the resulting value.
@@ -124,18 +130,16 @@ module HDLRuby
                     return self.send(orig_operator(op),val)
                 end
                 # Process val.
-                index = val.content
-                if index.is_a?(BitString) && !index.specified? then
-                    return self.class.new(self.type.base,
-                                          BitString::UNKNOWN.clone)
+                if val.is_a?(Value) then
+                    index = val.content
+                    if index.is_a?(BitString) && !index.specified? then
+                        return self.class.new(self.type.base,
+                                              BitString::UNKNOWN.clone)
+                    end
+                    index = self.trunc(index.to_i,val.type.width)
+                else
+                    index = val.to_i
                 end
-                index = self.trunc(index.to_i,val.type.width)
-                # index = index.to_i
-                # if index >= self.type.size then
-                #     # puts "index=#{index}"
-                #     index %= self.type.size
-                #     # puts "now index=#{index}"
-                # end
                 # Generate the resulting type.
                 res_type = self.type.base
                 # Generate the resulting value.
@@ -308,7 +312,7 @@ module HDLRuby
                         break if count == width
                     end
                     if count < width then
-                        res_content.concat(res_content[-1] * (width-count))
+                        res_content.concat([res_content[-1]] * (width-count))
                     end
                 else
                     width.times do |p|

data/lib/HDLRuby/std/bram.rb

@@ -0,0 +1,22 @@
+module HDLRuby::High::Std
+
+    # Describe a RAM compatibile with BRAM of FPGAs.
+    # - 'widthA': address bit width
+    # - 'widthD': data bit width
+    system :bram do |widthA, widthD|
+        input :clk, :rwb
+        [widthA].input :addr
+        [widthD].input :din
+        [widthD].output :dout
+
+        # puts "widthA=#{widthA} widthD=#{widthD}"
+
+        bit[widthD][-2**widthA].inner mem: [ :"_b#{"0"*widthD}".to_value ] * 2**widthA
+
+        par(clk.negedge) do
+            hif(rwb == 1) { mem[addr] <= din }
+            dout <= mem[addr]
+        end
+    end
+
+end

data/lib/HDLRuby/std/fixpoint.rb

@@ -55,14 +55,14 @@ module HDLRuby::High::Std
                             if (typ.signed?) then
                                 (left.as(signed[isize+fsize*2])*right) >> fsize
                             else
-                                (left.as([isize+fsize*2])*right) >> fsize
+                                (left.as(bit[isize+fsize*2])*right) >> fsize
                             end
                         end
                         typ.define_operator(:/) do |left,right|
                             if (typ.signed?) then
                                 (left.as(signed[isize+fsize*2]) << fsize) / right
                             else
-                                (left.as([isize+fsize*2]) << fsize) / right
+                                (left.as(bit[isize+fsize*2]) << fsize) / right
                             end
                         end
                         # Define the removal of the point.