HDLRuby 2.11.11 → 2.11.12

data/lib/HDLRuby/hdr_samples/struct.rb

@@ -1,14 +1,48 @@
-system :dff do
-   input :clk, :rst, :d
-   output :q
-
-   par(clk.posedge) { q <= d & ~rst }
+typedef(:some_struct) do
+    { sub2: bit, sub3: bit[2] }
 end
 
 system :my_system do
-   input :clk, :rst
-   { sub0: bit, sub1: bit}.inner :sig
-   
-   dff(:dff0).(clk: clk, rst: rst)
-   dff0.d <= sig.sub0
+    inner :x
+    [3].inner :y
+    inner :z
+    { sub0: bit, sub1: bit[2]}.inner :sigA
+    some_struct.inner :sigB, :sigC
+
+    sigC <= sigA
+
+    par(sigA) { z <= ~z }
+
+
+    timed do
+        z <= 0
+        x <= 1
+        y <= _b000
+        !10.ns
+        sigA.sub0 <= 0
+        sigA.sub1 <= x
+        sigB.sub2 <= 0
+        sigB.sub3 <= x
+        !10.ns
+        sigA.sub0 <= x
+        sigA.sub1 <= ~sigB.sub3
+        sigB.sub2 <= x
+        sigB.sub3 <= ~sigA.sub1
+        !10.ns
+        sigA <= _b111
+        sigB <= _b111
+        !10.ns
+        sigA <= _b100
+        !10.ns
+        y <= sigA
+        sigB <= sigA
+        !10.ns
+        sigA <= _b011
+        !10.ns
+        sigB <= sigA
+        !10.ns
+        sigB <= sigA + 1
+        !10.ns
+    end
+
 end

data/lib/HDLRuby/hdr_samples/with_bram.rb

@@ -0,0 +1,45 @@
+require 'std/bram.rb'
+
+include HDLRuby::High::Std
+
+
+# A system testing the memory.
+system :bram_test do
+
+    widthA = 16
+    widthD = 8
+
+
+    input :clk,:rwb
+    [widthA].inner :addr
+    [widthD].inner  :din,:dout
+
+    bram(widthA,widthD).(:bramI).(clk,rwb,addr,din,dout)
+
+    timed do
+        clk  <= 0
+        rwb  <= 1
+        addr <= 0
+        din  <= 0
+        !10.ns
+        clk  <= 1
+        !10.ns
+        rwb <= 1
+        repeat(16) do
+            clk <= 0
+            !10.ns
+            clk <= 1
+            addr <= addr + 1
+            din <= din + 1
+            !10.ns
+        end
+        rwb <= 0
+        repeat(16) do
+            clk <= 0
+            !10.ns
+            clk <= 1
+            addr <= addr-1
+            !10.ns
+        end
+    end
+end

data/lib/HDLRuby/hdr_samples/with_casts.rb

@@ -6,9 +6,9 @@ system :with_cast do
     [9].inner :val2,:val3
 
     timed do
-        val0 <= _11111111
-        val1 <= _00000010
-        val3 <= _000000000
+        val0 <= _b11111111
+        val1 <= _b00000010
+        val3 <= _b000000000
         count <= 0
         !10.ns
         count <= 1

data/lib/HDLRuby/hdr_samples/with_concat.rb

@@ -10,16 +10,16 @@ system :with_concat do
     val3 <= [val2,val0]
 
     timed do
-        val0 <= _1111
-        val1 <= _0000
+        val0 <= _b1111
+        val1 <= _b0000
         count <= 0
         !10.ns
-        val0 <= _1001
-        val1 <= _0110
+        val0 <= _b1001
+        val1 <= _b0110
         count <= 1
         !10.ns
-        val0 <= _1010
-        val1 <= _0101
+        val0 <= _b1010
+        val1 <= _b0101
         count <= 2
         !10.ns
     end

data/lib/HDLRuby/hdr_samples/with_connector_memory.rb

@@ -12,8 +12,8 @@ system :channel_connector do
     address_width = 4 # lutのアドレスのビット幅
     typ = signed[integer_width + decimal_width] # データ型
     
-    inputs_x = _00010011
-    inputs_h = _10100001
+    inputs_x = _b00010011
+    inputs_h = _b10100001
     columns = [2, 2, 1]
 
     inner :clk,   # clock

data/lib/HDLRuby/hdr_samples/with_def.rb

@@ -9,11 +9,18 @@ end
 system :def_bench do
 
     [2].inner :addr
-    [8].inner :val0, :val1
+    [8].inner :val0, :val1, :val2, :val3
 
     par do
-        val0 <= lut84([0,1,4,9],addr)
-        val1 <= lut84([0,1,4,9],3-addr)
+        val0 <= lut84([_b8d0,_b8d1,_b8d4,_b8d9],addr)
+        val1 <= lut84([_b8d0,_b8d1,_b8d4,_b8d9],3-addr)
+    end
+
+    bit[8][-4].inner otbl: [_b8d0,_b8d1,_b8d4,_b8d9]
+
+    par do
+        val2 <= otbl[addr]
+        val3 <= otbl[3-addr]
     end
 
     timed do

data/lib/HDLRuby/hdr_samples/with_define_operator.rb

@@ -0,0 +1,44 @@
+# A sample for testing define operator.
+
+typedef :sat100 do |width|
+    signed[width]
+end
+
+sat100.define_operator(:+) do |width, x,y|
+    tmp = x.as(bit[width]) + y.as(bit[width])
+    mux(tmp > 100,tmp,100)
+end
+
+typedef :sat do |width, max|
+    signed[width]
+end
+
+sat.define_operator(:+) do |width,max, x,y|
+    tmp = x.as(bit[width]) + y.as(bit[width])
+    mux(tmp > max, tmp, max)
+end
+
+
+system :bench_sat do
+    sat100(8).inner :x,:y,:z
+    sat(8,55).inner :u,:v,:w
+
+    timed do
+        x <= 40
+        y <= 32
+        z <= x+y
+        !10.ns
+        u <= 20
+        v <= 24
+        w <= u+v
+        !10.ns
+        x <= 70
+        y <= 32
+        z <= x+y
+        !10.ns
+        u <= 50
+        v <= 24
+        w <= u+v
+        !10.ns
+    end
+end

data/lib/HDLRuby/hdr_samples/with_fixpoint.rb

@@ -14,9 +14,9 @@ system :fix_test do
 
     # Performs calculation between then
     timed do
-        # x <= _00110011 # 3.1875
+        # x <= _b00110011 # 3.1875
         x <= 3.1875.to_fix(4)
-        y <= _01000000 # 4
+        y <= _b01000000 # 4
         !10.ns
         z <= x + y
         !10.ns
@@ -24,8 +24,8 @@ system :fix_test do
         !10.ns
         z <= z / x
         !10.ns
-        a <= _00010000
-        b <= _00001111
+        a <= _b00010000
+        b <= _b00001111
         !10.ns
         c <= a * b
         d <= 0
@@ -49,15 +49,15 @@ system :fix_test do
         !10.ns
         c <= a * b
         !10.ns
-        # a <= _00010000
-        # b <= _00010101
-        a <= _0000111x
-        b <= _1110011x
+        # a <= _b00010000
+        # b <= _b00010101
+        a <= _sb0000111x
+        b <= _sb1110011x
         !10.ns
-        # a <= a & _11111110
-        # b <= b | _00000001
-        a <= a | _00000001
-        b <= b | _00000001
+        # a <= a & _b11111110
+        # b <= b | _b00000001
+        a <= a | _b00000001
+        b <= b | _b00000001
         !10.ns
         c <= a * b
         !10.ns

data/lib/HDLRuby/hdr_samples/with_init.rb

@@ -2,9 +2,9 @@
 # A benchmark for testing the initialization of signals.
 system :with_init do
     [8].constant cst0: 127
-    constant cst1: _1
-    [8].inner sig0: _10000000
-    inner sig1: _1
+    constant cst1: _b1
+    [8].inner sig0: _b10000000
+    inner sig1: _b1
     [8].inner :sig2
 
     timed do

data/lib/HDLRuby/hdr_samples/with_leftright.rb

@@ -0,0 +1,21 @@
+# A benchmark for the cases where a left value is also a right value
+# in a block without sensitivity list.
+system :leftright_bench do
+    [8].inner :l,:r0,:r1,:lr
+
+    par do
+        lr <= r0*2
+        l <= [lr[7],lr[6..0]].to_expr + r1
+    end
+
+    timed do
+        !10.ns
+        r0 <= 1
+        !10.ns
+        r1 <= 2
+        !10.ns
+        r0 <= 3
+        r1 <= 4
+        !10.ns
+    end
+end

data/lib/HDLRuby/hdr_samples/with_reduce.rb

@@ -6,33 +6,33 @@ system :with_reduce_bench do
     [64].inner :val64
 
     timed do
-        val <= _01101010
-        res <= val.reduce(_00000000,:+)
+        val <= _b01101010
+        res <= val.reduce(_b00000000,:+)
         !10.ns
         val <= _01010010
-        res <= val.reduce(_00000000,:+)
+        res <= val.reduce(_b00000000,:+)
         !10.ns
         val <= _01101111
-        res <= val.reduce(_00000000,:+)
+        res <= val.reduce(_b00000000,:+)
         !10.ns
-        val64 <= _0110101001101010011010100110101001101010011010100110101001101010
-        res <= val64.reduce(_00000000,:+)
+        val64 <= _b0110101001101010011010100110101001101010011010100110101001101010
+        res <= val64.reduce(_b00000000,:+)
         !10.ns
         res <= val64[7..0]
         !10.ns
-        res <= res.reduce(_00000000,:+)
+        res <= res.reduce(_b00000000,:+)
         !10.ns
         res <= val64[63..60]
         !10.ns
-        res <= res.reduce(_00000000,:+)
+        res <= res.reduce(_b00000000,:+)
         !10.ns
         val64 <= ~(val64 ^ val64)
-        res <= val64.reduce(_00000000,:+)
+        res <= val64.reduce(_b00000000,:+)
         !10.ns
-        val64[0] <= _0
-        val64[3] <= _0
-        val64[63] <= _0
-        res <= val64.reduce(_00000000,:+)
+        val64[0] <= _b0
+        val64[3] <= _b0
+        val64[63] <= _b0
+        res <= val64.reduce(_b00000000,:+)
         !10.ns
     end
 end

data/lib/HDLRuby/hdr_samples/with_ref_array.rb

@@ -10,16 +10,16 @@ system :with_concat do
     val3[6..3] <= val1[7..4]
 
     timed do
-        val0 <= _00001111
-        val1 <= _11000011
+        val0 <= _b00001111
+        val1 <= _b11000011
         count <= 0
         !10.ns
-        val0 <= _11110000
-        val1 <= _00111100
+        val0 <= _b11110000
+        val1 <= _b00111100
         count <= 1
         !10.ns
-        val0 <= _10101010
-        val1 <= _01010101
+        val0 <= _b10101010
+        val1 <= _b01010101
         count <= 2
         !10.ns
     end

data/lib/HDLRuby/hdr_samples/with_subsums.rb

@@ -20,13 +20,13 @@ system :with_concat do
     val6 <= bs.reduce(:+)
 
     timed do
-        val0 <= _1111000011110000
+        val0 <= _b1111000011110000
         count <= 0
         !10.ns
-        val0 <= _0000111100001111
+        val0 <= _b0000111100001111
         count <= 1
         !10.ns
-        val0 <= _1010101010101010
+        val0 <= _b1010101010101010
         count <= 2
         !10.ns
     end

data/lib/HDLRuby/hdr_samples/with_terminate.rb

@@ -2,9 +2,9 @@
 # A benchmark for testing the terminate statement.
 system :with_terminate do
     [8].constant cst0: 127
-    constant cst1: _1
-    [8].inner sig0: _10000000
-    inner sig1: _1
+    constant cst1: _b1
+    [8].inner sig0: _b10000000
+    inner sig1: _b1
     [8].inner :sig2
     [8].inner count: 0
 

data/lib/HDLRuby/hdr_samples/with_to_a.rb

@@ -52,26 +52,26 @@ system :with_to_a_bench do
     four2sixfour(:my_four2sixfour).(four,*(sixfour.to_a.reverse))
 
     timed do
-        val <= _01101010
+        val <= _b01101010
         res <= vals.reverse
         !10.ns
-        val64 <= _0110101001101010011010100110101001101010011010100110101001101010
+        val64 <= _b0110101001101010011010100110101001101010011010100110101001101010
         res64 <= val64s.reverse
         !10.ns
-        val <= _00000000
-        val64 <= _0000000000000000000000000000000000000000000000000000000000000000
+        val <= _b00000000
+        val64 <= _b0000000000000000000000000000000000000000000000000000000000000000
         !10.ns
         vals.each.with_index do |v,i|
-            v <= (i/2) & _1
+            v <= (i/2) & _b1
         end
         res <= val
         !10.ns
         val64s.each.with_index do |v,i|
-            v <= (i/2) & _1
+            v <= (i/2) & _b1
         end
         res64 <= val64
         !10.ns
-        val <= _01010011
+        val <= _b01010011
         !10.ns
         8.times do |i|
             val64s[i] <= val[i]
@@ -80,11 +80,11 @@ system :with_to_a_bench do
         end
         res64 <= val64
         !10.ns
-        four <= _0000
+        four <= _b0000
         !10.ns
-        four <= _0001
+        four <= _b0001
         !10.ns
-        four <= _1100
+        four <= _b1100
         !10.ns
     end
 end

data/lib/HDLRuby/hdr_samples/with_values.rb

@@ -11,7 +11,7 @@ system :with_values do
 
 
     timed do
-        v1  <= 0
+        v1  <= _b0
         v8  <= 0
         v16 <= 0
         v32 <= 0
@@ -19,7 +19,7 @@ system :with_values do
         v64 <= 0
         v96 <= 0
         !10.ns
-        v1  <= 1
+        v1  <= _b1
         v8  <= 1
         v16 <= 1
         v32 <= 1
@@ -27,7 +27,7 @@ system :with_values do
         v64 <= 1
         v96 <= 1
         !10.ns
-        v1  <= _1010[2]
+        v1  <= _b1010[2]
         v8  <= _uhFF00[12..4]
         !10.ns
         v8  <= 128

data/lib/HDLRuby/hdrcc.rb

@@ -60,6 +60,7 @@ require 'HDLRuby/hruby_check.rb'
 require 'HDLRuby/hruby_low2hdr'
 require 'HDLRuby/hruby_low2c'
 require 'HDLRuby/hruby_low2vhd'
+require 'HDLRuby/hruby_low_without_subsignals'
 require 'HDLRuby/hruby_low_fix_types'
 # require 'HDLRuby/hruby_low_expand_types' # For now dormant
 require 'HDLRuby/hruby_low_without_outread'
@@ -641,8 +642,12 @@ elsif $options[:clang] then
     # top_system = $top_system
     # Preprocess the HW description for valid C generation.
     $top_system.each_systemT_deep do |systemT|
+        HDLRuby.show? "signal2subs step..."
+        # Ensure there is not implicit assign to sub signals.
+        systemT.signal2subs!
+        HDLRuby.show? "#{Time.now}#{show_mem}"
         HDLRuby.show? "seq2seq step..."
-        # Coverts the par blocks in seq blocks to seq blocks to match
+        # Converts the par blocks in seq blocks to seq blocks to match
         # the simulation engine.
         systemT.par_in_seq2seq!
         HDLRuby.show? "#{Time.now}#{show_mem}"
@@ -801,6 +806,9 @@ elsif $options[:verilog] then
     # top_system = $top_system
     # Make description compatible with verilog generation.
     $top_system.each_systemT_deep do |systemT|
+        HDLRuby.show? "signal2subs step..."
+        # Ensure there is not implicit assign to sub signals.
+        systemT.signal2subs!
         # HDLRuby.show "casts_without_expression! step..."
         # systemT.casts_without_expression!
         # HDLRuby.show Time.now
@@ -889,6 +897,8 @@ elsif $options[:rcsim] then
     require 'HDLRuby/hruby_rcsim.rb'
     # Merge the included from the top system.
     $top_system.merge_included!
+    # Process par in seq.
+    $top_system.par_in_seq2seq!
     # Generate the C data structures.
     $top_system.to_rcsim
     HDLRuby.show "Executing the hybrid C-Ruby-level simulator..."
@@ -902,6 +912,9 @@ elsif $options[:vhdl] then
     # top_system = $top_system
     # Make description compatible with vhdl generation.
     $top_system.each_systemT_deep do |systemT|
+        HDLRuby.show? "signal2subs step..."
+        # Ensure there is not implicit assign to sub signals.
+        systemT.signal2subs!
         systemT.outread2inner!            unless $options[:vhdl08] || $options[:alliance]
         systemT.with_boolean!
         systemT.boolean_in_assign2select! unless $options[:alliance]

data/lib/HDLRuby/hruby_bstr.rb

@@ -225,6 +225,7 @@ module HDLRuby
         #       * when index is larger than the bit width, the bit string is
         #         X extended accordingly.
         def []=(index,value)
+            # puts "first @content=#{@content}"
             # Change inside the bit string, it is not know any longer if it
             # is specified or not
             @specified = nil
@@ -250,8 +251,8 @@ module HDLRuby
                     sign = @content[-1]
                     @content.concat([sign] * (right-@content.size+1))
                 end
+                # puts "left=#{left} right=#{right} sign=#{sign} @content=#{@content}"
                 if right >= left then
-                    # puts "left=#{left} right=#{right} value=#{value} (#{value.class})"
                     # Sets the value to a copy of the bit string.
                     @content[left..right] = value.is_a?(BitString) ?
                         value.raw_content[0..right-left] : 
@@ -412,10 +413,14 @@ module HDLRuby
             return @specified
         end
 
-        # # Coerces.
-        # def coerce(other)
-        #     return [BitString.new(other),self]
-        # end
+        # Coerces.
+        def coerce(other)
+            if other.is_a?(Numeric) && self.specified? then
+                return [other,self.to_i]
+            else
+                return [BitString.new(other),self]
+            end
+        end
 
         # String conversion table.
         B2S_T = [ "0", "1", "z", "x" ]