yowasp-yosys 0.56.0.141.post974.dev0__py3-none-any.whl → 0.58.0.0.post1010__py3-none-any.whl

yowasp_yosys/share/include/kernel/threading.h

@@ -0,0 +1,186 @@
+#include <deque>
+
+#ifdef YOSYS_ENABLE_THREADS
+#include <condition_variable>
+#include <mutex>
+#include <thread>
+#endif
+
+#include "kernel/yosys_common.h"
+#include "kernel/log.h"
+
+#ifndef YOSYS_THREADING_H
+#define YOSYS_THREADING_H
+
+YOSYS_NAMESPACE_BEGIN
+
+// Concurrent queue implementation. Not fast, but simple.
+// Multi-producer, multi-consumer, optionally bounded.
+// When YOSYS_ENABLE_THREADS is not defined, this is just a non-thread-safe non-blocking deque.
+template <typename T>
+class ConcurrentQueue
+{
+public:
+	ConcurrentQueue(int capacity = INT_MAX)
+		: capacity(capacity) {}
+	// Push an element into the queue. If it's at capacity, block until there is room.
+	void push_back(T t)
+	{
+#ifdef YOSYS_ENABLE_THREADS
+		std::unique_lock<std::mutex> lock(mutex);
+		not_full_condition.wait(lock, [this] { return static_cast<int>(contents.size()) < capacity; });
+		if (contents.empty())
+			not_empty_condition.notify_one();
+#endif
+		log_assert(!closed);
+		contents.push_back(std::move(t));
+#ifdef YOSYS_ENABLE_THREADS
+		if (static_cast<int>(contents.size()) < capacity)
+			not_full_condition.notify_one();
+#endif
+	}
+	// Signal that no more elements will be produced. `pop_front()` will return nullopt.
+	void close()
+	{
+#ifdef YOSYS_ENABLE_THREADS
+		std::unique_lock<std::mutex> lock(mutex);
+		not_empty_condition.notify_all();
+#endif
+		closed = true;
+	}
+	// Pop an element from the queue. Blocks until an element is available
+	// or the queue is closed and empty.
+	std::optional<T> pop_front()
+	{
+		return pop_front_internal(true);
+	}
+	// Pop an element from the queue. Does not block, just returns nullopt if the
+	// queue is empty.
+	std::optional<T> try_pop_front()
+	{
+		return pop_front_internal(false);
+	}
+private:
+#ifdef YOSYS_ENABLE_THREADS
+	std::optional<T> pop_front_internal(bool wait)
+	{
+		std::unique_lock<std::mutex> lock(mutex);
+		if (wait) {
+			not_empty_condition.wait(lock, [this] { return !contents.empty() || closed; });
+		}
+#else
+	std::optional<T> pop_front_internal(bool)
+	{
+#endif
+		if (contents.empty())
+			return std::nullopt;
+#ifdef YOSYS_ENABLE_THREADS
+		if (static_cast<int>(contents.size()) == capacity)
+			not_full_condition.notify_one();
+#endif
+		T result = std::move(contents.front());
+		contents.pop_front();
+#ifdef YOSYS_ENABLE_THREADS
+		if (!contents.empty())
+			not_empty_condition.notify_one();
+#endif
+		return std::move(result);
+	}
+
+#ifdef YOSYS_ENABLE_THREADS
+	std::mutex mutex;
+	// Signals one waiter thread when the queue changes and is not full.
+	std::condition_variable not_full_condition;
+	// Signals one waiter thread when the queue changes and is not empty.
+	std::condition_variable not_empty_condition;
+#endif
+	std::deque<T> contents;
+	int capacity;
+	bool closed = false;
+};
+
+class DeferredLogs
+{
+public:
+	template <typename... Args>
+	void log(FmtString<TypeIdentity<Args>...> fmt, Args... args)
+	{
+		logs.push_back({fmt.format(args...), false});
+	}
+	template <typename... Args>
+	void log_error(FmtString<TypeIdentity<Args>...> fmt, Args... args)
+	{
+		logs.push_back({fmt.format(args...), true});
+	}
+	void flush();
+private:
+	struct Message
+	{
+		std::string text;
+		bool error;
+	};
+	std::vector<Message> logs;
+};
+
+class ThreadPool
+{
+public:
+	// Computes the number of worker threads to use.
+	// `reserved_cores` cores are set aside for other threads (e.g. work on the main thread).
+	// `max_threads` --- don't return more workers than this.
+	// The result may be 0.
+	static int pool_size(int reserved_cores, int max_threads);
+
+	// Create a pool of threads running the given closure (parameterized by thread number).
+	// `pool_size` must be the result of a `pool_size()` call.
+	ThreadPool(int pool_size, std::function<void(int)> b);
+	ThreadPool(ThreadPool &&other) = delete;
+	// Waits for all threads to terminate. Make sure those closures return!
+	~ThreadPool();
+
+	// Return the number of threads in the pool.
+	int num_threads() const
+	{
+#ifdef YOSYS_ENABLE_THREADS
+		return threads.size();
+#else
+		return 0;
+#endif
+	}
+private:
+	std::function<void(int)> body;
+#ifdef YOSYS_ENABLE_THREADS
+	std::vector<std::thread> threads;
+#endif
+};
+
+template <class T>
+class ConcurrentStack
+{
+public:
+	void push_back(T &&t) {
+#ifdef YOSYS_ENABLE_THREADS
+		std::lock_guard<std::mutex> lock(mutex);
+#endif
+		contents.push_back(std::move(t));
+	}
+	std::optional<T> try_pop_back() {
+#ifdef YOSYS_ENABLE_THREADS
+		std::lock_guard<std::mutex> lock(mutex);
+#endif
+		if (contents.empty())
+			return std::nullopt;
+		T result = std::move(contents.back());
+		contents.pop_back();
+		return result;
+	}
+private:
+#ifdef YOSYS_ENABLE_THREADS
+	std::mutex mutex;
+#endif
+	std::vector<T> contents;
+};
+
+YOSYS_NAMESPACE_END
+
+#endif // YOSYS_THREADING_H

yowasp_yosys/share/include/kernel/utils.h

@@ -21,6 +21,7 @@
 // do not depend on any other components of yosys (except stuff like log_*).
 
 #include "kernel/yosys.h"
+#include <iterator>
 
 #ifndef UTILS_H
 #define UTILS_H
@@ -276,6 +277,16 @@ inline int ceil_log2(int x)
 #endif
 }
 
+template <typename T>
+auto reversed(const T& container) {
+    struct reverse_view {
+        const T& cont;
+        auto begin() const { return cont.rbegin(); }
+        auto end() const { return cont.rend(); }
+    };
+    return reverse_view{container};
+}
+
 YOSYS_NAMESPACE_END
 
 #endif

yowasp_yosys/share/include/kernel/yosys_common.h

@@ -20,6 +20,7 @@
 #ifndef YOSYS_COMMON_H
 #define YOSYS_COMMON_H
 
+#include <array>
 #include <map>
 #include <set>
 #include <tuple>
@@ -141,7 +142,12 @@
 #define YOSYS_CONSTEVAL constexpr
 #endif
 
-#define YOSYS_ABORT(s) abort()
+#define YOSYS_ABORT(s) YOSYS_NAMESPACE_PREFIX log_yosys_abort_message(__FILE__, __LINE__, __FUNCTION__, s)
+
+// This has to precede including "kernel/io.h"
+YOSYS_NAMESPACE_BEGIN
+[[noreturn]] void log_yosys_abort_message(std::string_view file, int line, std::string_view func, std::string_view message);
+YOSYS_NAMESPACE_END
 
 #include "kernel/io.h"
 
@@ -205,13 +211,13 @@ namespace RTLIL {
 	struct Module;
 	struct Design;
 	struct Monitor;
-    struct Selection;
+	struct Selection;
 	struct SigChunk;
 	enum State : unsigned char;
 
 	typedef std::pair<SigSpec, SigSpec> SigSig;
 
-    namespace ID {}
+	namespace ID {}
 }
 
 namespace AST {
@@ -276,16 +282,6 @@ RTLIL::IdString new_id_suffix(std::string file, int line, std::string func, std:
 #define NEW_ID_SUFFIX(suffix) \
 	YOSYS_NAMESPACE_PREFIX new_id_suffix(__FILE__, __LINE__, __FUNCTION__, suffix)
 
-// Create a statically allocated IdString object, using for example ID::A or ID($add).
-//
-// Recipe for Converting old code that is using conversion of strings like ID::A and
-// "$add" for creating IdStrings: Run below SED command on the .cc file and then use for
-// example "meld foo.cc foo.cc.orig" to manually compile errors, if necessary.
-//
-//  sed -i.orig -r 's/"\\\\([a-zA-Z0-9_]+)"/ID(\1)/g; s/"(\$[a-zA-Z0-9_]+)"/ID(\1)/g;' <filename>
-//
-#define ID(_id) ([]() { const char *p = "\\" #_id, *q = p[1] == '$' ? p+1 : p; \
-        static const YOSYS_NAMESPACE_PREFIX RTLIL::IdString id(q); return id; })()
 namespace ID = RTLIL::ID;
 
 

yowasp_yosys/share/include/passes/fsm/fsmdata.h

@@ -45,35 +45,27 @@ struct FsmData
 		cell->parameters[ID::STATE_NUM] = RTLIL::Const(state_table.size());
 		cell->parameters[ID::STATE_NUM_LOG2] = RTLIL::Const(state_num_log2);
 		cell->parameters[ID::STATE_RST] = RTLIL::Const(reset_state);
-		cell->parameters[ID::STATE_TABLE] = RTLIL::Const();
-
-		for (int i = 0; i < int(state_table.size()); i++) {
-			std::vector<RTLIL::State> &bits_table = cell->parameters[ID::STATE_TABLE].bits();
-			std::vector<RTLIL::State> &bits_state = state_table[i].bits();
-			bits_table.insert(bits_table.end(), bits_state.begin(), bits_state.end());
-		}
+		RTLIL::Const cell_state_table;
+		for (const RTLIL::Const &c : state_table)
+			cell_state_table.append(c);
+		cell->parameters[ID::STATE_TABLE] = std::move(cell_state_table);
 
 		cell->parameters[ID::TRANS_NUM] = RTLIL::Const(transition_table.size());
-		cell->parameters[ID::TRANS_TABLE] = RTLIL::Const();
+		RTLIL::Const cell_trans_table;
 		for (int i = 0; i < int(transition_table.size()); i++)
 		{
-			std::vector<RTLIL::State> &bits_table = cell->parameters[ID::TRANS_TABLE].bits();
 			transition_t &tr = transition_table[i];
 
 			RTLIL::Const const_state_in = RTLIL::Const(tr.state_in, state_num_log2);
 			RTLIL::Const const_state_out = RTLIL::Const(tr.state_out, state_num_log2);
-			std::vector<RTLIL::State> &bits_state_in = const_state_in.bits();
-			std::vector<RTLIL::State> &bits_state_out = const_state_out.bits();
-
-			std::vector<RTLIL::State> &bits_ctrl_in = tr.ctrl_in.bits();
-			std::vector<RTLIL::State> &bits_ctrl_out = tr.ctrl_out.bits();
 
 			// append lsb first
-			bits_table.insert(bits_table.end(), bits_ctrl_out.begin(), bits_ctrl_out.end());
-			bits_table.insert(bits_table.end(), bits_state_out.begin(), bits_state_out.end());
-			bits_table.insert(bits_table.end(), bits_ctrl_in.begin(), bits_ctrl_in.end());
-			bits_table.insert(bits_table.end(), bits_state_in.begin(), bits_state_in.end());
+			cell_trans_table.append(tr.ctrl_out);
+			cell_trans_table.append(const_state_out);
+			cell_trans_table.append(tr.ctrl_in);
+			cell_trans_table.append(const_state_in);
 		}
+		cell->parameters[ID::TRANS_TABLE] = std::move(cell_trans_table);
 	}
 
 	void copy_from_cell(RTLIL::Cell *cell)
@@ -95,25 +87,18 @@ struct FsmData
 		const RTLIL::Const &trans_table = cell->parameters[ID::TRANS_TABLE];
 
 		for (int i = 0; i < state_num; i++) {
-			RTLIL::Const state_code;
-			int off_begin = i*state_bits, off_end = off_begin + state_bits;
-			state_code.bits().insert(state_code.bits().begin(), state_table.begin()+off_begin, state_table.begin()+off_end);
+			int off_begin = i*state_bits;
+			RTLIL::Const state_code = state_table.extract(off_begin, state_bits);
 			this->state_table.push_back(state_code);
 		}
 
 		for (int i = 0; i < trans_num; i++)
 		{
-			auto off_ctrl_out = trans_table.begin() + i*(num_inputs+num_outputs+2*state_num_log2);
-			auto off_state_out = off_ctrl_out + num_outputs;
-			auto off_ctrl_in = off_state_out + state_num_log2;
-			auto off_state_in = off_ctrl_in + num_inputs;
-			auto off_end = off_state_in + state_num_log2;
-
-			RTLIL::Const state_in, state_out, ctrl_in, ctrl_out;
-			ctrl_out.bits().insert(ctrl_out.bits().begin(), off_ctrl_out, off_state_out);
-			state_out.bits().insert(state_out.bits().begin(), off_state_out, off_ctrl_in);
-			ctrl_in.bits().insert(ctrl_in.bits().begin(), off_ctrl_in, off_state_in);
-			state_in.bits().insert(state_in.bits().begin(), off_state_in, off_end);
+			int base_offset = i*(num_inputs+num_outputs+2*state_num_log2);
+			RTLIL::Const ctrl_out = trans_table.extract(base_offset, num_outputs);
+			RTLIL::Const state_out = trans_table.extract(base_offset + num_outputs, state_num_log2);
+			RTLIL::Const ctrl_in = trans_table.extract(base_offset + num_outputs + state_num_log2, num_inputs);
+			RTLIL::Const state_in = trans_table.extract(base_offset + num_outputs + state_num_log2 + num_inputs, state_num_log2);
 
 			transition_t tr;
 			tr.state_in = state_in.as_int();
@@ -134,7 +119,7 @@ struct FsmData
 	{
 		log("-------------------------------------\n");
 		log("\n");
-		log("  Information on FSM %s (%s):\n", cell->name.c_str(), cell->parameters[ID::NAME].decode_string().c_str());
+		log("  Information on FSM %s (%s):\n", cell->name, cell->parameters[ID::NAME].decode_string());
 		log("\n");
 		log("  Number of input signals:  %3d\n", num_inputs);
 		log("  Number of output signals: %3d\n", num_outputs);

yowasp_yosys/share/include/passes/techmap/libparse.h

@@ -204,7 +204,7 @@ namespace Yosys
 			}
 			ast = shared_ast.get();
 			if (!ast) {
-				log_error("No entries found in liberty file `%s'.\n", fname.c_str());
+				log_error("No entries found in liberty file `%s'.\n", fname);
 			}
 		}
 #endif

yowasp_yosys/share/lattice/cells_bb_ecp5.v

@@ -19,6 +19,8 @@ endmodule
 
 (* blackbox *)
 module DP16KD (...);
+    parameter CLKAMUX = "CLKA";
+    parameter CLKBMUX = "CLKB";
     parameter DATA_WIDTH_A = 18;
     parameter DATA_WIDTH_B = 18;
     parameter REGMODE_A = "NOREG";
@@ -215,6 +217,8 @@ endmodule
 
 (* blackbox *)
 module PDPW16KD (...);
+    parameter CLKRMUX = "CLKR";
+    parameter CLKWMUX = "CLKW";
     parameter DATA_WIDTH_W = 36;
     parameter DATA_WIDTH_R = 36;
     parameter GSR = "ENABLED";

yowasp_yosys/share/python3/sby_engine_abc.py

@@ -203,7 +203,7 @@ def run(mode, task, engine_idx, engine):
         match = re.match(r"^Proved output +([0-9]+) in frame +-?[0-9]+", line)
         if match:
             output = int(match[1])
-            prop = aiger_props[output]
+            prop = aiger_props[output] if aiger_props else None
             if prop:
                 prop.status = "PASS"
                 task.summary.add_event(
@@ -232,7 +232,7 @@ def run(mode, task, engine_idx, engine):
                 disproved_count = int(match[3])
                 undecided_count = int(match[4])
                 if (
-                    all_count != len(aiger_props) or
+                    (aiger_props and all_count != len(aiger_props)) or
                     all_count != proved_count + disproved_count + undecided_count or
                     disproved_count != len(disproved) or
                     proved_count != len(proved)
@@ -246,6 +246,9 @@ def run(mode, task, engine_idx, engine):
                 else:
                     proc_status = "FAIL"
 
+        match = re.match("Error: (Does not work|Only works) for (sequential|combinational) networks.", line)
+        if match: proc_status = "ERROR"
+
         return line
 
     def exit_callback(retcode):

yowasp_yosys/share/simlib.v

@@ -31,6 +31,14 @@
  *
  */
 
+// If using Verilator, define SIMLIB_VERILATOR_COMPAT
+`ifdef SIMLIB_VERILATOR_COMPAT
+ /* verilator lint_save */
+ /* verilator lint_off DEFOVERRIDE */
+ `define SIMLIB_NOCONNECT
+ /* verilator lint_restore */
+`endif
+
 // --------------------------------------------------------
 //* ver 2
 //* title Bit-wise inverter
@@ -3216,3 +3224,29 @@ module \$scopeinfo ();
 parameter TYPE = "";
 
 endmodule
+
+// --------------------------------------------------------
+//* group wire
+`ifndef SIMLIB_NOCONNECT
+
+module \$connect (A, B);
+
+parameter WIDTH = 0;
+
+inout [WIDTH-1:0] A;
+inout [WIDTH-1:0] B;
+
+tran connect[WIDTH-1:0] (A, B);
+
+endmodule
+
+`endif
+// --------------------------------------------------------
+//* group wire
+module \$input_port (Y);
+
+parameter WIDTH = 0;
+
+inout [WIDTH-1:0] Y;
+
+endmodule

yowasp_yosys/share/techmap.v

@@ -283,9 +283,16 @@ module _90_alu (A, B, CI, BI, X, Y, CO);
 	\$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(Y_WIDTH)) A_conv (.A(A), .Y(A_buf));
 	\$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) B_conv (.A(B), .Y(B_buf));
 
-	\$lcu #(.WIDTH(Y_WIDTH)) lcu (.P(X), .G(AA & BB), .CI(CI), .CO(CO));
+	(* force_downto *)
+	wire [Y_WIDTH-1:0] P;
+	wire [Y_WIDTH-1:0] G;
+	wire [Y_WIDTH-1:0] Cnull;
+	assign Cnull = 1'b0;
+
+	\$fa #(.WIDTH(Y_WIDTH)) fa (.A(AA), .B(BB), .C(Cnull), .X(G), .Y(P));
+	\$lcu #(.WIDTH(Y_WIDTH)) lcu (.P(P), .G(G), .CI(CI), .CO(CO));
 
-	assign X = AA ^ BB;
+	assign X = P;
 	assign Y = X ^ {CO, CI};
 endmodule
 
@@ -647,3 +654,28 @@ module _90_lut;
 endmodule
 `endif
 
+
+// --------------------------------------------------------
+// Bufnorm helpers
+// --------------------------------------------------------
+
+(* techmap_celltype = "$connect" *)
+module \$connect (A, B);
+
+parameter WIDTH = 0;
+
+inout [WIDTH-1:0] A;
+inout [WIDTH-1:0] B;
+
+assign A = B; // RTLIL assignments are not inherently directed
+
+endmodule
+
+(* techmap_celltype = "$input_port" *)
+module \$input_port (Y);
+
+parameter WIDTH = 0;
+
+inout [WIDTH-1:0] Y; // This cell is just a maker, so we leave Y undriven
+
+endmodule

yowasp_yosys/smtbmc.py

@@ -1875,6 +1875,11 @@ elif covermode:
             smt_assert_antecedent("(|%s_t| s%d s%d)" % (topmod, step-1, step))
             smt_assert_antecedent("(not (|%s_is| s%d))" % (topmod, step))
 
+        if step < skip_steps:
+            print_msg("Skipping step %d.." % (step))
+            step += 1
+            continue
+
         while "1" in cover_mask:
             print_msg("Checking cover reachability in step %d.." % (step))
             smt_push()

{yowasp_yosys-0.56.0.141.post974.dev0.dist-info → yowasp_yosys-0.58.0.0.post1010.dist-info}/METADATA

@@ -1,6 +1,6 @@
 Metadata-Version: 2.4
 Name: yowasp-yosys
-Version: 0.56.0.141.post974.dev0
+Version: 0.58.0.0.post1010
 Summary: Yosys Open SYnthesis Suite
 Author-email: Catherine <whitequark@whitequark.org>
 License-Expression: ISC