yowasp-yosys 0.56.0.141.post974.dev0__py3-none-any.whl → 0.58.0.0.post1010__py3-none-any.whl

yowasp_yosys/share/gowin/cells_sim.v

@@ -1958,14 +1958,6 @@ parameter FREQ_DIV = 100;
 parameter REGULATOR_EN = 1'b0;
 endmodule
 
-(* blackbox *)
-module DCS (CLK0, CLK1, CLK2, CLK3, CLKSEL, SELFORCE, CLKOUT);
-input CLK0, CLK1, CLK2, CLK3, SELFORCE;
-input [3:0] CLKSEL;
-output CLKOUT;
-parameter DCS_MODE = "RISING";
-endmodule
-
 (* blackbox *)
 module EMCU (
   input          FCLK,

yowasp_yosys/share/gowin/cells_xtra_gw1n.v

@@ -1109,6 +1109,13 @@ parameter IDLE    =  4'd0,
 		  RD_S2   =  4'd12;
 endmodule
 
+module DCS (...);
+input CLK0, CLK1, CLK2, CLK3, SELFORCE;
+input [3:0] CLKSEL;
+output CLKOUT;
+  parameter DCS_MODE = "RISING";  
+endmodule
+
 module DQCE (...);
 input CLKIN;
 input CE;

yowasp_yosys/share/gowin/cells_xtra_gw2a.v

@@ -1082,6 +1082,11 @@ input RLOADN, RMOVE, RDIR, WLOADN, WMOVE, WDIR, HOLD;
 output DQSR90, DQSW0, DQSW270; 
 output [2:0] RPOINT, WPOINT;
 output RVALID,RBURST, RFLAG, WFLAG;
+    parameter FIFO_MODE_SEL = 1'b0; 
+    parameter RD_PNTR = 3'b000; 
+    parameter DQS_MODE = "X1"; 
+    parameter HWL = "false";     
+    parameter GSREN = "false"; 
 endmodule
 
 module DLLDLY (...);
@@ -1095,6 +1100,13 @@ parameter DLY_SIGN = 1'b0;
 parameter DLY_ADJ = 0; 
 endmodule
 
+module DCS (...);
+input CLK0, CLK1, CLK2, CLK3, SELFORCE;
+input [3:0] CLKSEL;
+output CLKOUT;
+  parameter DCS_MODE = "RISING";  
+endmodule
+
 module DQCE (...);
 input CLKIN;
 input CE;

yowasp_yosys/share/gowin/cells_xtra_gw5a.v

@@ -1143,6 +1143,13 @@ input CE;
 output CLKOUT;
 endmodule
 
+module DCS (...);
+input CLKIN0, CLKIN1, CLKIN2, CLKIN3, SELFORCE;
+input [3:0] CLKSEL;
+output CLKOUT;
+parameter DCS_MODE = "RISING";  
+endmodule
+
 module DDRDLL (...);
 input CLKIN;
 input STOP;
@@ -1714,18 +1721,94 @@ input LOAD;
 endmodule
 
 module ADCLRC (...);
+  parameter DYN_BKEN = "FALSE";
+  parameter BUF_SERDES_Q1_EN = 3'b000;    
+  parameter BUF_BK2_EN       = 6'b000000; 
+  parameter BUF_BK3_EN       = 6'b000000; 
+  parameter BUF_BK4_EN       = 6'b000000; 
+  parameter BUF_BK5_EN       = 6'b000000; 
+  parameter BUF_BK10_EN      = 5'b00000;  
+  parameter BUF_BK11_EN      = 5'b00000;  
+  parameter CLK_SEL          = 1'b0;      
+  parameter PIOCLK_SEL       = 1'b0;      
+  parameter VSEN_CTL         = 3'b000;    
+  parameter VSEN_CTL_SEL     = 1'b0;      
+  parameter ADC_MODE      = 1'b0;      
+  parameter DIV_CTL       = 2'd0;      
+  parameter SAMPLE_CNT_SEL   = 3'd4;      
+  parameter RATE_CHANGE_CTRL = 3'd4;      
 endmodule
 
 module ADCULC (...);
+  parameter DYN_BKEN = "FALSE";
+  parameter BUF_VCC_EN       = 1'b0;      
+  parameter BUF_VCCM_EN      = 1'b0;      
+  parameter BUF_MIPI_M0_EN   = 3'b000;    
+  parameter BUF_MIPI_M1_EN   = 3'b000;    
+  parameter BUF_SERDES_Q0_EN = 3'b000;    
+  parameter BUF_BK6_EN       = 6'b000000; 
+  parameter BUF_BK7_EN       = 6'b000000; 
+  parameter CLK_SEL          = 1'b0;      
+  parameter PIOCLK_SEL       = 1'b0;      
+  parameter VSEN_CTL         = 3'b000;    
+  parameter VSEN_CTL_SEL     = 1'b0;      
+  parameter ADC_MODE      = 1'b0;      
+  parameter DIV_CTL          = 2'd0;      
+  parameter SAMPLE_CNT_SEL   = 3'd4;      
+  parameter RATE_CHANGE_CTRL = 3'd4;      
 endmodule
 
 module ADC (...);
+  parameter CLK_SEL         = 1'b0;      
+  parameter DIV_CTL         = 2'd0;      
+  parameter BUF_EN          = 12'b000000000000; 
+  parameter BUF_BK0_VREF_EN = 1'b0;  
+  parameter BUF_BK1_VREF_EN = 1'b0;  
+  parameter BUF_BK2_VREF_EN = 1'b0;  
+  parameter BUF_BK3_VREF_EN = 1'b0;  
+  parameter BUF_BK4_VREF_EN = 1'b0;  
+  parameter BUF_BK5_VREF_EN = 1'b0;  
+  parameter BUF_BK6_VREF_EN = 1'b0;  
+  parameter BUF_BK7_VREF_EN = 1'b0;  
+  parameter CSR_ADC_MODE      = 1'b1;       
+  parameter CSR_VSEN_CTRL        = 3'd0;       
+  parameter CSR_SAMPLE_CNT_SEL   = 3'd4;       
+  parameter CSR_RATE_CHANGE_CTRL = 3'd4;       
+  parameter CSR_FSCAL            = 10'd730;    
+  parameter CSR_OFFSET           = -12'd1180;  
 endmodule
 
 module ADC_SAR (...);
+  parameter BUF_EN = 29'b0;    
+  parameter CLK_SEL        = 1'b1;     
+  parameter DIV_CTL        = 2'd2;     
+  parameter ADC_EN_SEL     = 1'b0;     
+  parameter PHASE_SEL      = 1'b0;     
+  parameter CSR_ADC_MODE         = 1'b1;          
+  parameter CSR_VSEN_CTRL        = 3'd0;       
+  parameter CSR_SAMPLE_CNT_SEL   = 3'd4;       
+  parameter CSR_RATE_CHANGE_CTRL = 3'd4;       
+  parameter CSR_FSCAL            = 10'd730;    
+  parameter CSR_OFFSET           = -12'd1180;  
+  parameter ADC_CLK_DIV        = 2'b00;     
+  parameter ADC_CLKDIV_EN      = 1'b0;     
+  parameter CLK_SRC_SEL        = 1'b1;     
+  parameter VREF_BUF_EN        = 1'b1;     
+  parameter COUNT_LEN          = 5'b10100; 
+  parameter DAC_SAMPLE_END     = 5'b10010; 
+  parameter DAC_SAMPLE_START   = 5'b01101; 
+  parameter SH_SAMPLE_END      = 5'b01011; 
+  parameter SH_SAMPLE_START    = 5'b00001; 
+  parameter AUTO_CHOP_EN       = 1'b0;     
+  parameter CHOP_CLK_DIV       = 4'b0;     
 endmodule
 
 module LICD (...);
+    parameter   STAGE_NUM = 2'b00;        
+    parameter   ENCDEC_NUM = 2'b00;       
+    parameter   CODE_WIDTH = 2'b00;       
+    parameter   INTERLEAVE_EN = 3'b000;   
+    parameter   INTERLEAVE_MODE = 3'b000;  
 endmodule
 
 module MIPI_DPHY (...);
@@ -2456,6 +2539,7 @@ parameter EQ_ZLD_LN2 = 4'b1000;
 endmodule
 
 module GTR12_QUAD (...);
+    parameter POSITION = "Q0";
 endmodule
 
 module GTR12_UPAR (...);

yowasp_yosys/share/include/backends/rtlil/rtlil_backend.h

@@ -31,6 +31,7 @@
 YOSYS_NAMESPACE_BEGIN
 
 namespace RTLIL_BACKEND {
+	void dump_attributes(std::ostream &f, std::string indent, const RTLIL::AttrObject *obj);
 	void dump_const(std::ostream &f, const RTLIL::Const &data, int width = -1, int offset = 0, bool autoint = true);
 	void dump_sigchunk(std::ostream &f, const RTLIL::SigChunk &chunk, bool autoint = true);
 	void dump_sigspec(std::ostream &f, const RTLIL::SigSpec &sig, bool autoint = true);

yowasp_yosys/share/include/frontends/ast/ast.h

@@ -378,7 +378,12 @@ namespace AST
 		AstNode *get_struct_member() const;
 
 		// helper to print errors from simplify/genrtlil code
-		[[noreturn]] void input_error(const char *format, ...) const YS_ATTRIBUTE(format(printf, 2, 3));
+		[[noreturn]] void formatted_input_error(std::string str) const;
+		template <typename... Args>
+		[[noreturn]] void input_error(FmtString<TypeIdentity<Args>...> fmt, const Args &... args) const
+		{
+			formatted_input_error(fmt.format(args...));
+		}
 	};
 
 	// process an AST tree (ast must point to an AST_DESIGN node) and generate RTLIL code

yowasp_yosys/share/include/kernel/bitpattern.h

@@ -25,6 +25,18 @@
 
 YOSYS_NAMESPACE_BEGIN
 
+/**
+ * This file implements BitPatternPool for efficiently storing and querying
+ * sets of fixed-width 2-valued logic constants compressed as "bit patterns".
+ * A bit pattern can have don't cares on one or more bit positions (State::Sa).
+ *
+ * In terms of logic synthesis:
+ * A BitPatternPool is a sum of products (SOP).
+ * BitPatternPool::bits_t is a cube.
+ *
+ * BitPatternPool does not permit adding new patterns, only removing.
+ * Its intended use case is in analysing cases in case/match constructs in HDL.
+ */
 struct BitPatternPool
 {
 	int width;
@@ -67,6 +79,9 @@ struct BitPatternPool
 		}
 	}
 
+	/**
+	 * Constructs a pool of all possible patterns (all don't-care bits)
+	 */
 	BitPatternPool(int width)
 	{
 		this->width = width;
@@ -78,16 +93,23 @@ struct BitPatternPool
 		}
 	}
 
+	/**
+	 * Convert a constant SigSpec to a pattern. Normalize Yosys many-valued
+	 * to three-valued logic.
+	 */
 	bits_t sig2bits(RTLIL::SigSpec sig)
 	{
 		bits_t bits;
-		bits.bitdata = sig.as_const().bits();
+		bits.bitdata = sig.as_const().to_bits();
 		for (auto &b : bits.bitdata)
 			if (b > RTLIL::State::S1)
 				b = RTLIL::State::Sa;
 		return bits;
 	}
 
+	/**
+	 * Two cubes match if their intersection is non-empty.
+	 */
 	bool match(bits_t a, bits_t b)
 	{
 		log_assert(int(a.bitdata.size()) == width);
@@ -98,6 +120,15 @@ struct BitPatternPool
 		return true;
 	}
 
+	/**
+	 * Does cube sig overlap any cube in the pool?
+	 * For example:
+	 * pool({aaa}).has_any(01a) == true
+	 * pool({01a}).has_any(01a) == true
+	 * pool({011}).has_any(01a) == true
+	 * pool({01a}).has_any(011) == true
+	 * pool({111}).has_any(01a) == false
+	 */
 	bool has_any(RTLIL::SigSpec sig)
 	{
 		bits_t bits = sig2bits(sig);
@@ -107,6 +138,15 @@ struct BitPatternPool
 		return false;
 	}
 
+	/**
+	 * Is cube sig covered by a cube in the pool?
+	 * For example:
+	 * pool({aaa}).has_all(01a) == true
+	 * pool({01a}).has_any(01a) == true
+	 * pool({01a}).has_any(011) == true
+	 * pool({011}).has_all(01a) == false
+	 * pool({111}).has_all(01a) == false
+	 */
 	bool has_all(RTLIL::SigSpec sig)
 	{
 		bits_t bits = sig2bits(sig);
@@ -121,6 +161,12 @@ struct BitPatternPool
 		return false;
 	}
 
+	/**
+	 * Remove cube sig from the pool, splitting the remaining cubes. True if success.
+	 * For example:
+	 * Taking 011 out of pool({01a}) -> pool({010}), returns true.
+	 * Taking 011 out of pool({010}) does nothing, returns false.
+	 */
 	bool take(RTLIL::SigSpec sig)
 	{
 		bool status = false;
@@ -143,6 +189,9 @@ struct BitPatternPool
 		return status;
 	}
 
+	/**
+	 * Remove all patterns. Returns false if already empty.
+	 */
 	bool take_all()
 	{
 		if (database.empty())

yowasp_yosys/share/include/kernel/celltypes.h

@@ -111,6 +111,8 @@ struct CellTypes
 		setup_type(ID($original_tag), {ID::A}, {ID::Y});
 		setup_type(ID($future_ff), {ID::A}, {ID::Y});
 		setup_type(ID($scopeinfo), {}, {});
+		setup_type(ID($input_port), {}, {ID::Y});
+		setup_type(ID($connect), {ID::A, ID::B}, {});
 	}
 
 	void setup_internals_eval()
@@ -303,24 +305,34 @@ struct CellTypes
 		cell_types.clear();
 	}
 
-	bool cell_known(RTLIL::IdString type) const
+	bool cell_known(const RTLIL::IdString &type) const
 	{
 		return cell_types.count(type) != 0;
 	}
 
-	bool cell_output(RTLIL::IdString type, RTLIL::IdString port) const
+	bool cell_output(const RTLIL::IdString &type, const RTLIL::IdString &port) const
 	{
 		auto it = cell_types.find(type);
 		return it != cell_types.end() && it->second.outputs.count(port) != 0;
 	}
 
-	bool cell_input(RTLIL::IdString type, RTLIL::IdString port) const
+	bool cell_input(const RTLIL::IdString &type, const RTLIL::IdString &port) const
 	{
 		auto it = cell_types.find(type);
 		return it != cell_types.end() && it->second.inputs.count(port) != 0;
 	}
 
-	bool cell_evaluable(RTLIL::IdString type) const
+	RTLIL::PortDir cell_port_dir(RTLIL::IdString type, RTLIL::IdString port) const
+	{
+		auto it = cell_types.find(type);
+		if (it == cell_types.end())
+			return RTLIL::PD_UNKNOWN;
+		bool is_input = it->second.inputs.count(port);
+		bool is_output = it->second.outputs.count(port);
+		return RTLIL::PortDir(is_input + is_output * 2);
+	}
+
+	bool cell_evaluable(const RTLIL::IdString &type) const
 	{
 		auto it = cell_types.find(type);
 		return it != cell_types.end() && it->second.is_evaluable;
@@ -328,7 +340,7 @@ struct CellTypes
 
 	static RTLIL::Const eval_not(RTLIL::Const v)
 	{
-		for (auto &bit : v.bits())
+		for (auto bit : v)
 			if (bit == State::S0) bit = State::S1;
 			else if (bit == State::S1) bit = State::S0;
 		return v;
@@ -421,16 +433,14 @@ struct CellTypes
 	static RTLIL::Const eval(RTLIL::Cell *cell, const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool *errp = nullptr)
 	{
 		if (cell->type == ID($slice)) {
-			RTLIL::Const ret;
 			int width = cell->parameters.at(ID::Y_WIDTH).as_int();
 			int offset = cell->parameters.at(ID::OFFSET).as_int();
-			ret.bits().insert(ret.bits().end(), arg1.begin()+offset, arg1.begin()+offset+width);
-			return ret;
+			return arg1.extract(offset, width);
 		}
 
 		if (cell->type == ID($concat)) {
 			RTLIL::Const ret = arg1;
-			ret.bits().insert(ret.bits().end(), arg2.begin(), arg2.end());
+			ret.append(arg2);
 			return ret;
 		}
 

yowasp_yosys/share/include/kernel/consteval.h

@@ -115,7 +115,7 @@ struct ConstEval
 
 				for (int i = 0; i < GetSize(coval); i++) {
 					carry = (sig_g[i] == State::S1) || (sig_p[i] == RTLIL::S1 && carry);
-					coval.bits()[i] = carry ? State::S1 : State::S0;
+					coval.set(i, carry ? State::S1 : State::S0);
 				}
 
 				set(sig_co, coval);
@@ -249,7 +249,7 @@ struct ConstEval
 
 			for (int i = 0; i < GetSize(val_y); i++)
 				if (val_y[i] == RTLIL::Sx)
-					val_x.bits()[i] = RTLIL::Sx;
+					val_x.set(i, RTLIL::Sx);
 
 			set(sig_y, val_y);
 			set(sig_x, val_x);