siliconcompiler 0.36.0__py3-none-any.whl → 0.36.2__py3-none-any.whl

siliconcompiler/tools/vpr/route.py

@@ -1,4 +1,5 @@
 import shutil
+from typing import Optional
 
 from siliconcompiler.tools.vpr import VPRTask
 
@@ -19,6 +20,45 @@ class RouteTask(VPRTask):
                            "set the timing corner for files generated by the post-implementation "
                            "netlist", defvalue="typical")
 
+    def set_vpr_maxrouteriterations(self, iterations: int,
+                                    step: Optional[str] = None,
+                                    index: Optional[str] = None):
+        """
+        Sets the maximum number of routing iterations.
+
+        Args:
+            iterations (int): The maximum number of iterations.
+            step (str, optional): The specific step to apply this configuration to.
+            index (str, optional): The specific index to apply this configuration to.
+        """
+        self.set("var", "max_router_iterations", iterations, step=step, index=index)
+
+    def set_vpr_genpostimplementationnetlist(self, enable: bool,
+                                             step: Optional[str] = None,
+                                             index: Optional[str] = None):
+        """
+        Enables or disables generating a post-implementation netlist.
+
+        Args:
+            enable (bool): Whether to generate the netlist.
+            step (str, optional): The specific step to apply this configuration to.
+            index (str, optional): The specific index to apply this configuration to.
+        """
+        self.set("var", "gen_post_implementation_netlist", enable, step=step, index=index)
+
+    def set_vpr_timingcorner(self, corner: str,
+                             step: Optional[str] = None,
+                             index: Optional[str] = None):
+        """
+        Sets the timing corner for files generated by the post-implementation netlist.
+
+        Args:
+            corner (str): The timing corner.
+            step (str, optional): The specific step to apply this configuration to.
+            index (str, optional): The specific index to apply this configuration to.
+        """
+        self.set("var", "timing_corner", corner, step=step, index=index)
+
     def task(self):
         return "route"
 

siliconcompiler/tools/xdm/convert.py

@@ -2,6 +2,7 @@ import shutil
 
 import os.path
 
+from typing import Optional
 from siliconcompiler import Task
 
 
@@ -14,6 +15,19 @@ class ConvertTask(Task):
                            "the naming scheme for siliconcompiler",
                            defvalue=True)
 
+    def set_xdm_rename(self, enable: bool,
+                       step: Optional[str] = None,
+                       index: Optional[str] = None):
+        """
+        Enables or disables renaming the output file.
+
+        Args:
+            enable (bool): Whether to rename the output file.
+            step (str, optional): The specific step to apply this configuration to.
+            index (str, optional): The specific index to apply this configuration to.
+        """
+        self.set("var", "rename", enable, step=step, index=index)
+
     def tool(self):
         return "xdm"
 

siliconcompiler/tools/xyce/simulate.py

@@ -1,5 +1,7 @@
 import os.path
 
+from typing import Union, Optional
+
 from siliconcompiler import Task
 
 
@@ -11,6 +13,30 @@ class SimulateTask(Task):
         self.add_parameter("trace_format", "<ASCII,binary>", "Format to use for traces.",
                            defvalue="ASCII")
 
+    def set_xyce_trace(self, enable: bool,
+                       step: Optional[str] = None, index: Optional[Union[int, str]] = None):
+        """
+        Enables or disables dumping all signals.
+
+        Args:
+            enable (bool): True to enable, False to disable.
+            step (str, optional): The specific step to apply this configuration to.
+            index (str, optional): The specific index to apply this configuration to.
+        """
+        self.set('var', 'trace', enable, step=step, index=index)
+
+    def set_xyce_traceformat(self, trace_format: str,
+                             step: Optional[str] = None, index: Optional[Union[int, str]] = None):
+        """
+        Sets the format to use for traces.
+
+        Args:
+            trace_format (str): The format to use for traces.
+            step (str, optional): The specific step to apply this configuration to.
+            index (str, optional): The specific index to apply this configuration to.
+        """
+        self.set('var', 'trace_format', trace_format, step=step, index=index)
+
     def tool(self):
         return "xyce"
 

siliconcompiler/tools/yosys/lec_asic.py

@@ -1,4 +1,5 @@
 import re
+from typing import Optional
 
 from siliconcompiler import sc_open
 
@@ -15,6 +16,18 @@ class ASICLECTask(_ASICTask):
         self.add_parameter("induction_steps", "int",
                            "Number of induction steps for yosys equivalence checking", defvalue=10)
 
+    def set_yosys_inductionsteps(self, steps: int,
+                                 step: Optional[str] = None, index: Optional[str] = None):
+        """
+        Sets the number of induction steps for yosys equivalence checking.
+
+        Args:
+            steps (int): The number of steps.
+            step (str, optional): The specific step to apply this configuration to.
+            index (str, optional): The specific index to apply this configuration to.
+        """
+        self.set("var", "induction_steps", steps, step=step, index=index)
+
     def task(self):
         return "lec_asic"
 

siliconcompiler/tools/yosys/syn_asic.py

@@ -2,7 +2,7 @@ import json
 
 import os.path
 
-from typing import Optional
+from typing import Optional, Union, List
 
 from siliconcompiler.tools.yosys.prepareLib import process_liberty_file
 from siliconcompiler import sc_open
@@ -39,7 +39,7 @@ class _ASICTask(ASICTask, YosysTask):
 
         delaymodel = self.project.get("asic", "delaymodel")
         for lib in self.project.get("asic", "asiclib"):
-            lib_obj = self.project.get("library", lib, field="schema")
+            lib_obj = self.project.get_library(lib)
             for corner in self.get("var", "synthesis_corner"):
                 if lib_obj.get("asic", "libcornerfileset", corner, delaymodel):
                     self.add_required_key(lib_obj, "asic", "libcornerfileset", corner, delaymodel)
@@ -56,14 +56,14 @@ class _ASICTask(ASICTask, YosysTask):
             if not scenario.get_libcorner():
                 continue
             if "setup" in scenario.get_check():
-                self.add_synthesis_corner(scenario.get_libcorner())
+                self.add_yosys_synthesiscorner(scenario.get_libcorner())
                 return
 
         if scenarios:
             # try getting it from first constraint with a valid libcorner
             for scenario in scenarios.get_scenario().values():
                 if scenario.get_libcorner():
-                    self.add_synthesis_corner(scenario.get_libcorner())
+                    self.add_yosys_synthesiscorner(scenario.get_libcorner())
                     return
 
     def pre_process(self):
@@ -81,7 +81,7 @@ class _ASICTask(ASICTask, YosysTask):
         # Generate synthesis_libraries for Yosys use
         fileset_map = []
         for lib in self.project.get("asic", "asiclib"):
-            lib_obj = self.project.get("library", lib, field="schema")
+            lib_obj = self.project.get_library(lib)
             for corner in self.get("var", "synthesis_corner"):
                 for fileset in lib_obj.get("asic", "libcornerfileset", corner, delaymodel):
                     fileset_map.append((lib_obj, fileset))
@@ -132,6 +132,28 @@ class _ASICTask(ASICTask, YosysTask):
                 self.add("var", 'synthesis_libraries', output_file)
 
     def add_synthesis_corner(self, corner, step=None, index=None, clobber=True):
+        """Deprecated"""
+        import warnings
+        warnings.warn(
+            "add_synthesis_corner is deprecated. "
+            "Please use add_yosys_synthesiscorner instead.",
+            DeprecationWarning,
+            stacklevel=2
+        )
+        self.add_yosys_synthesiscorner(corner, step=step, index=index, clobber=clobber)
+
+    def add_yosys_synthesiscorner(self, corner: str,
+                                  step: Optional[str] = None, index: Optional[str] = None,
+                                  clobber: bool = False):
+        """
+        Adds a timing corner to use for synthesis.
+
+        Args:
+            corner (str): The name of the corner.
+            step (str, optional): The specific step to apply this configuration to.
+            index (str, optional): The specific index to apply this configuration to.
+            clobber (bool, optional): If True, overwrites the existing list. Defaults to False.
+        """
         if clobber:
             self.set("var", "synthesis_corner", corner, step=step, index=index)
         else:
@@ -316,24 +338,331 @@ class ASICSynthesis(_ASICTask, YosysTask):
 
     def set_yosys_useslang(self, enable: bool,
                            step: Optional[str] = None, index: Optional[str] = None):
+        """
+        Enables or disables using the slang frontend.
+
+        Args:
+            enable (bool): True to enable, False to disable.
+            step (str, optional): The specific step to apply this configuration to.
+            index (str, optional): The specific index to apply this configuration to.
+        """
         self.set("var", "use_slang", enable, step=step, index=index)
 
+    def set_yosys_autoname(self, enable: bool,
+                           step: Optional[str] = None, index: Optional[str] = None):
+        """
+        Enables or disables renaming wires based on registers.
+
+        Args:
+            enable (bool): True to enable, False to disable.
+            step (str, optional): The specific step to apply this configuration to.
+            index (str, optional): The specific index to apply this configuration to.
+        """
+        self.set("var", "autoname", enable, step=step, index=index)
+
     def set_yosys_tieundefined(self, tie: str,
                                step: Optional[str] = None, index: Optional[str] = None):
+        """
+        Sets how to handle undefined signals in the netlist.
+
+        Args:
+            tie (str): The tie strategy ('high', 'low', 'none').
+            step (str, optional): The specific step to apply this configuration to.
+            index (str, optional): The specific index to apply this configuration to.
+        """
         self.set("var", "tie_undef", tie, step=step, index=index)
 
     def set_yosys_addtiecells(self, enable: bool,
                               step: Optional[str] = None, index: Optional[str] = None):
+        """
+        Enables or disables adding tie high and tie low cells.
+
+        Args:
+            enable (bool): True to enable, False to disable.
+            step (str, optional): The specific step to apply this configuration to.
+            index (str, optional): The specific index to apply this configuration to.
+        """
         self.set("var", "add_tieoffs", enable, step=step, index=index)
 
     def set_yosys_addbuffers(self, enable: bool,
                              step: Optional[str] = None, index: Optional[str] = None):
+        """
+        Enables or disables adding buffers.
+
+        Args:
+            enable (bool): True to enable, False to disable.
+            step (str, optional): The specific step to apply this configuration to.
+            index (str, optional): The specific index to apply this configuration to.
+        """
         self.set("var", "add_buffers", enable, step=step, index=index)
 
     def set_yosys_optundriven(self, enable: bool,
                               step: Optional[str] = None, index: Optional[str] = None):
+        """
+        Enables or disables marking undriven nets during optimization.
+
+        Args:
+            enable (bool): True to enable, False to disable.
+            step (str, optional): The specific step to apply this configuration to.
+            index (str, optional): The specific index to apply this configuration to.
+        """
         self.set("var", "opt_undriven", enable, step=step, index=index)
 
+    def set_yosys_mapadders(self, enable: bool,
+                            step: Optional[str] = None, index: Optional[str] = None):
+        """
+        Enables or disables techmapping adders in Yosys.
+
+        Args:
+            enable (bool): True to enable, False to disable.
+            step (str, optional): The specific step to apply this configuration to.
+            index (str, optional): The specific index to apply this configuration to.
+        """
+        self.set("var", "map_adders", enable, step=step, index=index)
+
+    def set_yosys_memorylibmap(self, file: str,
+                               step: Optional[str] = None, index: Optional[str] = None):
+        """
+        Sets the file used to map memories with Yosys.
+
+        Args:
+            file (str): The path to the library map file.
+            step (str, optional): The specific step to apply this configuration to.
+            index (str, optional): The specific index to apply this configuration to.
+        """
+        self.set("var", "memory_libmap", file, step=step, index=index)
+
+    def set_yosys_memorytechmap(self, file: str,
+                                step: Optional[str] = None, index: Optional[str] = None):
+        """
+        Sets the file used to techmap memories with Yosys.
+
+        Args:
+            file (str): The path to the technology map file.
+            step (str, optional): The specific step to apply this configuration to.
+            index (str, optional): The specific index to apply this configuration to.
+        """
+        self.set("var", "memory_techmap", file, step=step, index=index)
+
+    def add_yosys_synthextramap(self, map: Union[str, List[str]],
+                                step: Optional[str] = None, index: Optional[str] = None,
+                                clobber: bool = False):
+        """
+        Adds files used in synthesis to perform additional techmapping.
+
+        Args:
+            map (Union[str, List[str]]): The map file(s) to add.
+            step (str, optional): The specific step to apply this configuration to.
+            index (str, optional): The specific index to apply this configuration to.
+            clobber (bool, optional): If True, overwrites the existing list. Defaults to False.
+        """
+        if clobber:
+            self.set("var", "synth_extra_map", map, step=step, index=index)
+        else:
+            self.add("var", "synth_extra_map", map, step=step, index=index)
+
+    def add_yosys_preservemodules(self, modules: Union[str, List[str]],
+                                  step: Optional[str] = None, index: Optional[str] = None,
+                                  clobber: bool = False):
+        """
+        Adds modules to prevent flattening.
+
+        Args:
+            modules (Union[str, List[str]]): The module name(s) to preserve.
+            step (str, optional): The specific step to apply this configuration to.
+            index (str, optional): The specific index to apply this configuration to.
+            clobber (bool, optional): If True, overwrites the existing list. Defaults to False.
+        """
+        if clobber:
+            self.set("var", "preserve_modules", modules, step=step, index=index)
+        else:
+            self.add("var", "preserve_modules", modules, step=step, index=index)
+
+    def add_yosys_blackboxmodules(self, modules: Union[str, List[str]],
+                                  step: Optional[str] = None, index: Optional[str] = None,
+                                  clobber: bool = False):
+        """
+        Adds modules to exclude from synthesis by replacing them with empty blackboxes.
+
+        Args:
+            modules (Union[str, List[str]]): The module name(s) to blackbox.
+            step (str, optional): The specific step to apply this configuration to.
+            index (str, optional): The specific index to apply this configuration to.
+            clobber (bool, optional): If True, overwrites the existing list. Defaults to False.
+        """
+        if clobber:
+            self.set("var", "blackbox_modules", modules, step=step, index=index)
+        else:
+            self.add("var", "blackbox_modules", modules, step=step, index=index)
+
+    def set_yosys_flatten(self, enable: bool,
+                          step: Optional[str] = None, index: Optional[str] = None):
+        """
+        Enables or disables invoking synth with the -flatten option.
+
+        Args:
+            enable (bool): True to enable, False to disable.
+            step (str, optional): The specific step to apply this configuration to.
+            index (str, optional): The specific index to apply this configuration to.
+        """
+        self.set("var", "flatten", enable, step=step, index=index)
+
+    def set_yosys_autoflatten(self, enable: bool,
+                              step: Optional[str] = None, index: Optional[str] = None):
+        """
+        Enables or disables attempting to determine how to flatten the design.
+
+        Args:
+            enable (bool): True to enable, False to disable.
+            step (str, optional): The specific step to apply this configuration to.
+            index (str, optional): The specific index to apply this configuration to.
+        """
+        self.set("var", "auto_flatten", enable, step=step, index=index)
+
+    def set_yosys_hierthreshold(self, threshold: int,
+                                step: Optional[str] = None, index: Optional[str] = None):
+        """
+        Sets the instance limit for the number of cells in a module to preserve.
+
+        Args:
+            threshold (int): The instance limit.
+            step (str, optional): The specific step to apply this configuration to.
+            index (str, optional): The specific index to apply this configuration to.
+        """
+        self.set("var", "hier_threshold", threshold, step=step, index=index)
+
+    def set_yosys_hierarchyseparator(self, separator: str,
+                                     step: Optional[str] = None, index: Optional[str] = None):
+        """
+        Sets the hierarchy separator used during design flattening.
+
+        Args:
+            separator (str): The separator character.
+            step (str, optional): The specific step to apply this configuration to.
+            index (str, optional): The specific index to apply this configuration to.
+        """
+        self.set("var", "hierarchy_separator", separator, step=step, index=index)
+
+    def set_yosys_strategy(self, strategy: str,
+                           step: Optional[str] = None, index: Optional[str] = None):
+        """
+        Sets the ABC synthesis strategy.
+
+        Args:
+            strategy (str): The strategy name (e.g., 'DELAY1', 'AREA2').
+            step (str, optional): The specific step to apply this configuration to.
+            index (str, optional): The specific index to apply this configuration to.
+        """
+        self.set("var", "strategy", strategy, step=step, index=index)
+
+    def set_yosys_abcconstraintdriver(self, driver: str,
+                                      step: Optional[str] = None, index: Optional[str] = None):
+        """
+        Sets the buffer that drives the ABC techmapping.
+
+        Args:
+            driver (str): The driver cell name.
+            step (str, optional): The specific step to apply this configuration to.
+            index (str, optional): The specific index to apply this configuration to.
+        """
+        self.set("var", "abc_constraint_driver", driver, step=step, index=index)
+
+    def set_yosys_abcclockperiod(self, period: float,
+                                 step: Optional[str] = None, index: Optional[str] = None):
+        """
+        Sets the clock period to use for synthesis.
+
+        Args:
+            period (float): The clock period in ps.
+            step (str, optional): The specific step to apply this configuration to.
+            index (str, optional): The specific index to apply this configuration to.
+        """
+        self.set("var", "abc_clock_period", period, step=step, index=index)
+
+    def set_yosys_abcconstraintload(self, load: float,
+                                    step: Optional[str] = None, index: Optional[str] = None):
+        """
+        Sets the capacitive load for the ABC techmapping.
+
+        Args:
+            load (float): The load in fF.
+            step (str, optional): The specific step to apply this configuration to.
+            index (str, optional): The specific index to apply this configuration to.
+        """
+        self.set("var", "abc_constraint_load", load, step=step, index=index)
+
+    def set_yosys_abcclockderating(self, derating: float,
+                                   step: Optional[str] = None, index: Optional[str] = None):
+        """
+        Sets the derating to apply to the clock period for ABC synthesis.
+
+        Args:
+            derating (float): The derating factor.
+            step (str, optional): The specific step to apply this configuration to.
+            index (str, optional): The specific index to apply this configuration to.
+        """
+        self.set("var", "abc_clock_derating", derating, step=step, index=index)
+
+    def set_yosys_mapclockgates(self, enable: bool,
+                                step: Optional[str] = None, index: Optional[str] = None):
+        """
+        Enables or disables mapping clockgates during synthesis.
+
+        Args:
+            enable (bool): True to enable, False to disable.
+            step (str, optional): The specific step to apply this configuration to.
+            index (str, optional): The specific index to apply this configuration to.
+        """
+        self.set("var", "map_clockgates", enable, step=step, index=index)
+
+    def set_yosys_minclockgatefanout(self, fanout: int,
+                                     step: Optional[str] = None, index: Optional[str] = None):
+        """
+        Sets the minimum clockgate fanout.
+
+        Args:
+            fanout (int): The minimum fanout.
+            step (str, optional): The specific step to apply this configuration to.
+            index (str, optional): The specific index to apply this configuration to.
+        """
+        self.set("var", "min_clockgate_fanout", fanout, step=step, index=index)
+
+    def set_yosys_lockdesign(self, enable: bool,
+                             step: Optional[str] = None, index: Optional[str] = None):
+        """
+        Enables or disables attempting to lock the design with moosic.
+
+        Args:
+            enable (bool): True to enable, False to disable.
+            step (str, optional): The specific step to apply this configuration to.
+            index (str, optional): The specific index to apply this configuration to.
+        """
+        self.set("var", "lock_design", enable, step=step, index=index)
+
+    def set_yosys_lockdesignkey(self, key: str,
+                                step: Optional[str] = None, index: Optional[str] = None):
+        """
+        Sets the lock locking key.
+
+        Args:
+            key (str): The key.
+            step (str, optional): The specific step to apply this configuration to.
+            index (str, optional): The specific index to apply this configuration to.
+        """
+        self.set("var", "lock_design_key", key, step=step, index=index)
+
+    def set_yosys_lockdesignport(self, port: str,
+                                 step: Optional[str] = None, index: Optional[str] = None):
+        """
+        Sets the lock locking port name.
+
+        Args:
+            port (str): The port name.
+            step (str, optional): The specific step to apply this configuration to.
+            index (str, optional): The specific index to apply this configuration to.
+        """
+        self.set("var", "lock_design_port", port, step=step, index=index)
+
     def task(self):
         return "syn_asic"
 
@@ -367,7 +696,7 @@ class ASICSynthesis(_ASICTask, YosysTask):
         self.add_output_file(ext="vg", clobber=True)
         self.add_output_file(ext="netlist.json")
 
-        mainlib = self.project.get("library", self.project.get("asic", "mainlib"), field="schema")
+        mainlib = self.project.get_library(self.project.get("asic", "mainlib"))
 
         if self.get('var', 'abc_constraint_driver') is not None:
             self.add_required_key("var", "abc_constraint_driver")
@@ -470,7 +799,7 @@ class ASICSynthesis(_ASICTask, YosysTask):
 
     def _get_clock_period(self):
         mainlib = self.project.get("asic", "mainlib")
-        clock_units_multiplier = self.project.get("library", mainlib, field="schema").get(
+        clock_units_multiplier = self.project.get_library(mainlib).get(
             "tool", "yosys", "abc_clock_multiplier") / 1000
 
         _, period = self.get_clock()

siliconcompiler/tools/yosys/syn_fpga.py

@@ -30,8 +30,40 @@ class FPGASynthesis(YosysTask):
 
     def set_yosys_useslang(self, enable: bool,
                            step: Optional[str] = None, index: Optional[str] = None):
+        """
+        Enables or disables using the slang frontend.
+
+        Args:
+            enable (bool): True to enable, False to disable.
+            step (str, optional): The specific step to apply this configuration to.
+            index (str, optional): The specific index to apply this configuration to.
+        """
         self.set("var", "use_slang", enable, step=step, index=index)
 
+    def set_yosys_synthoptmode(self, mode: str,
+                               step: Optional[str] = None, index: Optional[str] = None):
+        """
+        Sets the optimization mode for synthesis.
+
+        Args:
+            mode (str): The optimization mode ('none', 'delay', 'area').
+            step (str, optional): The specific step to apply this configuration to.
+            index (str, optional): The specific index to apply this configuration to.
+        """
+        self.set("var", "synth_opt_mode", mode, step=step, index=index)
+
+    def set_yosys_synthinsertbuffers(self, enable: bool,
+                                     step: Optional[str] = None, index: Optional[str] = None):
+        """
+        Enables or disables buffer insertion during synthesis.
+
+        Args:
+            enable (bool): True to enable, False to disable.
+            step (str, optional): The specific step to apply this configuration to.
+            index (str, optional): The specific index to apply this configuration to.
+        """
+        self.set("var", "synth_insert_buffers", enable, step=step, index=index)
+
     def task(self):
         return "syn_fpga"
 
@@ -66,7 +98,7 @@ class FPGASynthesis(YosysTask):
 
         self._synthesis_post_process()
 
-        fpga = self.project.get("fpga", "device")
+        fpga = self.project.get_library(self.project.get("fpga", "device"))
 
         with sc_open("reports/stat.json") as f:
             metrics = json.load(f)
@@ -81,15 +113,14 @@ class FPGASynthesis(YosysTask):
                 return
 
             dff_cells = []
-            if self.project.valid("library", fpga, "tool", "yosys", "registers"):
-                dff_cells = self.project.get("library", fpga, "tool", "yosys", "registers")
+            if fpga.valid("tool", "yosys", "registers"):
+                dff_cells = fpga.get("tool", "yosys", "registers")
             brams_cells = []
-            if self.project.valid("library", fpga, "tool", "yosys", "brams"):
-                brams_cells = self.project.get("library", fpga, "tool", "yosys", "brams")
+            if fpga.valid("tool", "yosys", "brams"):
+                brams_cells = fpga.get("tool", "yosys", "brams")
             dsps_cells = []
-            if self.project.valid("library", fpga, "tool", "yosys", "dsps"):
-                dsps_cells = self.project.get("library", fpga, "tool", "yosys", "dsps")
-
+            if fpga.valid("tool", "yosys", "dsps"):
+                dsps_cells = fpga.get("tool", "yosys", "dsps")
             data = {
                 "registers": 0,
                 "luts": 0,