siliconcompiler 0.36.0__py3-none-any.whl → 0.36.2__py3-none-any.whl

siliconcompiler/tools/openroad/repair_timing.py

@@ -1,3 +1,5 @@
+from typing import Optional, Union
+
 from siliconcompiler.tools.openroad._apr import APRTask
 from siliconcompiler.tools.openroad._apr import OpenROADSTAParameter, OpenROADDPLParameter, \
     OpenROADRSZDRVParameter, OpenROADRSZTimingParameter, OpenROADFillCellsParameter
@@ -21,6 +23,58 @@ class RepairTimingTask(APRTask, OpenROADSTAParameter, OpenROADDPLParameter,
         self.add_parameter("rsz_skip_recover_power", "bool", "skip power recovery",
                            defvalue=False)
 
+    def set_openroad_skipdrvrepair(self, skip: bool,
+                                   step: Optional[str] = None,
+                                   index: Optional[Union[int, str]] = None):
+        """
+        Enables or disables skipping design rule violation repair.
+
+        Args:
+            skip (bool): True to skip repair, False to perform it.
+            step (str, optional): The specific step to apply this configuration to.
+            index (str, optional): The specific index to apply this configuration to.
+        """
+        self.set("var", "rsz_skip_drv_repair", skip, step=step, index=index)
+
+    def set_openroad_skipsetuprepair(self, skip: bool,
+                                     step: Optional[str] = None,
+                                     index: Optional[Union[int, str]] = None):
+        """
+        Enables or disables skipping setup timing repair.
+
+        Args:
+            skip (bool): True to skip repair, False to perform it.
+            step (str, optional): The specific step to apply this configuration to.
+            index (str, optional): The specific index to apply this configuration to.
+        """
+        self.set("var", "rsz_skip_setup_repair", skip, step=step, index=index)
+
+    def set_openroad_skipholdrepair(self, skip: bool,
+                                    step: Optional[str] = None,
+                                    index: Optional[Union[int, str]] = None):
+        """
+        Enables or disables skipping hold timing repair.
+
+        Args:
+            skip (bool): True to skip repair, False to perform it.
+            step (str, optional): The specific step to apply this configuration to.
+            index (str, optional): The specific index to apply this configuration to.
+        """
+        self.set("var", "rsz_skip_hold_repair", skip, step=step, index=index)
+
+    def set_openroad_skiprecoverpower(self, skip: bool,
+                                      step: Optional[str] = None,
+                                      index: Optional[Union[int, str]] = None):
+        """
+        Enables or disables skipping power recovery.
+
+        Args:
+            skip (bool): True to skip recovery, False to perform it.
+            step (str, optional): The specific step to apply this configuration to.
+            index (str, optional): The specific index to apply this configuration to.
+        """
+        self.set("var", "rsz_skip_recover_power", skip, step=step, index=index)
+
     def task(self):
         return "repair_timing"
 

siliconcompiler/tools/openroad/screenshot.py

@@ -1,3 +1,5 @@
+from typing import Optional, Union
+
 from siliconcompiler import ScreenshotTask
 from siliconcompiler.tools.openroad.show import ShowTask
 
@@ -9,10 +11,38 @@ class ScreenshotTask(ScreenshotTask, ShowTask):
     def __init__(self):
         super().__init__()
 
-        self.add_parameter("show_vertical_resolution", "int", "blah", defvalue=1024)
+        self.add_parameter("show_vertical_resolution", "int",
+                           "Vertical resolution of the screenshot image",
+                           defvalue=1024)
         self.add_parameter("include_report_images", "bool",
                            "true/false, include the images in reports/", defvalue=False)
 
+    def set_openroad_verticalresolution(self, value: int,
+                                        step: Optional[str] = None,
+                                        index: Optional[Union[int, str]] = None):
+        """
+        Set the vertical resolution for OpenROAD screenshots.
+
+        Args:
+            value (int): The vertical resolution in pixels.
+            step (Optional[str]): The step in the flow where this setting applies.
+            index (Optional[Union[int, str]]): The index for multiple runs or configurations.
+        """
+        self.set("var", "show_vertical_resolution", value, step=step, index=index)
+
+    def set_openroad_includereportimages(self, value: bool,
+                                         step: Optional[str] = None,
+                                         index: Optional[Union[int, str]] = None):
+        """
+        Set whether to include report images in the output.
+
+        Args:
+            value (bool): Whether to include report images.
+            step (Optional[str]): The step in the flow where this setting applies.
+            index (Optional[Union[int, str]]): The index for multiple runs or configurations.
+        """
+        self.set("var", "include_report_images", value, step=step, index=index)
+
     def setup(self):
         super().setup()
 

siliconcompiler/tools/openroad/scripts/apr/preamble.tcl

@@ -92,3 +92,11 @@ tee -file reports/global_connections.start.rpt {report_global_connect}
 if { [sc_cfg_tool_task_check_in_list report_buffers var reports] && [sc_check_version 23264] } {
     tee -quiet -file reports/report_buffers.rpt {report_buffers -filtered}
 }
+tee -quiet -file reports/report_units.rpt {report_units}
+
+tee -quiet -file reports/report_layer_rc.rpt {report_layer_rc}
+foreach corner [sta::corners] {
+    set corner_name [$corner name]
+    tee -quiet -append -file reports/report_layer_rc.rpt "puts \"Corner: $corner_name\""
+    tee -quiet -append -file reports/report_layer_rc.rpt "report_layer_rc -corner $corner_name"
+}

siliconcompiler/tools/openroad/scripts/apr/sc_init_floorplan.tcl

@@ -149,7 +149,7 @@ set sc_hpinmetal [sc_get_layer_name [sc_cfg_tool_task_get var pin_layer_horizont
 set sc_vpinmetal [sc_get_layer_name [sc_cfg_tool_task_get var pin_layer_vertical]]
 
 if { [sc_cfg_exists constraint pin] } {
-    source "[sc_cfg_tool_task_get file sc_pin_constraint]"
+    source [sc_cfg_tool_task_get var sc_pin_constraints_tcl]
 
     proc sc_pin_print { arg } { utl::warn FLW 1 $arg }
     proc sc_pin_layer_select { pin } {
@@ -366,6 +366,10 @@ if { [sc_cfg_exists constraint component] } {
 
         if { $halo != {} } {
             set inst [[ord::get_db_block] findInst $name]
+            set halo_box [$inst getHalo]
+            if { $halo_box != "NULL" } {
+                odb::dbBox_destroy $halo_box
+            }
             odb::dbBox_create $inst \
                 [ord::microns_to_dbu [lindex $halo 0]] \
                 [ord::microns_to_dbu [lindex $halo 1]] \

siliconcompiler/tools/openroad/scripts/common/read_timing_constraints.tcl

@@ -2,22 +2,24 @@
 # Read timing constraints
 ###############################
 
-if { [file exists "inputs/${sc_topmodule}.sdc"] } {
-    set sdc "inputs/${sc_topmodule}.sdc"
-    puts "Reading SDC: ${sdc}"
-    read_sdc $sdc
-} else {
-    set sdcs [sc_cfg_get_fileset $sc_designlib [sc_cfg_get option fileset] sdc]
-    if { [llength $sdcs] > 0 } {
-        foreach sdc $sdcs {
+if { [sc_cfg_tool_task_get var load_sdcs] } {
+    if { [file exists "inputs/${sc_topmodule}.sdc"] } {
+        set sdc "inputs/${sc_topmodule}.sdc"
+        puts "Reading SDC: ${sdc}"
+        read_sdc $sdc
+    } else {
+        set sdcs [sc_cfg_get_fileset $sc_designlib [sc_cfg_get option fileset] sdc]
+        if { [llength $sdcs] > 0 } {
+            foreach sdc $sdcs {
+                puts "Reading SDC: ${sdc}"
+                read_sdc $sdc
+            }
+        } else {
+            # fall back on default auto generated constraints file
+            set sdc [sc_cfg_tool_task_get var opensta_generic_sdc]
             puts "Reading SDC: ${sdc}"
-            read_sdc $sdc
+            utl::warn FLW 1 "Defaulting back to default SDC"
+            read_sdc "${sdc}"
         }
-    } else {
-        # fall back on default auto generated constraints file
-        set sdc [sc_cfg_tool_task_get var opensta_generic_sdc]
-        puts "Reading SDC: ${sdc}"
-        utl::warn FLW 1 "Defaulting back to default SDC"
-        read_sdc "${sdc}"
     }
 }

siliconcompiler/tools/openroad/scripts/common/write_data_timing.tcl

@@ -1 +1,3 @@
-write_sdc "outputs/${sc_topmodule}.sdc"
+if { [sc_cfg_tool_task_get var load_sdcs] } {
+    write_sdc "outputs/${sc_topmodule}.sdc"
+}

siliconcompiler/tools/openroad/write_data.py

@@ -1,3 +1,5 @@
+from typing import Optional
+
 from siliconcompiler.tools.openroad._apr import APRTask
 from siliconcompiler.tools.openroad._apr import OpenROADSTAParameter, OpenROADPSMParameter
 
@@ -32,6 +34,80 @@ class WriteViewsTask(APRTask, OpenROADSTAParameter, OpenROADPSMParameter):
 
         self.add_parameter("pex_corners", "{str}", "set of pex corners to perform extraction on")
 
+    def set_openroad_abstractlefbloatlayers(self, enable: bool,
+                                            step: Optional[str] = None,
+                                            index: Optional[str] = None):
+        """
+        Enables or disables filling all layers when writing the abstract LEF.
+
+        Args:
+            enable (bool): True to enable, False to disable.
+            step (str, optional): The specific step to apply this configuration to.
+            index (str, optional): The specific index to apply this configuration to.
+        """
+        self.set("var", "ord_abstract_lef_bloat_layers", enable, step=step, index=index)
+
+    def set_openroad_abstractlefbloatfactor(self, factor: int,
+                                            step: Optional[str] = None,
+                                            index: Optional[str] = None):
+        """
+        Sets the bloat factor to apply when writing the abstract LEF.
+
+        Args:
+            factor (int): The bloat factor.
+            step (str, optional): The specific step to apply this configuration to.
+            index (str, optional): The specific index to apply this configuration to.
+        """
+        self.set("var", "ord_abstract_lef_bloat_factor", factor, step=step, index=index)
+
+    def set_openroad_writecdl(self, enable: bool,
+                              step: Optional[str] = None, index: Optional[str] = None):
+        """
+        Enables or disables writing the CDL file.
+
+        Args:
+            enable (bool): True to enable, False to disable.
+            step (str, optional): The specific step to apply this configuration to.
+            index (str, optional): The specific index to apply this configuration to.
+        """
+        self.set("var", "write_cdl", enable, step=step, index=index)
+
+    def set_openroad_writespef(self, enable: bool,
+                               step: Optional[str] = None, index: Optional[str] = None):
+        """
+        Enables or disables writing the SPEF file.
+
+        Args:
+            enable (bool): True to enable, False to disable.
+            step (str, optional): The specific step to apply this configuration to.
+            index (str, optional): The specific index to apply this configuration to.
+        """
+        self.set("var", "write_spef", enable, step=step, index=index)
+
+    def set_openroad_writeliberty(self, enable: bool,
+                                  step: Optional[str] = None, index: Optional[str] = None):
+        """
+        Enables or disables writing the Liberty timing model.
+
+        Args:
+            enable (bool): True to enable, False to disable.
+            step (str, optional): The specific step to apply this configuration to.
+            index (str, optional): The specific index to apply this configuration to.
+        """
+        self.set("var", "write_liberty", enable, step=step, index=index)
+
+    def set_openroad_writesdf(self, enable: bool,
+                              step: Optional[str] = None, index: Optional[str] = None):
+        """
+        Enables or disables writing the SDF timing model.
+
+        Args:
+            enable (bool): True to enable, False to disable.
+            step (str, optional): The specific step to apply this configuration to.
+            index (str, optional): The specific index to apply this configuration to.
+        """
+        self.set("var", "write_sdf", enable, step=step, index=index)
+
     def task(self):
         return "write_data"
 

siliconcompiler/tools/opensta/timing.py

@@ -29,8 +29,43 @@ class TimingTaskBase(OpenSTATask):
                            defvalue="tools/_common/sdc/sc_constraints.sdc",
                            dataroot="siliconcompiler")
 
-    def set_timing_mode(self, mode: str, step: Optional[str] = None, index: Optional[str] = None):
-        return self.set("var", "timing_mode", mode, step=step, index=index)
+    def set_opensta_topnpaths(self, n: int,
+                              step: Optional[str] = None,
+                              index: Optional[str] = None):
+        """
+        Sets the number of paths to report timing for.
+
+        Args:
+            n (int): The number of paths.
+            step (str, optional): The specific step to apply this configuration to.
+            index (str, optional): The specific index to apply this configuration to.
+        """
+        self.set("var", "top_n_paths", n, step=step, index=index)
+
+    def set_opensta_uniquepathgroupsperclock(self, enable: bool,
+                                             step: Optional[str] = None,
+                                             index: Optional[str] = None):
+        """
+        Enables or disables generating separate path groups per clock.
+
+        Args:
+            enable (bool): Whether to enable unique path groups per clock.
+            step (str, optional): The specific step to apply this configuration to.
+            index (str, optional): The specific index to apply this configuration to.
+        """
+        self.set("var", "unique_path_groups_per_clock", enable, step=step, index=index)
+
+    def set_opensta_timingmode(self, mode: str,
+                               step: Optional[str] = None, index: Optional[str] = None):
+        """
+        Sets the timing mode to use.
+
+        Args:
+            mode (str): The timing mode to use.
+            step (str, optional): The specific step to apply this configuration to.
+            index (str, optional): The specific index to apply this configuration to.
+        """
+        self.set("var", "timing_mode", mode, step=step, index=index)
 
     def setup(self):
         super().setup()

siliconcompiler/tools/slang/elaborate.py

@@ -1,6 +1,8 @@
+from typing import Optional, Union
+
 import os.path
-from siliconcompiler.tools.slang import pyslang
 
+from siliconcompiler.tools.slang import pyslang
 
 from siliconcompiler.tools.slang import SlangTask
 
@@ -18,6 +20,19 @@ class Elaborate(SlangTask):
             "true/false, if true add the source file path information",
             True)
 
+    def set_slang_includesourcepaths(self, enable: bool,
+                                     step: Optional[str] = None,
+                                     index: Optional[Union[int, str]] = None):
+        """
+        Enables or disables adding source file path information to the output.
+
+        Args:
+            enable (bool): True to include source paths, False to exclude.
+            step (str, optional): The specific step to apply this configuration to.
+            index (str, optional): The specific index to apply this configuration to.
+        """
+        self.set("var", "include_source_paths", enable, step=step, index=index)
+
     def task(self):
         return "elaborate"
 

siliconcompiler/tools/surelog/parse.py

@@ -3,6 +3,8 @@ import sys
 
 import os.path
 
+from typing import Optional
+
 from siliconcompiler import sc_open
 from siliconcompiler import utils
 
@@ -23,6 +25,58 @@ class ElaborateTask(Task):
         self.add_parameter("disable_note", "bool",
                            "true/false, when true instructs Surelog to not log notes.")
 
+    def set_surelog_enablelowmem(self, enable: bool,
+                                 step: Optional[str] = None,
+                                 index: Optional[str] = None):
+        """
+        Enables or disables low memory mode.
+
+        Args:
+            enable (bool): Whether to enable low memory mode.
+            step (str, optional): The specific step to apply this configuration to.
+            index (str, optional): The specific index to apply this configuration to.
+        """
+        self.set("var", "enable_lowmem", enable, step=step, index=index)
+
+    def set_surelog_disablewritecache(self, disable: bool,
+                                      step: Optional[str] = None,
+                                      index: Optional[str] = None):
+        """
+        Disables or enables writing to the cache.
+
+        Args:
+            disable (bool): Whether to disable writing to the cache.
+            step (str, optional): The specific step to apply this configuration to.
+            index (str, optional): The specific index to apply this configuration to.
+        """
+        self.set("var", "disable_write_cache", disable, step=step, index=index)
+
+    def set_surelog_disableinfo(self, disable: bool,
+                                step: Optional[str] = None,
+                                index: Optional[str] = None):
+        """
+        Disables or enables logging info messages.
+
+        Args:
+            disable (bool): Whether to disable logging info messages.
+            step (str, optional): The specific step to apply this configuration to.
+            index (str, optional): The specific index to apply this configuration to.
+        """
+        self.set("var", "disable_info", disable, step=step, index=index)
+
+    def set_surelog_disablenote(self, disable: bool,
+                                step: Optional[str] = None,
+                                index: Optional[str] = None):
+        """
+        Disables or enables logging note messages.
+
+        Args:
+            disable (bool): Whether to disable logging note messages.
+            step (str, optional): The specific step to apply this configuration to.
+            index (str, optional): The specific index to apply this configuration to.
+        """
+        self.set("var", "disable_note", disable, step=step, index=index)
+
     def tool(self):
         return "surelog"
 

siliconcompiler/tools/verilator/compile.py

@@ -1,4 +1,5 @@
 import shlex
+from typing import Optional, List, Union
 
 from siliconcompiler.tools.verilator import VerilatorTask
 
@@ -35,6 +36,125 @@ class CompileTask(VerilatorTask):
         self.add_parameter("initialize_random", "bool",
                            "true/false, when true registers will reset with a random value")
 
+    def set_verilator_mode(self, mode: str,
+                           step: Optional[str] = None,
+                           index: Optional[str] = None):
+        """
+        Sets the compilation mode for Verilator.
+
+        Args:
+            mode (str): The compilation mode.
+            step (str, optional): The specific step to apply this configuration to.
+            index (str, optional): The specific index to apply this configuration to.
+        """
+        self.set("var", "mode", mode, step=step, index=index)
+
+    def set_verilator_trace(self, enable: bool,
+                            step: Optional[str] = None,
+                            index: Optional[str] = None):
+        """
+        Enables or disables trace generation.
+
+        Args:
+            enable (bool): Whether to enable trace generation.
+            step (str, optional): The specific step to apply this configuration to.
+            index (str, optional): The specific index to apply this configuration to.
+        """
+        self.set("var", "trace", enable, step=step, index=index)
+
+    def set_verilator_tracetype(self, trace_type: str,
+                                step: Optional[str] = None,
+                                index: Optional[str] = None):
+        """
+        Sets the type of wave file to create when trace is enabled.
+
+        Args:
+            trace_type (str): The trace type.
+            step (str, optional): The specific step to apply this configuration to.
+            index (str, optional): The specific index to apply this configuration to.
+        """
+        self.set("var", "trace_type", trace_type, step=step, index=index)
+
+    def add_verilator_cincludes(self, include: Union[str, List[str]],
+                                step: Optional[str] = None,
+                                index: Optional[str] = None,
+                                clobber: bool = False):
+        """
+        Adds include directories for the C++ compiler.
+
+        Args:
+            include (Union[str, List[str]]): The include directory/directories to add.
+            step (str, optional): The specific step to apply this configuration to.
+            index (str, optional): The specific index to apply this configuration to.
+            clobber (bool, optional): If True, overwrites the existing list. Defaults to False.
+        """
+        if clobber:
+            self.set("var", "cincludes", include, step=step, index=index)
+        else:
+            self.add("var", "cincludes", include, step=step, index=index)
+
+    def add_verilator_cflags(self, flag: Union[str, List[str]],
+                             step: Optional[str] = None,
+                             index: Optional[str] = None,
+                             clobber: bool = False):
+        """
+        Adds flags for the C++ compiler.
+
+        Args:
+            flag (Union[str, List[str]]): The flag(s) to add.
+            step (str, optional): The specific step to apply this configuration to.
+            index (str, optional): The specific index to apply this configuration to.
+            clobber (bool, optional): If True, overwrites the existing list. Defaults to False.
+        """
+        if clobber:
+            self.set("var", "cflags", flag, step=step, index=index)
+        else:
+            self.add("var", "cflags", flag, step=step, index=index)
+
+    def add_verilator_ldflags(self, flag: Union[str, List[str]],
+                              step: Optional[str] = None,
+                              index: Optional[str] = None,
+                              clobber: bool = False):
+        """
+        Adds flags for the linker.
+
+        Args:
+            flag (Union[str, List[str]]): The flag(s) to add.
+            step (str, optional): The specific step to apply this configuration to.
+            index (str, optional): The specific index to apply this configuration to.
+            clobber (bool, optional): If True, overwrites the existing list. Defaults to False.
+        """
+        if clobber:
+            self.set("var", "ldflags", flag, step=step, index=index)
+        else:
+            self.add("var", "ldflags", flag, step=step, index=index)
+
+    def set_verilator_pinsbv(self, width: int,
+                             step: Optional[str] = None,
+                             index: Optional[str] = None):
+        """
+        Sets the datatype width for SystemC inputs/outputs.
+
+        Args:
+            width (int): The bit width.
+            step (str, optional): The specific step to apply this configuration to.
+            index (str, optional): The specific index to apply this configuration to.
+        """
+        self.set("var", "pins_bv", width, step=step, index=index)
+
+    def set_verilator_initializerandom(self, enable: bool,
+                                       step: Optional[str] = None,
+                                       index: Optional[str] = None):
+        """
+        Enables or disables random initialization of registers.
+
+        Args:
+            enable (bool): Whether to enable random initialization.
+            step (str, optional): The specific step to apply this configuration to.
+            index (str, optional): The specific index to apply this configuration to.
+        """
+        self.set("var", "initialize_random", enable, step=step, index=index)
+
     def task(self):
         return "compile"
 

siliconcompiler/tools/vivado/syn_fpga.py

@@ -1,3 +1,4 @@
+from typing import Optional
 from siliconcompiler.tools.vivado import VivadoTask
 
 
@@ -9,6 +10,32 @@ class SynthesisTask(VivadoTask):
         self.add_parameter("synth_directive", "str", "synthesis directive", defvalue="Default")
         self.add_parameter("synth_mode", "str", "synthesis mode", defvalue="none")
 
+    def set_vivado_synthdirective(self, directive: str,
+                                  step: Optional[str] = None,
+                                  index: Optional[str] = None):
+        """
+        Sets the synthesis directive.
+
+        Args:
+            directive (str): The synthesis directive.
+            step (str, optional): The specific step to apply this configuration to.
+            index (str, optional): The specific index to apply this configuration to.
+        """
+        self.set("var", "synth_directive", directive, step=step, index=index)
+
+    def set_vivado_synthmode(self, mode: str,
+                             step: Optional[str] = None,
+                             index: Optional[str] = None):
+        """
+        Sets the synthesis mode.
+
+        Args:
+            mode (str): The synthesis mode.
+            step (str, optional): The specific step to apply this configuration to.
+            index (str, optional): The specific index to apply this configuration to.
+        """
+        self.set("var", "synth_mode", mode, step=step, index=index)
+
     def task(self):
         return "syn_fpga"
 

siliconcompiler/tools/vpr/__init__.py

@@ -273,7 +273,7 @@ class VPRTask(Task):
                 self.add_required_key(lib, "fileset", fileset, "file", "sdc")
                 self.set("var", "enable_timing_analysis", True)
 
-        fpga = self.project.get("library", self.project.get("fpga", "device"), field="schema")
+        fpga = self.project.get_library(self.project.get("fpga", "device"))
         self.add_required_key(fpga, "tool", "vpr", "devicecode")
         self.add_required_key(fpga, "tool", "vpr", "clock_model")
         self.add_required_key(fpga, "tool", "vpr", "archfile")
@@ -287,7 +287,7 @@ class VPRTask(Task):
     def runtime_options(self):
         options = super().runtime_options()
 
-        fpga = self.project.get("library", self.project.get("fpga", "device"), field="schema")
+        fpga = self.project.get_library(self.project.get("fpga", "device"))
 
         options.extend(["--device", fpga.get("tool", "vpr", "devicecode")])
 
@@ -393,17 +393,17 @@ class VPRTask(Task):
         for report in glob.glob("*.rpt"):
             shutil.move(report, 'reports')
 
-        fpga = self.project.get("fpga", "device")
+        fpga = self.project.get_library(self.project.get("fpga", "device"))
 
         dff_cells = []
-        if self.project.valid("library", fpga, "tool", "yosys", "registers"):
-            dff_cells = self.project.get("library", fpga, "tool", "yosys", "registers")
+        if fpga.valid("tool", "yosys", "registers"):
+            dff_cells = fpga.get("tool", "yosys", "registers")
         brams_cells = []
-        if self.project.valid("library", fpga, "tool", "yosys", "brams"):
-            brams_cells = self.project.get("library", fpga, "tool", "yosys", "brams")
+        if fpga.valid("tool", "yosys", "brams"):
+            brams_cells = fpga.get("tool", "yosys", "brams")
         dsps_cells = []
-        if self.project.valid("library", fpga, "tool", "yosys", "dsps"):
-            dsps_cells = self.project.get("library", fpga, "tool", "yosys", "dsps")
+        if fpga.valid("tool", "yosys", "dsps"):
+            dsps_cells = fpga.get("tool", "yosys", "dsps")
 
         stat_extract = re.compile(r'  \s*(.*)\s*:\s*([0-9]+)')
         lut_match = re.compile(r'([0-9]+)-LUT')

siliconcompiler/tools/vpr/place.py

@@ -48,8 +48,7 @@ class PlaceTask(VPRTask):
             if files:
                 pcf_file = files[0]
 
-                fpga = self.project.get("library", self.project.get("fpga", "device"),
-                                        field="schema")
+                fpga = self.project.get_library(self.project.get("fpga", "device"))
                 map_file = fpga.find_files("tool", "vpr", "constraintsmap")
 
                 constraints_map = load_constraints_map(map_file)