siliconcompiler 0.33.2__py3-none-any.whl → 0.34.1__py3-none-any.whl

siliconcompiler/tools/vpr/vpr.py

@@ -43,7 +43,7 @@ def setup_tool(chip, clobber=True):
 
     chip.set('tool', 'vpr', 'exe', 'vpr', clobber=clobber)
     chip.set('tool', 'vpr', 'vswitch', '--version')
-    chip.set('tool', 'vpr', 'version', '>=9.0.0', clobber=clobber)
+    chip.set('tool', 'vpr', 'version', '>=v8.0.0-12677', clobber=clobber)
 
     step = chip.get('arg', 'step')
     index = chip.get('arg', 'index')
@@ -184,6 +184,7 @@ def runtime_options(chip):
         options.append("--sdc_file")
         options.append(sdc_file)
 
+    if use_timing_analysis(chip):
         report_type = chip.get('tool', tool, 'task', task, 'var', 'timing_report_type',
                                step=step, index=index)[0]
         options.extend(['--timing_report_detail', report_type])
@@ -297,20 +298,36 @@ def parse_version(stdout):
     # This is free open source code under MIT license.
     #
     #
-    return stdout.split()[6]
 
+    # Grab the revision. Which will be of the form:
+    #       v8.0.0-7887-gc4156f225
+    revision = stdout.split()[8]
 
-def normalize_version(version):
-    if '-' in version:
-        return version.split('-')[0]
+    # VTR infrequently makes even minor releases, use the number of commits
+    # since the last release of VTR as another part of the release segment.
+    pieces = revision.split("-")
+    if len(pieces) == 3:
+        # Strip off the hash if it exists.
+        return "-".join(pieces[:-1])
     else:
-        return version
+        return revision
 
 
 def auto_constraints():
     return 'inputs/sc_constraints.xml'
 
 
+def use_timing_analysis(chip):
+    '''
+    Return true if the given chip should use timing analysis in the VPR flow.
+    '''
+    step = chip.get('arg', 'step')
+    index = chip.get('arg', 'index')
+    return \
+        chip.valid('input', 'constraint', 'sdc') and \
+        chip.get('input', 'constraint', 'sdc', step=step, index=index)
+
+
 def vpr_post_process(chip):
     step = chip.get('arg', 'step')
     index = chip.get('arg', 'index')

siliconcompiler/tools/yosys/__init__.py

@@ -51,7 +51,7 @@ def setup(chip):
         option.append('-C')
     option.append('-c')
     chip.set('tool', tool, 'task', task, 'option', option, step=step, index=index, clobber=False)
-    chip.set('tool', tool, 'task', task, 'refdir', os.path.join('tools', tool),
+    chip.set('tool', tool, 'task', task, 'refdir', os.path.join('tools', tool, 'scripts'),
              step=step, index=index,
              package='siliconcompiler', clobber=False)
     chip.set('tool', tool, 'task', task, 'regex', 'warnings', "Warning:",

siliconcompiler/tools/yosys/scripts/procs.tcl

@@ -0,0 +1,143 @@
+# This file contains a set of procedures that are shared
+# between syn_asic.tcl and syn_fpga.tcl
+
+proc post_techmap { { opt_args "" } } {
+    # perform techmap in case previous techmaps introduced constructs
+    # that need techmapping
+    yosys techmap
+    # Quick optimization
+    yosys opt {*}$opt_args -purge
+}
+
+proc sc_map_memory { lib_file techmap_file do_rom } {
+    set design_mod 0
+
+    if { $lib_file != "" } {
+        yosys memory_libmap -lib $lib_file
+        set design_mod 1
+    }
+
+    if { $do_rom } {
+        yosys memory_map -rom-only
+        set design_mod 1
+    }
+
+    if { $techmap_file != "" } {
+        yosys techmap -map $techmap_file
+        set design_mod 1
+    }
+
+    return $design_mod
+}
+
+proc sc_apply_params { } {
+    global sc_design
+
+    yosys chparam -list $sc_design
+    if { [sc_cfg_exists option param] } {
+        yosys echo off
+        set module_params [yosys tee -q -s result.string chparam -list $sc_design]
+        yosys echo on
+
+        dict for {key value} [sc_cfg_get option param] {
+            if { ![string is integer $value] } {
+                set value [concat \"$value\"]
+            }
+
+            if { [string first $key $module_params] != -1 } {
+                yosys chparam -set $key $value $sc_design
+            } else {
+                puts "Warning: $key is not a defined parameter in $sc_design"
+            }
+        }
+    }
+}
+
+proc sc_get_scratchpad { name } {
+    yosys echo off
+    set value [yosys tee -q -s result.string scratchpad -get $name]
+    yosys echo on
+
+    return $value
+}
+
+proc sc_load_plugin { name } {
+    catch { yosys tee -q -s sc.load.test plugin -i $name }
+    set load_test [sc_get_scratchpad sc.load.test]
+    if { [string first "ERROR" $load_test] == -1 } {
+        return 1
+    }
+    return 0
+}
+
+proc sc_fpga_legalize_flops { feature_set } {
+    set legalize_flop_types []
+
+    if {
+        [lsearch -exact $feature_set enable] >= 0 &&
+        [lsearch -exact $feature_set async_set] >= 0 &&
+        [lsearch -exact $feature_set async_reset] >= 0
+    } {
+        lappend legalize_flop_types \$_DFF_P_
+        lappend legalize_flop_types \$_DFF_PN?_
+        lappend legalize_flop_types \$_DFFE_PP_
+        lappend legalize_flop_types \$_DFFE_PN?P_
+        lappend legalize_flop_types \$_DFFSR_PNN_
+        lappend legalize_flop_types \$_DFFSRE_PNNP_
+    } elseif {
+        [lsearch -exact $feature_set enable] >= 0 &&
+        [lsearch -exact $feature_set async_set] >= 0
+    } {
+        lappend legalize_flop_types \$_DFF_P_
+        lappend legalize_flop_types \$_DFF_PN1_
+        lappend legalize_flop_types \$_DFFE_PP_
+        lappend legalize_flop_types \$_DFFE_PN1P_
+    } elseif {
+        [lsearch -exact $feature_set enable] >= 0 &&
+        [lsearch -exact $feature_set async_reset] >= 0
+    } {
+        lappend legalize_flop_types \$_DFF_P_
+        lappend legalize_flop_types \$_DFF_PN0_
+        lappend legalize_flop_types \$_DFFE_PP_
+        lappend legalize_flop_types \$_DFFE_PN0P_
+    } elseif { [lsearch -exact $feature_set enable] >= 0 } {
+        lappend legalize_flop_types \$_DFF_P_
+        lappend legalize_flop_types \$_DFF_P??_
+        lappend legalize_flop_types \$_DFFE_PP_
+        lappend legalize_flop_types \$_DFFE_P??P_
+    } elseif {
+        [lsearch -exact $feature_set async_set] >= 0 &&
+        [lsearch -exact $feature_set async_reset] >= 0
+    } {
+        lappend legalize_flop_types \$_DFF_P_
+        lappend legalize_flop_types \$_DFF_PN?_
+        lappend legalize_flop_types \$_DFFSR_PNN_
+    } elseif { [lsearch -exact $feature_set async_set] >= 0 } {
+        lappend legalize_flop_types \$_DFF_P_
+        lappend legalize_flop_types \$_DFF_PN1_
+    } elseif { [lsearch -exact $feature_set async_reset] >= 0 } {
+        lappend legalize_flop_types \$_DFF_P_
+        lappend legalize_flop_types \$_DFF_PN0_
+    } else {
+        # Choose to legalize to async resets even though they
+        # won't tech map.  Goal is to get the user to fix
+        # their code and put in synchronous resets
+        lappend legalize_flop_types \$_DFF_P_
+        lappend legalize_flop_types \$_DFF_P??_
+    }
+
+    set legalize_list []
+    foreach flop_type $legalize_flop_types {
+        lappend legalize_list -cell $flop_type 01
+    }
+    yosys log "Legalize list: $legalize_list"
+    yosys dfflegalize {*}$legalize_list
+}
+
+proc sc_fpga_get_dsp_options { sc_syn_dsp_options } {
+    set option_text [list]
+    foreach dsp_option $sc_syn_dsp_options {
+        lappend option_text -D $dsp_option
+    }
+    return $option_text
+}

siliconcompiler/tools/yosys/{sc_synth_asic.tcl → scripts/sc_synth_asic.tcl}

@@ -507,6 +507,10 @@ yosys abc {*}$abc_args {*}$abc_dont_use
 ########################################################
 
 yosys clean -purge
+
+# Recheck hierarchy to remove all unused modules
+yosys hierarchy -top $sc_design
+
 yosys setundef -zero
 
 yosys splitnets

siliconcompiler/tools/yosys/{sc_synth_fpga.tcl → scripts/sc_synth_fpga.tcl}

@@ -57,9 +57,12 @@ if { [file exists $input_verilog] } {
         yosys read_slang \
             -D SYNTHESIS \
             --keep-hierarchy \
+            --ignore-assertions \
+            --allow-use-before-declare \
             --top $sc_design \
             {*}$slang_params \
             $input_verilog
+        yosys setattr -unset init
     } else {
         # Use -noblackbox to correctly interpret empty modules as empty,
         # actual black boxes are read in later
@@ -74,81 +77,6 @@ if { [file exists $input_verilog] } {
     }
 }
 
-####################
-# Helper functions
-####################
-proc legalize_flops { feature_set } {
-    set legalize_flop_types []
-
-    if {
-        [lsearch -exact $feature_set enable] >= 0 &&
-        [lsearch -exact $feature_set async_set] >= 0 &&
-        [lsearch -exact $feature_set async_reset] >= 0
-    } {
-        lappend legalize_flop_types \$_DFF_P_
-        lappend legalize_flop_types \$_DFF_PN?_
-        lappend legalize_flop_types \$_DFFE_PP_
-        lappend legalize_flop_types \$_DFFE_PN?P_
-        lappend legalize_flop_types \$_DFFSR_PNN_
-        lappend legalize_flop_types \$_DFFSRE_PNNP_
-    } elseif {
-        [lsearch -exact $feature_set enable] >= 0 &&
-        [lsearch -exact $feature_set async_set] >= 0
-    } {
-        lappend legalize_flop_types \$_DFF_P_
-        lappend legalize_flop_types \$_DFF_PN1_
-        lappend legalize_flop_types \$_DFFE_PP_
-        lappend legalize_flop_types \$_DFFE_PN1P_
-    } elseif {
-        [lsearch -exact $feature_set enable] >= 0 &&
-        [lsearch -exact $feature_set async_reset] >= 0
-    } {
-        lappend legalize_flop_types \$_DFF_P_
-        lappend legalize_flop_types \$_DFF_PN0_
-        lappend legalize_flop_types \$_DFFE_PP_
-        lappend legalize_flop_types \$_DFFE_PN0P_
-    } elseif { [lsearch -exact $feature_set enable] >= 0 } {
-        lappend legalize_flop_types \$_DFF_P_
-        lappend legalize_flop_types \$_DFF_P??_
-        lappend legalize_flop_types \$_DFFE_PP_
-        lappend legalize_flop_types \$_DFFE_P??P_
-    } elseif {
-        [lsearch -exact $feature_set async_set] >= 0 &&
-        [lsearch -exact $feature_set async_reset] >= 0
-    } {
-        lappend legalize_flop_types \$_DFF_P_
-        lappend legalize_flop_types \$_DFF_PN?_
-        lappend legalize_flop_types \$_DFFSR_PNN_
-    } elseif { [lsearch -exact $feature_set async_set] >= 0 } {
-        lappend legalize_flop_types \$_DFF_P_
-        lappend legalize_flop_types \$_DFF_PN1_
-    } elseif { [lsearch -exact $feature_set async_reset] >= 0 } {
-        lappend legalize_flop_types \$_DFF_P_
-        lappend legalize_flop_types \$_DFF_PN0_
-    } else {
-        # Choose to legalize to async resets even though they
-        # won't tech map.  Goal is to get the user to fix
-        # their code and put in synchronous resets
-        lappend legalize_flop_types \$_DFF_P_
-        lappend legalize_flop_types \$_DFF_P??_
-    }
-
-    set legalize_list []
-    foreach flop_type $legalize_flop_types {
-        lappend legalize_list -cell $flop_type 01
-    }
-    yosys log "Legalize list: $legalize_list"
-    yosys dfflegalize {*}$legalize_list
-}
-
-proc get_dsp_options { sc_syn_dsp_options } {
-    set option_text [list]
-    foreach dsp_option $sc_syn_dsp_options {
-        lappend option_text -D $dsp_option
-    }
-    return $option_text
-}
-
 set sc_partname [sc_cfg_get fpga partname]
 set build_dir [sc_cfg_get option builddir]
 set job_name [sc_cfg_get option jobname]
@@ -182,6 +110,25 @@ yosys hierarchy -top $sc_design
 
 if { [string match {ice*} $sc_partname] } {
     yosys synth_ice40 -top $sc_design -json "${sc_design}.netlist.json"
+} elseif {
+    [sc_cfg_exists fpga $sc_partname file yosys_fpga_config] &&
+    [llength [sc_cfg_get fpga $sc_partname file yosys_fpga_config]] != 0 &&
+    [sc_load_plugin yosys-syn]
+} {
+    set synth_fpga_args []
+    if { [lindex [sc_cfg_tool_task_get var synth_fpga_opt_mode] 0] != "none" } {
+        lappend synth_fpga_args \
+            -opt [lindex [sc_cfg_tool_task_get var synth_fpga_opt_mode] 0]
+    }
+    if { [lindex [sc_cfg_tool_task_get var synth_fpga_insert_buffers] 0] == "true" } {
+        lappend synth_fpga_args -insbuf
+    }
+
+    yosys synth_fpga \
+        -config [lindex [sc_cfg_get fpga $sc_partname file yosys_fpga_config] 0] \
+        -show_config \
+        -top $sc_design \
+        {*}$synth_fpga_args
 } else {
     # Pre-processing step:  if DSPs instance are hard-coded into
     # the user's design, we can use a blackbox flow for DSP mapping
@@ -252,7 +199,7 @@ if { [string match {ice*} $sc_partname] } {
             [sc_cfg_get fpga $sc_partname file yosys_dsp_techmap]
 
         yosys log "Run techmap flow for DSP Blocks"
-        set formatted_dsp_options [get_dsp_options $sc_syn_dsp_options]
+        set formatted_dsp_options [sc_fpga_get_dsp_options $sc_syn_dsp_options]
         yosys techmap -map +/mul2dsp.v -map $sc_syn_dsp_library \
             {*}$formatted_dsp_options
 
@@ -290,7 +237,7 @@ if { [string match {ice*} $sc_partname] } {
     yosys demuxmap
     yosys simplemap
 
-    legalize_flops $sc_syn_feature_set
+    sc_fpga_legalize_flops $sc_syn_feature_set
 
     if { [sc_cfg_exists fpga $sc_partname file yosys_flop_techmap] } {
         set sc_syn_flop_library \

siliconcompiler/tools/yosys/syn_fpga.py

@@ -43,6 +43,20 @@ def setup(chip):
              'true/false, if true will attempt to use the slang frontend',
              field='help')
 
+    chip.set('tool', tool, 'task', task, 'var', 'synth_fpga_opt_mode', 'none',
+             step=step, index=index,
+             clobber=False)
+    chip.set('tool', tool, 'task', task, 'var', 'synth_fpga_opt_mode',
+             'optimization mode for the synth_fpga command',
+             field='help')
+
+    chip.set('tool', tool, 'task', task, 'var', 'synth_fpga_insert_buffers', True,
+             step=step, index=index,
+             clobber=False)
+    chip.set('tool', tool, 'task', task, 'var', 'synth_fpga_insert_buffers',
+             'insert buffers as part of the synth_fpga command',
+             field='help')
+
     # Setup FPGA params
     part_name = chip.get('fpga', 'partname')
 

siliconcompiler/toolscripts/_tools.json

@@ -1,7 +1,7 @@
 {
   "openroad": {
     "git-url": "https://github.com/The-OpenROAD-Project/OpenROAD.git",
-    "git-commit": "cd121c095a6f77a501166e0961b2e93763c51b17",
+    "git-commit": "cef8746bc887f3da67bd964ad9061ca7a8b8903a",
     "docker-cmds": [
       "# Remove OR-Tools files",
       "RUN rm -f $SC_PREFIX/Makefile $SC_PREFIX/README.md",
@@ -17,7 +17,7 @@
   },
   "opensta": {
     "git-url": "https://github.com/parallaxsw/OpenSTA.git",
-    "git-commit": "0b59461bddb4ebc2228a20f17c9089be1f8c19da",
+    "git-commit": "cda30445d652c6d41f68732675ddbf28b5efeeab",
     "auto-update": true
   },
   "netgen": {
@@ -55,7 +55,7 @@
   },
   "sv2v": {
     "git-url": "https://github.com/zachjs/sv2v.git",
-    "git-commit": "380c2b978a54e459ac216c9e6b7f1a4e31573a0e",
+    "git-commit": "80a2f0cf685f6d873b4ee37b76e6c18dc60e2555",
     "auto-update": true
   },
   "verilator": {
@@ -76,7 +76,7 @@
   },
   "vpr": {
     "git-url": "https://github.com/verilog-to-routing/vtr-verilog-to-routing.git",
-    "git-commit": "c606a21d9ab5db53fb382a7dd79a0703c887108c",
+    "git-commit": "4bb340af8243b95efdea493d4cb58aed1099151f",
     "auto-update": false
   },
   "icepack": {
@@ -101,7 +101,7 @@
   },
   "yosys": {
     "git-url": "https://github.com/YosysHQ/yosys.git",
-    "git-commit": "v0.53",
+    "git-commit": "v0.54",
     "version-prefix": "",
     "auto-update": true
   },
@@ -151,7 +151,7 @@
   },
   "yosys-slang": {
     "git-url": "https://github.com/povik/yosys-slang.git",
-    "git-commit": "7da40107a513f0094d209ab3b0899f64e8dbeb0e",
+    "git-commit": "9d9ce7b767d2ea776e2dee0ef636a84512e6b229",
     "docker-depends": "yosys",
     "auto-update": true
   },
@@ -161,13 +161,9 @@
     "docker-depends": "yosys",
     "auto-update": true
   },
-  "yosys-parmys": {
-    "git-url": "https://github.com/verilog-to-routing/vtr-verilog-to-routing.git",
-    "git-commit": "c606a21d9ab5db53fb382a7dd79a0703c887108c",
-    "docker-depends": [
-      "yosys",
-      "vpr"
-    ],
+  "surfer": {
+    "git-url": "https://gitlab.com/surfer-project/surfer.git",
+    "git-commit": "v0.3.0",
     "auto-update": false
   }
 }

siliconcompiler/toolscripts/rhel9/install-vpr.sh

@@ -24,8 +24,6 @@ git submodule update --init --recursive
 
 sudo dnf config-manager --set-enabled devel || true
 ./install_dnf_packages.sh
-
-sudo yum install -y tbb-devel
 sudo dnf config-manager --set-disabled devel || true
 
 args=

siliconcompiler/toolscripts/ubuntu22/install-surfer.sh

@@ -0,0 +1,33 @@
+#!/bin/sh
+
+set -ex
+
+# Get directory of script
+src_path=$(cd -- "$(dirname "$0")" >/dev/null 2>&1 ; pwd -P)/..
+
+mkdir -p deps
+cd deps
+
+sudo apt-get install -y build-essential curl git libssl-dev openssl pkg-config
+
+USE_SUDO_INSTALL="${USE_SUDO_INSTALL:-yes}"
+if [ "${USE_SUDO_INSTALL:-yes}" = "yes" ]; then
+    SUDO_INSTALL=sudo
+else
+    SUDO_INSTALL=""
+fi
+
+curl --proto '=https' --tlsv1.2 -sSf https://sh.rustup.rs | sh -s - -y
+export PATH="$HOME/.cargo/bin:$PATH"
+
+git clone $(python3 ${src_path}/_tools.py --tool surfer --field git-url) surfer
+cd surfer
+git checkout $(python3 ${src_path}/_tools.py --tool surfer --field git-commit)
+git submodule update --init
+
+cargo fetch --locked
+cargo build -j $(nproc) --frozen --release
+
+if [ ! -z ${PREFIX} ]; then
+    $SUDO_INSTALL install -Dm00755 target/release/surfer -t ${PREFIX}/bin
+fi

siliconcompiler/toolscripts/ubuntu24/install-surfer.sh

@@ -0,0 +1,33 @@
+#!/bin/sh
+
+set -ex
+
+# Get directory of script
+src_path=$(cd -- "$(dirname "$0")" >/dev/null 2>&1 ; pwd -P)/..
+
+mkdir -p deps
+cd deps
+
+sudo apt-get install -y build-essential curl git libssl-dev openssl pkg-config
+
+USE_SUDO_INSTALL="${USE_SUDO_INSTALL:-yes}"
+if [ "${USE_SUDO_INSTALL:-yes}" = "yes" ]; then
+    SUDO_INSTALL=sudo
+else
+    SUDO_INSTALL=""
+fi
+
+curl --proto '=https' --tlsv1.2 -sSf https://sh.rustup.rs | sh -s - -y
+export PATH="$HOME/.cargo/bin:$PATH"
+
+git clone $(python3 ${src_path}/_tools.py --tool surfer --field git-url) surfer
+cd surfer
+git checkout $(python3 ${src_path}/_tools.py --tool surfer --field git-commit)
+git submodule update --init
+
+cargo fetch --locked
+cargo build -j $(nproc) --frozen --release
+
+if [ ! -z ${PREFIX} ]; then
+    $SUDO_INSTALL install -Dm00755 target/release/surfer -t ${PREFIX}/bin
+fi

siliconcompiler/utils/__init__.py

@@ -221,7 +221,8 @@ def default_email_credentials_file():
 
 @contextlib.contextmanager
 def sc_open(path, *args, **kwargs):
-    kwargs['errors'] = 'ignore_with_warning'
+    if 'errors' not in kwargs:
+        kwargs['errors'] = 'ignore'
     fobj = open(path, *args, **kwargs)
     try:
         with contextlib.closing(fobj):
@@ -329,29 +330,6 @@ def grep(chip, args, line):
         return line
 
 
-#######################################
-def get_env_vars(chip, step, index):
-    '''
-    Returns a dictionary of environmental variables from the manifest
-    '''
-
-    schema_env = {}
-    for env in chip.getkeys('option', 'env'):
-        schema_env[env] = chip.get('option', 'env', env)
-
-    flow = chip.get('option', 'flow')
-    if step is not None and index is not None and flow:
-        tool = chip.get('flowgraph', flow, step, str(index), 'tool')
-        task = chip.get('flowgraph', flow, step, str(index), 'task')
-
-        if chip.valid('tool', tool, 'task', task, 'env'):
-            for env in chip.getkeys('tool', tool, 'task', task, 'env'):
-                schema_env[env] = chip.get('tool', tool, 'task', task, 'env', env,
-                                           step=step, index=index)
-
-    return schema_env
-
-
 def get_plugins(system, name=None):
     '''
     Search for python modules with a specific function
@@ -370,6 +348,8 @@ def get_plugins(system, name=None):
 
 
 def truncate_text(text, width):
+    width = max(width, 5)
+
     if len(text) <= width:
         return text